1
Features
3.0V to 5.5V Operating Range
Lowest Power in It Class
Advanced Low-voltage, Zero-power, Electrically Erasable Programmable Logic Device
"Zero" Standby Power (25 A Maximum) (Input Transition Detection)
Low-voltage Equivalent of ATF22V10CZ
Ideal for Battery Powered Systems
CMOS- and TTL-compatible Inputs and Outputs
Inputs are 5V Tolerant
Latch Feature Hold Inputs to Previous Logic States
EE Technology
Reprogrammable
100% Tested
High-reliability CMOS Process
20-year Data Retention
10,000 Erase/Write Cycles
2,000V ESD Protection
200 mA Latch-up Immunity
Commercial and Industrial Temperature Ranges
Dual Inline and Surface Mount Standard Pinouts
Block Diagram
High-
performance
EE PLD
ATF22LV10CZ
ATF22LV10CQZ
Rev. 0779K04/01
Pin Configurations
All Pinouts Top View
Pin Name
Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
GND
Ground
VCC
(3 to 5.5V) Supply
TSSOP
Note:
TSSOP is the smallest package
of SPLD offering.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
PLCC
Note:
For PLCC, pins 1, 8, 15, and
22 can be left unconnected.
For superior performance,
connect VCC to pin 1 and
GND to pins 8, 15, and 22.
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
IN
IN
GND*
IN
IN
IN
I/O
I/O
I/O
GND*
I/O
I/O
I/O
4
3
2
1
28
27
26
12
13
14
15
16
17
18
IN
IN
GND
GND*
IN
I/O
I/O
IN
IN
CLK/IN
VCC*
VCC
I/O
I/O
ATF22LV10C(Q)Z
2
Description
The ATF22LV10CZ/CQZ is a high-performance CMOS
(electrically erasable) programmable logic device (PLD)
that utilizes Atmel's proven electrically erasable Flash
memory technology and provides 25 ns speed with standby
current of 25 A maximum. All speed ranges are specified
over the 3.0V to 5.5V range for industrial and commercial
temperature ranges.
The ATF22LV10CZ/CQZ provides a low-voltage and edge-
sensing "zero" power CMOS PLD solution with "zero"
standby power (5 A typical). The ATF22LV10CZ/CQZ
powers down automatically to the zero power mode
through Atmel's patented Input Transition Detection (ITD)
circuitry when the device is idle. The ATF22LV10CZ/CQZ
is capable of operating at supply voltages down to 3.0V.
Pin "keeper" circuits on input and output pins hold pins to
their previous logic levels when idle, which eliminate static
power consumed by pull-up resistors. The "CQZ" combines
this low high-frequency I
CC
of the "Q" design with the "Z"
feature.
The ATF22LV10CZ/CQZ macrocell incorporates a variable
product term architecture. Each output is allocated from 8
to 16 product terms which allows highly complex logic func-
tions to be realized. Two additional product terms are
included to provide synchronous reset and asynchronous
reset. These additional product terms are common to all 10
registers and are automatically cleared upon power-up.
Register Preload simplifies testing. A security fuse prevents
unauthorized copying of programmed fuse patterns.
Absolute Maximum Ratings*
Temperature under Bias .................................. -40C to +85C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
1.
Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
CC
+ 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65C to +150C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
during Programming .....................................-2.0V to +14.0V
(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
DC and AC Operating Conditions
Commercial
Industrial
Operating Temperature (Ambient)
0
C - 70C
-40
C - 85C
V
CC
Power Supply
3.0V - 5.5V
3.0V - 5.5V
ATF22LV10C(Q)Z
3
Functional Logic Diagram Description
T h e F u n c t i o n a l L o g i c D i a g r a m d e s c r i b e s t h e
ATF22LV10CZ/CQZ architecture.
The ATF22LV10CZ/CQZ has 12 inputs and 10 I/O macro-
cells. Each macrocell can be configured into one of four
output configurations: active high/low or registered/combi-
n a t o r i a l . T h e u n i v e r s a l a r c h i t e c t u r e o f t h e
ATF22LV10CZ/CQZ can be programmed to emulate most
24-pin PAL devices.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
w h e n p r o g r a m m e d , p r o t e c t s t h e c o n t e n t s o f t h e
ATF22LV10CZ/CQZ. Eight bytes (64 fuses) of User Signa-
ture are accessible to the user for purposes such as storing
project name, part number, revision or date. The User
Signature is accessible regardless of the state of the
security fuse.
Notes:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. For DC characterization, the test condition of V
CC
= Max corresponds to 3.6V.
DC Characteristics
Symbol
Parameter
Condition
(2)
Min
Typ
Max
Units
I
IL
Input or I/O Low
Leakage Current
0
V
IN
V
IL
(Max)
-10.0
A
I
IH
Input or I/O High
Leakage Current
(V
CC
- 0.2)V
V
IN
V
CC
10.0
A
I
CC
Clocked Power
Supply Current
V
CC
= Max
Outputs Open,
f = 15 MHz
CZ-25
Com.
50.0
85.0
mA
CZ-25
Ind.
55.0
90.0
mA
CQZ-30
Com.
18.0
50.0
mA
CQZ-30
Ind.
19.0
60.0
mA
I
SB
Power Supply Current,
Standby
V
CC
= Max
V
IN
= Max
Outputs Open
CZ-25
Com.
3.0
25.0
A
CZ-25
Ind.
4.0
50.0
A
CQZ-30
Com.
3.0
25.0
A
CQZ-30
Ind.
4.0
50.0
A
I
OS
(1)
Output Short Circuit
Current
V
OUT
= 0.5V
-130.0
mA
V
IL
Input Low Voltage
-0.5
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+ 0.75
V
V
OL
Output Low Voltage
V
IN
= V
IH
or V
IL
V
CC
= Min,
I
OL
= 16 mA
0.5
V
V
OH
Output High Voltage
V
IN
= V
IH
or V
IL
V
CCIO
= Min,
I
OH
= -2.0 mA
2.4
V
V
OH
Output High Voltage
I
OH
= -100 A
V
CC
- 0.2V
V
ATF22LV10C(Q)Z
4
AC Waveforms
Note:
1. See ordering information for valid part numbers.
INPUTS, I/O
REG. FEEDBACK
SYNCH. PRESET
CP
ASYNCH. RESET
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS
VALID
VALID
VALID
VALID
VALID
VALID
OUTPUT
DISABLED
OUTPUT
DISABLED
tS
tH
tW
tW
tP
tAR
tAW
tAP
tCO
tPD
tER
tEA
tEA
tER
AC Characteristics
(1)
Symbol
Parameter
-25
-30
Units
Min
Max
Min
Max
t
PD
Input or Feedback to Non-registered Output
3.0
25.0
10.0
30.0
ns
t
CF
Clock to Feedback
13.0
10.0
15.0
ns
t
CO
Clock to Output
2.0
15.0
4.0
20.0
ns
t
S
Input or Feedback Setup Time
15.0
18.0
ns
t
H
Input Hold Time
0
0
ns
t
P
Clock Period
25.0
30.0
ns
t
W
Clock Width
12.5
15.0
ns
f
MAX
External Feedback 1/(t
S
+ t
CO
)
Internal Feedback 1/(t
S
+ t
CF
)
No Feedback 1/(t
P
)
33.3
35.7
40.0
25.0
30.0
33.3
MHz
MHz
MHz
t
EA
Input to Output Enable
3.0
25.0
10.0
30.0
ns
t
ER
Input to Output Disable
3.0
25.0
10.0
30.0
ns
t
AP
Input or I/O to Asynchronous Reset of Register
3.0
25.0
10.0
3.0
ns
t
SP
Setup Time, Synchronous Preset
15.0
20.0
ns
t
AW
Asynchronous Reset Width
25.0
30.0
ns
t
AR
Asynchronous Reset Recovery Time
25.0
30.0
ns
t
SPR
Synchronous Preset to Clock Recovery Time
15.0
20.0
ns
ATF22LV10C(Q)Z
5
Input Test Waveforms and
Measurement Levels
Output Test Loads
Note:
Similar competitors devices are specified with slightly
different loads. These load differences may affect output
signals' delay and slew rate. Atmel devices are tested
with sufficient margins to meet compatible device specifi-
cation conditions.
Notes:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF22LV10CZ/CQZ are designed to
reset during power-up. At a point delayed slightly from V
CC
crossing V
RST
, all registers will be reset to the low state.
The output state will depend on the polarity of the buffer.
This feature is critical for state machine initialization.
However, due to the asynchronous nature of reset and the
uncertainty of how V
CC
actually rises in the system, the
following conditions are required:
1.
The V
CC
rise must be monotonic and start
below 0.7V.
2.
The clock must remain stable during T
PR
.
3.
After T
PR
, all input and feedback setup times must
be met before driving the clock pin high.
Preload of Register Outputs
The ATF22LV10CZ/CQZ's registers are provided with cir-
cuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can
be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF22LV10CZ/CQZ fuse patterns. Once pro-
grammed, fuse verify and preload are inhibited. However,
the 64-bit User Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
Programming/Erasing
Programming/erasing is pe rformed using standard
P L D p r o g r a m m e r s. S e e C M O S P L D P r o g r a m m i n g
Hardware & Software Support for information on software/
programming.
Pin Capacitance
f = 1 MHz, T = 25
C
(1)
Typ
Max
Units
Conditions
C
IN
5
8
pF
V
IN
= 0V
C
I/O
6
8
pF
V
OUT
= 0V
Parameter
Description
Typ
Max
Units
T
PR
Power-up
Reset Time
600
1000
ns
V
RST
Power-up
Reset Voltage
2.3
2.7
V
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