1
Features
Industry-standard Architecture
12 ns Maximum Pin-to-pin Delay
Zero Power 25
A Maximum Standby Power (Input Transition Detection)
CMOS and TTL Compatible Inputs and Outputs
Advanced Electrically-erasableTechnology
Reprogrammable
100% Tested
Latch Feature Holds Inputs to Previous Logic State
High-reliability CMOS Process
20 Year Data Retention
100 Erase/Write Cycles
2,000V ESD Protection
200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-line and Surface Mount Standard Pinouts
PCI Compliant
Block Diagram
Description
The ATF22V10CZ/CQZ is a high-performance CMOS (electrically-erasable)
programmable logic device (PLD) which utilizes Atmel's proven electrically-erasable
High-
performance
EE PLD
ATF22V10CZ
ATF22V10CQZ
Rev. 0778H03/01
Pin Configurations
All Pinouts Top View
Pin Name
Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
VCC
+5V Supply
TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
PLCC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
IN
IN
GND*
IN
IN
IN
I/O
I/O
I/O
GND*
I/O
I/O
I/O
4
3
2
1
28
27
26
12
13
14
15
16
17
18
IN
IN
GND
GND*
IN
I/O
I/O
IN
IN
CLK/IN
VCC*
VCC
I/O
I/O
DIP/SOIC
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
Note:
For PLCC, P1, P8, P15 and P22 can be left
unconnected. For superior performance, con-
nect VCC to pin 1 and GND to 8, 15, and 22.
(continued)
ATF22V10C(Q)Z
2
Flash memory technology. Speeds down to 12 ns with zero
standby power dissipation are offered. All speed ranges
are specified over the full 5V 10% range for industrial tem-
perature ranges; 5V 5% for commercial range 5-volt
devices. The ATF22V10CZ/CQZ provides a low voltage
and edge-sensing "zero" power CMOS PLD solution with
" z e r o " s t a n d b y p o w e r ( 5 A t y p i c a l ) . T h e
ATF22V10CZ/CQZ provides a "zero" power CMOS PLD
solution with 5V operating voltages, powering down auto-
matically to the zero power-mode through Atmel's patented
Input Transition Detection (ITD) circuitry when the device is
idle, offering "zero" (25 A worst case) standby power. This
feature allows the user to manage total system power to
meet specific application requirements and enhance reli-
ability. Pin "keeper" circuits on input and output pins elimi-
nate static power consumed by pull-up resistors. The
"CQZ" combines the low high-frequency I
CC
of the "Q"
design with the "Z" feature.
The ATF22V10CZ/CQZ incorporates a superset of the
generic architectures, which allows direct replacement of
the 22V10 family and most 24-pin combinatorial PLDs. Ten
outputs are each allocated 8 to 16 product terms. Three
different modes of operation, configured automatically
with software, allow highly complex logic functions to be
realized.
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40C to +85C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
1.
Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is V
CC
+ 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65C to +150C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
DC and AC Operating Conditions
Commercial
Industrial
Operating Temperature (Ambient)
0
C - 70C
-40
C - 85C
V
CC
Power Supply
5V
5%
5V
10%
Compiler Mode Selection
PAL Mode
(5828 Fuses)
GAL Mode
(5892 Fuses)
Synario
ATF22V10C (DIP)
ATF22V10C (PLCC)
ATF22V10C DIP (UES)
ATF22V10C PLCC (UES)
WINCUPL
P22V10
P22V10LCC
G22V10
G22V10LCC
ATF22V10C(Q)Z
3
Functional Logic Diagram Description
T h e F u n c t i o n a l L o g i c D i a g r a m d e s c r i b e s t h e
ATF22V10CZ/CQZ architecture.
The ATF22V10CZ/CQZ has 12 inputs and 10 I/O macro-
cells. Each macrocell can be configured into one of four
output configurations: active high/low, registered/combina-
t o r i a l o u t p u t . T h e u n i v e r s a l a r c h i t e c t u r e o f t h e
ATF22V10CZ/CQZ can be programmed to emulate most
24-pin PAL devices.
Unused product terms are automatically disabled by the
compiler to decrease power consumption. A security fuse,
w h e n p r o g r a m m e d , p r o t e c t s t h e c o n t e n t s o f t h e
ATF22V10CZ/CQZ. Eight bytes (64 fuses) of User Signa-
ture are accessible to the user for purposes such as storing
project name, part number, revision or date. The User Sig-
nature is accessible regardless of the state of the security
fuse.
Notes:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
I
IL
Input or I/O Low
Leakage Current
0
V
IN
V
IL
(Max)
3.5
V
IN
V
CC
-10
A
I
IH
Input or I/O High
Leakage Current
10
A
I
CC
Clocked Power
Supply Current
V
CC
= Max
Outputs Open,
f = 15 MHz
CZ-12, 15
Com
90
150
mA
CZ-15
Ind
90
180
mA
CQZ-20
Com
40
60
mA
CQZ-20
Ind
40
80
mA
I
SB
Power Supply Current,
Standby
V
CC
= Max
V
IN
= MAX
Outputs Open
CZ-12, 15
Com
5
25
A
CZ-15
Ind
5
50
A
CQZ-20
Com
5
25
A
CQZ-20
Ind
5
50
A
I
OS
(1)
Output Short Circuit
Current
V
OUT
= 0.5V
-130
mA
V
IL
Input Low Voltage
-0.5
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+ 0.75
V
V
OL
Output Low Voltage
V
IN
= V
IH
or V
IL
V
CC
= Min,
I
OL
= 16 mA
0.5
V
V
OH
Output High Voltage
V
IN
= V
IH
or V
IL
V
CCIO
= Min,
I
OH
= -4.0 mA
2.4
V
ATF22V10C(Q)Z
4
AC Waveforms
Note:
1. See ordering information for valid part numbers.
INPUTS, I/O
REG. FEEDBACK
SYNCH. PRESET
CP
ASYNCH. RESET
REGISTERED
OUTPUTS
COMBINATORIAL
OUTPUTS
VALID
VALID
VALID
VALID
VALID
VALID
OUTPUT
DISABLED
OUTPUT
DISABLED
tS
tH
tW
tW
tP
tAR
tAW
tAP
tCO
tPD
tER
tEA
tEA
tER
AC Characteristics
(1)
Symbol
Parameter
-12
-15
-20
Units
Min
Max
Min
Max
Min
Max
t
PD
Input or Feedback to Non-registered Output
3
12
3
15
3
20
ns
t
CF
Clock to Feedback
6
4.5
8
ns
t
CO
Clock to Output
2
8
2
8
2
12
ns
t
S
Input or Feedback Setup Time
10
10
14
ns
t
H
Input Hold Time
0
0
0
ns
t
W
Clock Width
6
6
10
ns
f
MAX
External Feedback 1/(t
S
+ t
CO
)
Internal Feedback 1/(t
S
+ t
CF
)
No Feedback 1/(t
P
)
55.5
62
83.3
55.5
69
83.3
38.5
45.5
50.0
MHz
MHz
MHz
t
EA
Input to Output Enable - Product Term
3
12
3
15
3
20
ns
t
ER
Input to Output Disable - Product Term
2
15
3
15
3
20
ns
t
PZX
OE Pin to Output Enable
2
12
2
15
2
20
ns
t
PXZ
OE Pin to Output Disable
2
15
2
15
2
20
ns
t
AP
Input or I/O to Asynchronous Reset of
Register
3
10
3
15
3
22
ns
t
SP
Setup Time, Synchronous Preset
10
10
14
ns
t
AW
Asynchronous Reset Width
7
8
20
ns
t
AR
Asynchronous Reset Recovery Time
5
6
20
ns
t
SPR
Synchronous Preset to Clock Recovery
Time
10
10
14
ns
ATF22V10C(Q)Z
5
Input Test Waveforms and
Measurement Levels
Output Test Loads
Note:
Similar competitors devices are specified with slightly
different loads. These load differences may affect output
signals' delay and slew rate. Atmel devices are tested
with sufficient margins to meet compatible device specifi-
cation conditions.
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF22V10CZ/CQZ are designed to
reset during power-up. At a point delayed slightly from V
CC
crossing V
RST
, all registers will be reset to the low state.
The output state will depend on the polarity of the buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how V
CC
actually rises in the system, the
following conditions are required:
1.
The V
CC
rise must be monotonic and start
below 0.7V.
2.
The clock must remain stable during T
PR
.
3.
After T
PR
occurs, all input and feedback setup times
must be met before driving the clock pin high.
Preload of Register Outputs
The ATF22V10CZ/CQZ's registers are provided with cir-
cuitry to allow loading of each register with either a high or
a low. This feature will simplify testing since any state can
be forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Electronic Signature Word
There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF22V10 CZ/CQZ fuse patterns. Once pro-
grammed, fuse verify and preload are inhibited. However,
the 64-bit User Signature remains accessible. The security
fuse should be programmed last, as its effect is immediate.
Programming/Erasing
Programming/erasing is pe rformed using standard
PLD programmers. See CMOS PLD Programming Hard-
ware & Software Support for information on software/pro-
gramming.
Pin Capacitance
f = 1 MHz, T = 25C
(1)
Typ
Max
Units
Conditions
C
IN
8
10
pF
V
IN
= 0V; f = 1.0 MHz
C
I/O
8
10
pF
V
OUT
= 0V; f = 1.0 MHz
Parameter
Description
Typ
Max
Units
T
PR
Power-up
Reset Time
600
1000
ns
V
RST
Power-up
Reset Voltage
3.8
4.5
V
C
LOCK
V
R
ST
POWER
REGISTERED
OUTPUTS
t
S
t
PR
t
W
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