1
Features
High-performance, High-density, Electrically-erasable Programmable Logic Device
Fully Connected Logic Array with 416 Product Terms
15 ns Maximum Pin-to-pin Delay for 5V Operation
24 Flexible Output Macrocells
48 Flip-flops Two per Macrocell
72 Sum Terms
All Flip-flops, I/O Pins Feed in Independently
D- or T-type Flip-flops
Product Term or Direct Input Pin Clocking
Registered or Combinatorial Internal Feedback
Backward Compatible with ATV2500B/BQ and ATV2500H Software
Advanced Electrically-erasable Technology
Reprogrammable
100% Tested
44-lead Surface Mount Package and DIP Package
Flexible Design: Up to 48 Buried Flip-flops and 24 Combinatorial Outputs
Simultaneously
8 Synchronous Product Terms
Individual Asynchronous Reset per Macrocell
OE Control per Macrocell
Functionality Equivalent to ATV2500B/BQ and ATV2500H
2000V ESD Protection
Security Fuse Feature to Protect the Code
Commercial and Industrial Temperature Range Offered
10 Year Data Retention
Pin Keeper Option
200 mA Latch-up Immunity
Block Diagram
ATF2500C
CPLD Family
Datasheet
ATF2500C
Rev. 0777IPLD4/03
Pin Configurations
Pin Name
Function
IN
Logic Inputs
CLK/IN
Pin Clock and Input
I/O
Bi-directional Buffers
I/O 0,2,4...
"Even" I/O Buffers
I/O 1,3,5...
"Odd" I/O Buffers
GND
Ground
VCC
+5V Supply
DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
CLK/IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
PLCC/LCC/JLCC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
6
5
4
3
2
1
44
43
42
41
40
18
19
20
21
22
23
24
25
26
27
28
I/O12
IN
IN
IN
IN
IN
IN
IN
GND
I/O18
I/O19
I/O1
I/O0
GND
IN
IN
CLK/IN
IN
IN
IN
IN
I/O6
Note:
(PLCC/LCC/JLCC packages) pin 4 and pin 26
GND connections are not required, but are rec-
ommended for improved noise immunity.
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ATF2500C Family
0777IPLD4/03
Description
The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully con-
nected logic array and flexible macrocell structure, high gate utilization is easily obtainable.
The ATF2500C is a high-performance CMOS (electrically-erasable) programmable logic
device (PLD) that utilizes Atmel's proven electrically-erasable technology.
The ATF2500C is organized around a single universal array. All pins and feedback terms are
always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out-
puts of each flip-flop.
In the ATF2500C, four product terms are input to each sum term. Furthermore, each macro-
cell's three sum terms can be combined to provide up to 12 product terms per sum term with
no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, pro-
viding further logic compaction. Also, 24 of the flip-flops may be bypassed to provide internal
combinatorial feedback to the logic array.
Product terms provide individual clocks and asynchronous resets for each flip-flop. The flip-
flops may also be individually configured to have direct input pin clocking. Each output has its
own enable product term. Eight synchronous preset product terms serve local groups of either
four or eight flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.
Using the
ATF2500C
Family's Many
Advanced
Features
The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:
Fully Connected Logic Array Each array input is always available to every product
term. This makes logic placement a breeze.
Selectable D- and T-Type Registers Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are
also easily created. These options allow more efficient product term usage.
Buried Combinatorial Feedback Each macrocell's Q2 register may be bypassed to
feed its input (D/T2) directly back to the logic array. This provides further logic expansion
capability without using precious pin resources.
Selectable Synchronous/Asynchronous Clocking Each of the ATF2500Cs flip-flops
has a dedicated clock product term. This removes the constraint that all registers use the
same clock. Buried state machines, counters and registers can all coexist in one device
while running on separate clocks. Individual flip-flop clock source selection further allows
mixing higher performance pin clocking and flexible product term clocking within one
design.
A Total of 48 Registers The ATF2500C provides two flip-flops per macrocell a total of
48. Each register has its own clock and reset terms, as well as its own sum term.
Independent I/O Pin and Feedback Paths Each I/O pin on the ATF2500C has a
dedicated input path. Each of the 48 registers has its own feedback term into the array as
well. These features, combined with individual product terms for each I/O's output enable,
facilitate true bi-directional I/O design.
Combinable Sum Terms Each output macrocell's three sum terms may be combined
into a single term. This provides a fan in of up to 12 product terms per sum term with
no
speed penalty.
Programmable Pin-keeper Circuits These weak feedback latches are useful for bus
interfacing applications. Floating pins can be set to a known state if the Pin-keepers are
enabled.
User Row (64 bits) Use to store information such as unit history.
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ATF2500C Family
0777IPLD4/03
Power-up Reset
The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed
slightly from V
CC
crossing V
RST
, all registers will be reset to the low state. The output state will
depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the uncertainty of how V
CC
actually rises
in the system, the following conditions are required:
1.
The V
CC
rise must be monotonic,
2.
After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and
3.
The clock pin, and any signals from which clock terms are derived, must remain stable
during t
PR
.
Parameter
Description
Typ
Max
Units
t
PR
Power-up Reset Time
600
1000
ns
V
RST
Power-up Reset Voltage
3.8
4.5
V
Level Forced on
Odd I/O Pin during
PRELOAD Cycle
Q Select Pin
State
Even/Odd
Select
Even Q1 State
after Cycle
Even Q2 State
after Cycle
Odd Q1 State
after Cycle
Odd Q2 State
after Cycle
V
IH
/V
IL
Low
Low
High/Low
X
X
X
V
IH
/V
IL
High
Low
X
High/Low
X
X
V
IH
/V
IL
Low
High
X
X
High/Low
X
V
IH
/V
IL
High
High
X
X
X
High/Low
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ATF2500C Family
0777IPLD4/03
Preload and
Observability of
Registered
Outputs
The ATF2500Cs registers are provided with circuitry to allow loading of each register asyn-
chronously with either a high or a low. This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A V
IH
level on the odd I/O pins will force the
appropriate register high; a V
IL
will force it low, independent of the polarity or other configura-
tion bit settings.
The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12
registers chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 10.25V to 10.75V signal on pin/lead 2.
In this mode, the contents of the buried register bank will appear on the associated outputs
when the OE control signals are active.
Programming
Software
Support
All family members of the ATF2500C can be designed with Atmel-WinCUPL
TM
. ProChip
Designer
support is expected soon. Check Atmel's web site for the latest version of ProChip.
Additionally, the ATF2500C may be programmed to perform the ATV2500Hs functional subset
(no T-type flip-flops, pin clocking or D/T2 feedback) using the ATV2500H JEDEC file. In this
case, the ATF2500C becomes a direct replacement or speed upgrade for the ATV2500H. The
ATF2500C are direct replacements for the ATV2500B/BQ and the ATV2500H, including the
lack of extra grounds on P4 and P26.
Security Fuse
Usage
A single fuse is provided to prevent unauthorized copying of ATF2500C fuse patterns. Once
programmed, the outputs will read programmed during verify.
The security fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits Preload and Q2 observability.
Bus-friendly
Pin-keeper
Input and I/O
All ATF2500C family members have programmable internal input and I/O pin-keeper circuits.
The default condition, including when using the AT2500C/CQ family to replace the
AT2500B/BQ or AT2500H, is that the pin-keepers are not activated.
When pin-keepers are active, inputs or I/Os not being driven externally will maintain their last
driven state. This ensures that all logic array inputs and device outputs are known states. Pin-
keepers are relatively weak active circuits that can be easily overridden by TTL-compatible
drivers (see input and I/O diagrams below).
Enabling or disabling of the pin-keeper circuits is controlled by the device type chosen in the
logic compiler device selection menu. Please refer to the Software Compiler Mode Selection
table for more details. Once the pin-keeper circuits are disabled, normal termination proce-
dures required for unused inputs and I/Os.
5
ATF2500C Family
0777IPLD4/03
Note:
The ATF2500C has 71816 Jedec fuses.
Input Diagram
Software Compiler Mode Selection
Device
Atmel - WinCupL Device Mnemonic
Pin-keeper
ATF2500C-DIP
V2500C
V2500CPPK
Disabled
Enabled
ATF2500C-PLCC
V2500LCC
V2500CPPKLCC
Disabled
Enabled
THIRD PARTY PROGRAMMER SUPPORT
Major Third Party Device Programmers support three types of JEDEC files.
Device
Description
ATF2500C (V2500)
V2500 Cross-programming. JEDEC file compatible with standard V2500
JEDEC file (Total fuses in JEDEC file = 71648). The Programmer will
automatically disable the User row fuses and also disable the pin-keeper
feature. The Fuse checksum will be the same as the old ATV2500H/L file.
This Device type is recommended for customers that are directly migrating
from an ATV2500H/L device to an ATF2500C device.
ATF2500C (V2500B)
V2500B Cross-programming. JEDEC file compatible with standard
V2500B JEDEC file (Total fuses in JEDEC file = 71745). The Programmer
will automatically disable the User row fuses and also disable the pin-
keeper feature. The Fuse checksum will be the same as the old
ATV2500B/BQ/BQL/BL file. This Device type is recommended for
customers that are directly migrating from an ATV2500B/BQ/BQL/BL
device to an ATF2500C device.
ATF2500C
Programming of User Row bits supported and Pin keeper bit is user-
programmable. (Total fuses in JEDEC file = 71816). This is the default
device type and is recommended for users that have Re-compiled their
Source Design files to specifically target the ATF2500C device.
PROGRAMMABLE
OPTION
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