1
Features
3.0V to 3.6V Operating Range
Advanced, High-speed, Electrically-erasable Programmable Logic Device
Superset of 22V10
Enhanced Logic Flexibility
Architecturally Compatible with ATV750B and ATV750 Software and Hardware
D- or T-type Flip-flop
Product Term or Direct Input Pin Clocking
15 ns Maximum Pin-to-pin Delay with 3V Operation
Highest Density Programmable Logic Available in 24-pin Package
Advanced Electrically-erasable Technology
Reprogrammable
100% Tested
Increased Logic Flexibility
42 Array Inputs, 20 Sum Terms and 20 Flip-flops
Enhanced Output Logic Flexibility
All 20 Flip-flops Feed Back Internally
10 Flip-flops are also Available as Outputs
Programmable Pin-keeper Circuits
Dual-in-line and Surface Mount Package in Standard Pinouts
Commercial and Industrial Temperature Ranges
20-year Data Retention
2000V ESD Protection
1000 Erase/Write Cycles
Block Diagram
Description
The Atmel "750" architecture is twice as powerful as most other 24-pin programmable
logic devices. Increased product terms, sum terms, flip-flops and output logic configu-
rations translate into more usable gates. High-speed logic and uniform, predictable
delays guarantee fast in-system performance. The ATF750LVC is a high-performance
PROGRAMMABLE
INTERCONNECT
AND
COMBINATORIAL
LOGIC ARRAY
LOGIC
OPTION
(UP T0 20
FLIP-FLOPS)
OUTPUT
OPTION
4 TO 8
PRODUCT
TERMS
(OE PRODUCT TERMS)
10
I/O
PINS
12
INPUT
PINS
(CLOCK PIN)
Rev. 1447D03/01
High-speed
Complex
Programmable
Logic Device
ATF750LVC
Pin Configurations
Pin Name
Function
CLK
Clock
IN
Logic Inputs
I/O
Bi-directional Buffers
GND
Ground
VCC
3V Supply
(continued)
DIP/SOIC/TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK/IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN
PLCC
5
6
7
8
9
10
11
25
24
23
22
21
20
19
IN
IN
IN
GND *
IN
IN
IN
I/O
I/O
I/O
GND *
I/O
I/O
I/O
4
3
2
1
28
27
26
12
13
14
15
16
17
18
IN
IN
GND
GND *
IN
I/O
I/O
IN
IN
CLK/IN
VCC *
VCC
I/O
I/O
Note:
For PLCC, pins 1, 8, 15, and 22
can be left unconnected. For
superior performance, connect
VCC to pin 1 and GND to pins
8, 15, and 22.
ATF750LVC
2
CMOS (electrically-erasable) complex programmable logic
device (CPLD) that utilizes Atmel's proven electrically-eras-
able technology.
Each of the ATF750LVC's 22 logic pins can be used as an
input. Ten of these can be used as inputs, outputs or bi-
directional I/O pins. Each flip-flop is individually config-
urable as either D- or T-type. Each flip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.
There are 171 total product terms available. There are two
sum terms per output, providing added flexibility. A variable
format is used to assign between four to eight product
terms per sum term. Much more logic can be replaced by
this device than by any other 24-pin PLD. With 20 sum
terms and flip-flops, complex state machines are easily
implemented with logic to spare.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individu-
ally configured to have direct input pin controlled clocking.
Each output has its own enable product term. One product
term provides a common synchronous preset for all flip-
flops. Register preload functions are provided to simplify
testing. All registers automatically reset upon power-up.
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40C to +85C
*NOTICE:
Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
1.
Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
CC
+ 0.75V DC,
which may overshoot to 4.6V for pulses of less
than 20 ns.
Storage Temperature ..................................... -65C to +150C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +4.6V
(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V
(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V
(1)
DC and AC Operating Conditions
3.3V Operation
Commercial
Industrial
Operating Temperature (Ambient)
0C - 70C
-40C - +85C
V
CC
Power Supply
3.0 - 3.6V
3.0 -
=3.6V
ATF750LVC
3
Clock Mux
Output Options
Bus-friendly Pin-keeper Input and I/Os
All input and I/O pins on the ATF750LVC(L) have program-
mable "pin-keeper" circuits. If activated, when any pin is
driven high or low and then subsequently left floating, it will
stay at that previous high or low level.
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which cause unnec-
essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
Enabling or disabling of the pin-keeper circuits is controlled
by the device type chosen in the logic compiler device
selection menu. Please refer to the software compiler table
for more details. Once the pin-keeper circuits are disabled,
normal termination procedures are required for unused
inputs and I/Os.
Input Diagram
I/O Diagram
SELECT
LOGIC
TO
CELL
CLOCK
PRODUCT
TERM
CLK
CKi
CK MUX
PIN
Table 1. Software Compiler Mode Selection
Synario
Wincupl
Pin-keeper Circuit
ATF750LVC
V750C
Disabled
ATF750LVC (PPK)
V750CPPK
Enabled
100K
V
CC
ESD
PROTECTION
CIRCUIT
INPUT
PROGRAMMABLE
OPTION
100K
V
CC
V
CC
DATA
OE
I/O
PROGRAMMABLE
OPTION
ATF750LVC
4
Notes:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. This test is performed at initial characterisation only.
Input Test Waveforms and
Measurement Levels
t
R
, t
F
< 3 ns (10% to 90%)
Output Test Load
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
I
LI
Input Load Current
V
IN
= -0.1V to V
CC
+ 1V
10
A
I
LO
Output Leakage
Current
V
OUT
= -0.1V to V
CC
+ 0.1V
10
A
I
CC
Power Supply
Current, Standby
V
CC
= Max,
V
IN
= Max,
Outputs Open
C-15
Com.
65
90
mA
Ind.
70
100
mA
I
OS
(1)(2)
Output Short
Circuit Current
V
OUT
= 0.5V
-120
mA
V
IL
Input Low Voltage
3.0
V
CC
3.6V
-0.6
0.8
V
V
IH
Input High Voltage
2.0
V
CC
+ 0.75
V
V
OL
Output Low
Voltage
V
IN
= V
IH
or V
IL
,
V
CC
= Min
I
OL
= 16 mA
Com., Ind.
0.5
V
I
OL
= 12 mA
Mil.
0.5
V
I
OL
= 24 mA
Com.
0.8
V
V
OH
Output High
Voltage
V
IN
= V
IH
or V
IL
,
V
CC
= Min
I
OH
= -2.0 mA
2.4
V
VCC
348
316
ATF750LVC
5
AC Waveforms, Product Term Clock
(1)
Note:
1.
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
Note:
1. See ordering information for valid part numbers.
AC Characteristics, Product Term Clock
(1)
Symbol
Parameter
-15
Units
Min
Max
t
PD
Input or Feedback to Non-registered Output
15
ns
t
EA
Input to Output Enable
15
ns
t
ER
Input to Output Disable
15
ns
t
CO
Clock to Output
5
12
ns
t
CF
Clock to Feedback
5
9
ns
t
S
Input Setup Time
8
ns
t
SF
Feedback Setup Time
7
ns
t
H
Hold Time
5
ns
t
P
Clock Period
14
ns
t
W
Clock Width
7
ns
f
MAX
External Feedback 1/(t
S
+ t
CO
)
50
MHz
Internal Feedback 1/(t
SF
+ t
CF
)
62
MHz
No Feedback 1/(t
P
)
71
MHz
t
AW
Asynchronous Reset Width
15
ns
t
AR
Asynchronous Reset Recovery Time
15
ns
t
AP
Asynchronous Reset to Registered Output Reset
15
ns
t
SP
Setup Time, Synchronous Preset
8
ns
PDF 
ZIP