1
Features
Utilizes the AVR
Enhanced RISC Architecture
121 Powerful Instructions - Most Single Clock Cycle Execution
128K bytes of In-System Reprogrammable Flash ATmega103/L
64K bytes of In-System Reprogrammable Flash ATmega603/L
SPI Interface for In-System Programming
Endurance: 1,000 Write/Erase Cycles
4K bytes EEPROM ATmega103/L
2K bytes of EEPROM ATmega603/L
Endurance: 100,000 Write/Erase Cycles
4K bytes Internal SRAM
32 x 8 General Purpose Working Registers + Peripheral Control Registers
32 Programmable I/O Lines, 8 Output Lines, 8 Input Lines
Programmable Serial UART + SPI Serial Interface
V
CC
Supply
2.7 - 3.6V ATmega603L/ATmega103L
4.0 - 5.5V ATmega603/ATmega103
Fully Static Operation
0 - 6 MHz ATmega603/ATmega103
0 - 4 MHz ATmega603L/ATmega103L
Up to 6 MIPS Throughput at 6 MHz
RTC with Separate Oscillator
Two 8-Bit Timer/Counters with Separate Prescaler and PWM
One 16-Bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and
Dual 8-, 9- or 10-Bit PWM
Programmable Watchdog Timer with On-Chip Oscillator
On-Chip Analog Comparator
8-Channel, 10-Bit ADC
Low Power Idle, Power Save and Power Down Modes
Software Selectable Clock Frequency
Programming Lock for Software Security
Pin Configuration
Rev. 0945BS09/98
8-Bit
Microcontroller
with 64K/128K
Bytes In-System
Programmable
Flash
ATmega603
ATmega603L
ATmega103
ATmega103L
Preliminary
ATmega103/L
ATmega103/L
TQFP
Note:
This is a summary document. For the complete 92
page document, please visit our web site at
www.atmel.com or e-mail at literature@atmel.com
and request literature #0945B.
ATmega603(L) and ATmega103(L)
2
Block Diagram
Figure 1. The ATmega603/103 Block Diagram
Description
The ATmega603/103 is a low-power CMOS 8-bit microcon-
troller based on the
AVR
enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the
ATmega603/103 achieves throughputs approaching 1
MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
The AVR core is based on an enhanced RISC architecture
that combines a rich instruction set with 32 general purpose
working registers. All the 32 registers are directly con-
nected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruc-
tion executed in one clock cycle. The resulting architecture
is more code efficient while achieving throughputs up to ten
times faster than conventional CISC microcontrollers.
The ATmega603/103 provides the following features:
64K/128K bytes of In-system Programmable Flash, 2K/4K
bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O
lines, 8 Input lines, 8 Output lines, 32 general purpose
working registers, 4 flexible timer/counters with compare
modes and PWM, UART, programmable Watchdog Timer
with internal oscillator, an SPI serial port and three software
selectable power saving modes. The Idle Mode stops the
CPU while allowing the SRAM, timer/counters, SPI port
and interrupt system to continue functioning. The Power
PROGRAM
COUNTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
STACK
POINTER
PROGRAM
FLASH
MCU CONTROL
REGISTER
SRAM
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTERS
INSTRUCTION
DECODER
DATA DIR.
REG. PORTB
DATA DIR.
REG. PORTE
DATA DIR.
REG. PORTA
DATA DIR.
REG. PORTD
DATA REGISTER
PORTB
DATA REGISTER
PORTE
DATA REGISTER
PORTA
DATA REGISTER
PORTC
DATA REGISTER
PORTD
PROGRAMMING
LOGIC
TIMING AND
CONTROL
OSCILLATOR
OSCILLATOR
INTERRUPT
UNIT
EEPROM
SPI
UART
STATUS
REGISTER
Z
Y
X
ALU
PORTB DRIVER/BUFFERS
PORTE DRIVER/BUFFERS
PORTA DRIVER/BUFFERS
PORTF BUFFERS
ANALOG MUX
ADC
PORTD DRIVER/BUFFERS
PORTC DRIVERS
PB0 - PB7
PE0 - PE7
PA0 - PA7
PF0 - PF7
RESET
VCC
VCC
AGND
GND
GND
AREF
TOSC2
TOSC1
XTAL1
XTAL1
CONTROL
LINES
+
-
ANALOG
COMP
ARA
T
O
R
PD0 - PD7
PC0 - PC7
PEN
ALE
WR
RD
8-BIT DATA BUS
AVCC
ATmega603(L) and ATmega103(L)
3
Down mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next
interrupt or hardware reset. In Power Save mode, the timer
oscillator continues to run, allowing the user to maintain a
timer base while the rest of the device is sleeping.
The device is manufactured using Atmel's high-density
non-volatile memory technology. The on-chip ISP Flash
allows the program memory to be reprogrammed in-system
through a serial interface or by a conventional nonvolatile
memory programmer. By combining an 8-bit RISC CPU
with a large array of ISP Flash on a monolithic chip, the
Atmel ATmega603/103 is a powerful microcontroller that
provides a highly flexible and cost effective solution to
many embedded control applications.
The ATmega603/103 AVR is supported with a full suite of
program and system development tools including: C com-
pilers, macro assemblers, program debugger/simulators,
in-circuit emulators, and evaluation kits.
Comparison Between ATmega 603 and
ATmega 103
The ATmega603 has 64K bytes of In-System Programma-
ble Flash, 2K bytes of EEPROM, and 4K bytes of internal
SRAM. The ATmega603 does not have the ELPM instruc-
tion.
The ATmega103 has 128K bytes of In-System Program-
mable Flash, 4K bytes of EEPROM, and 4K bytes of inter-
nal SRAM. The ATmega103 has the ELPM instruction,
necessary to reach the upper half of the Flash memory for
constant table lookup.
Table 1 summarizes the different memory sizes for the two
devices.
Pin Descriptions
VCC
Supply voltage
GND
Ground
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port. Port pins can pro-
vide internal pull-up resistors (selected for each bit). The
Port A output buffers can sink 20 mA and can drive LED
displays directly. When pins PA0 to PA7 are used as inputs
and are externally pulled low, they will source current if the
internal pull-up resistors are activated.
Port A serves as Multiplexed Address/Data bus when using
external SRAM.
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O pins with internal pull-up
resistors. The Port B output buffers can sink 20 mA. As
inputs, Port B pins that are externally pulled low, will source
current if the pull-up resistors are activated.
Port B also serves the functions of various special features.
Port C (PC7..PC0)
Port C is an 8-bit Output port. The Port C output buffers can
sink 20 mA.
Port C also serves as Address output when using external
SRAM.
Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up
resistors. The Port D output buffers can sink 20 mA. As
inputs, Port D pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port D also serves the functions of various special features.
Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up
resistors. The Port E output buffers can sink 20 mA. As
inputs, Port E pins that are externally pulled low will source
current if the pull-up resistors are activated.
Port E also serves the functions of various special features.
Port F (PF7..PF0)
Port F is an 8-bit Input port. Port F also serves as the ana-
log inputs for the ADC.
RESET
input. A low on this pin for two machine cycles while the
oscillator is running resets the device.
XTAL1
Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier
TOSC1
Input to the inverting Timer/Counter oscillator amplifier
TOSC2
Output from the inverting Timer/Counter oscillator amplifier
WR
External SRAM Write Strobe.
RD
External SRAM Read Strobe.
ALE
ALE is the Address Latch Enable used when the External
Memory is enabled. The ALE strobe is used to latch the
low-order address (8 bits) into an address latch during the
Table 1. Memory Size Summary
Part
Flash
EEPROM
SRAM
ATmega603
64K bytes
2K bytes
4K bytes
ATmega103
128K bytes
4K bytes
4K bytes
ATmega603(L) and ATmega103(L)
4
first access cycle, and the AD0-7 pins are used for data
during the second access cycle.
AV
CC
This is the supply voltage to the A/D Converter. It should be
externally connected to V
CC
via a low-pass filter. See
page 53 for details on operation of the ADC.
AREF
This is the analog reference input for the ADC converter.
For ADC operations, a voltage in the range AGND to AVCC
must be applied to this pin.
AGND
If the board has a separate analog ground plane, this pin
should be connected to this ground plane. Otherwise, con-
nect to GND.
PEN
This is a programming enable pin for the low-voltage serial
programming mode. By holding this pin low during a power-
on reset, the device will enter the serial programming
mode.
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an
inverting amplifier which can be configured for use as an
on-chip oscillator, as shown in Figure 2. Either a quartz
crystal or a ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 3.
For the Timer Oscillator pins, OSC1 and OSC2, the crystal
is connected directly between the pins. No external capaci-
tors are needed. The oscillator is optimized for use with a
32,768Hz watch crystal. An external clock signal applied to
this pin goes through the same amplifier having a band-
width of 256kHz. The external clock signal should therefore
be in the interval 0Hz - 256kHz.
Figure 2. Oscillator Connections
Figure 3. External Clock Drive Configuration
ATmega603/103 Architectural Overview
The fast-access register file contains 32 x 8-bit general pur-
pose working registers with a single clock cycle access
time. This means that during one single clock cycle, one
ALU (Arithmetic Logic Unit) operation is executed. Two
operands are output from the register file, the operation is
executed, and the result is stored back in the register file -
in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect
address register pointers for Data Space addressing -
enabling efficient address calculations. One of the three
address pointers is also used as the address pointer for the
constant table look up function. These added function reg-
isters are the 16-bit X-register, Y-register and Z-register.
The ALU supports arithmetic and logic functions between
registers or between a constant and a register. Single reg-
ister operations are also executed in the ALU. Figure 4
shows the ATmega603/103 AVR Enhanced RISC micro-
controller architecture.
In addition to the register operation, the conventional mem-
ory addressing modes can be used on the register file as
well. This is enabled by the fact that the register file is
assigned the 32 lowermost Data Space addresses, allow-
ing them to be accessed as though they were ordinary
memory locations.
The I/O memory space contains 64 addresses for CPU
peripheral functions as Control Registers, Timer/Counters,
A/D-converters, and other I/O functions. The I/O Memory
can be accessed directly, or as the Data Space locations
following those of the register file, $20 - $5F.
C2
XTAL2
GND
XTAL1
C1
XTAL2
XTAL1
GND
NC
EXTERNAL
OSCILLATOR
SIGNAL
ATmega603(L) and ATmega103(L)
5
Figure 4. The ATmega603/103 AVR Enhanced RISC Architecture
The AVR uses a Harvard architecture concept - with sepa-
rate memories and buses for program and data. The pro-
gram memory is executed with a single level pipelining.
While one instruction is being executed, the next instruction
is pre-fetched from the program memory. This concept
enables instructions to be executed in every clock cycle.
The program memory is in-system programmable Flash
memory. With a few exceptions, AVR instructions have a
single 16-bit word format, meaning that every program
memory address contains a single 16-bit instruction.
During interrupts and subroutine calls, the return address
program counter (PC) is stored on the stack. The stack is
effectively allocated in the general data SRAM, and conse-
quently the stack size is only limited by the total SRAM size
and the usage of the SRAM. All user programs must initial-
ize the SP in the reset routine (before subroutines or inter-
rupts are executed). The 16-bit stack pointer SP is
read/write accessible in the I/O space.
The 4000 bytes data SRAM can be easily accessed
through the five different addressing modes supported in
the AVR architecture.
A flexible interrupt module has its control registers in the
I/O space with an additional global interrupt enable bit in
the status register. All the different interrupts have a sepa-
rate interrupt vector in the interrupt vector table at the
beginning of the program memory. The different interrupts
have priority in accordance with their interrupt vector posi-
tion. The lower the interrupt vector address, the higher the
priority.
The memory spaces in the AVR architecture are all linear
and regular memory maps.
The General Purpose Register File
Figure 5 shows the structure of the 32 general purpose
working registers in the CPU.
32K/64K x 16
Program
Memory
Instruction
Register
Instruction
Decoder
Program
Counter
Control Lines
32 x 8
General
Purpose
Registers
ALU
Status
and Test
2K/4K x 8
EEPROM
Peripherals
Data Bus 8-bit
AVR ATmega603/103 Architecture
4K x 8
Data
SRAM
DirectAddressing
IndirectAddressing
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