1
Features
Interfaces Directly to Instrument Hardware
Keyboard Velocity Scanner (Up to 88 Keys, 64 s Time Accuracy, Log Timescale)
Switch Scanner (Up to 176 Switches)
LED Display Controller (Up to 88 LEDs)
Slider Scanner (Built-in ADC, Up to 16 Sliders)
LCD Display (8-bit Interface)
Crisp Musical Response
45 MHz Built-in 16-bit Microcontroller
Interface with Keyboard/Switches through Built-in Shared Memory
High-quality Sound
64-slot Digital Sound Synthesizer/Processor
Multi-algorithm: PCM with Dynamic LP Filter, FM, Delay Lines for Effects,
Equalizer, Surround, Digital Audio-in Processing
Compatible with ATSAM97xx Sounds and Firmware
44.1 kHz Sampling Rate
Up to 16 MB x 16 ROM/RAM for Firmware, Orchestration and PCM Data
Up to 4 Channels Audio-out, 2 Channels Audio-in
Top Technology
144-lead TQFP Space-saving Package
Single 11.2896 MHz Crystal Operation, Built-in PLL Minimizes RFI
Available Soundbanks for General MIDI
(GM)
(1)
or High-quality Piano
CleanWave
1-Mbyte and 4-Mbyte Sample Sets (Free License)
High-quality 2-Mbyte Piano and Strings Sample Sets
Other Sample Sets Available Under Special Licensing Conditions
Quick Time-to-market
Proven Reliable Synthesis Drivers
In-circuit Emulation with CodeView Debugger for Easy Prototype Development
Built-in External Flash Programming Algorithm, Allows On-board Flash
Programming
All Existing ATSAM97xx Tools Available for Sound and Sound-bank Development
Note:
1. General MIDI requires a license from Midi Manufacturers Association.
Description
The ATSAM9753 integrates into a single chip an ATSAM97xx core (64-slot DSP and
16-bit processor), a 32K x 16 RAM, an LCD display interface and a scanner, allowing
direct connection to velocity-sensitive keyboards, switches, LEDs and sliders. With the
addition of a single external ROM or Flash and a stereo DAC, a complete low-cost
musical instrument can be built that includes reverb and chorus effects, parametric
equalizer, surround effects, orchestrations, pitch-bend and wheel controller, without
compromising on sound quality. The ATSAM9753 is packaged in a standard 144-lead
TQFP package.
Sound
Synthesis
ATSAM9753
Integrated
Digital Music
Instrument
Rev. 1774DDRMSD11/02
2
ATSAM9753
1774DDRMSD11/02
Figure 1. Typical Application for the ATSAM9753
Figure 2. ATSAM9753 Block Diagram
ROM
ATSAM9753
DAC
Keyboards
Switches
LEDs
LCD Display
Sliders
MIDI_IN/MIDI_OUT
P16 Processor
256 x 16 RAM
512 x 16 ROM
64-slot DSP
with
Algorithms
in RAM
32K x 16
SRAM
Memory
Management
Unit
MIDI UART
3 x Timers
Control and
Status Regs
128 x 16
Scanning
RAM
Keyboards
Switches
Sliders
LEDs
Scanning I/F
Clock
and
PLL
8-bit
ADC
LCD
Display
Interface
DACLK
DABD[1:0]
DAAD
CLBD
WSBD
RUN
WA[23:0]
WD[15:0]
RD
WR
CS[1:0]
XIO[1:0]
MIDI_IN
MIDI_OUT
GPIO[4:0]
VREFP
VREFN
VIN
RS
RW
ENB
DB[7:0]
KBDIO
ROW[2:0]
BR[10:0]
MK[10:0]
X1
X2
LFT
RESET
PDWN
DEBUG
3
ATSAM9753
1774DDRMSD11/02
Pin Description
Table 1. Pin Description by Function
Pin Name
Pin Number
Type
Function
Power Supply
(1)
GND
4, 17, 24, 32, 42, 52, 56,
65, 77, 90, 97, 102, 110,
125, 130, 140
PWR
Digital Ground
All pins should be connected to a ground plane.
AGND
103
PWR
Analog Ground for the ADC
VCC
5, 18, 31, 41, 51, 66, 78,
91, 111, 126, 139
PWR
Power Supply, 3.3V/5V 10%
All pins should be connected to a V
CC
plane.
VC3
23, 55, 96, 101, 129
PWR
Core power, +3.3V nominal (3.3V 10%).
All V
C3
pins should be returned to +3.3V.
AVC3
107
PWR
Analog power for the ADC, +3.3V nominal (3.3V 10%)
Serial MIDI
MIDI_IN
94
IN
Serial MIDI_IN
MIDI_OUT
95
OUT
Serial MIDI_OUT
External PCM ROM/RAM/I/O
WA[23:0]
47 - 50, 53, 54, 57 - 64,
67 - 76
OUT
External memory I/O address. Up to 16M x 16 for direct ROM/RAM
connection.
WD[15:0]
19 - 22, 25 - 30, 33 - 38
I/O
External memory I/O data. Data is read (input) when RD is low, written
(output) when WR is low.
RD
39
OUT
External ROM/RAM/peripherals read
WR
40
OUT
External RAM/peripherals write
CS[1:0]
43, 44
OUT
Programmable chip selects. Can be configured to handle several ROMs or
mixed RAM/ROM/FLASH.
XIO[1:0]
45, 46
OUT
External peripherals chip select. Each peripheral maps onto 4K bytes
address space for optional further decoding.
Keyboard, Switches, LEDs, Sliders, Scanning
KBDIO
119
OUT
If 1: BR[10:0] and MK[10:0] hold keyboard contact input data.
If 0: BR[10:0] holds switch status input, MK[10:0] holds LED data output.
ROW[2:0]
115 - 117
OUT
Row select: Keyboard, switches/LEDs, external slider analog multiplexer
(4051) channel select. Eight rows combined with eleven BR/MK columns
allow to control 88 keys, 88 switches, 88 LEDs and 8 sliders. The
programmable bit GPIO0 allows control to be extended to 176 switches and
16 sliders when programmed as ROW3.
4
ATSAM9753
1774DDRMSD11/02
BR[10:0]
1 - 3, 135 - 138, 141 - 144
IN
Keyboard contact 1/switch status. When KBDIO = 1 then BR[10:0] holds the
keyboard key-off or first contact status. This can be configured as normally
closed (spring type), normally open (rubber type), common anode or
common cathode contact diodes. When KBDIO = 0 then BR[10:0] holds the
switch status from ROW[2:0] or ROW[3:0].
MK[10:0]
120 - 124,127, 128,
131 - 134
I/O
Keyboard contact 2/LED data. When KBDIO =1 then MK[10:0] holds the
keyboard key-on or second contact status. This can be configured as
common anode or common cathode contact diodes.When KBDIO = 1 then
MK[10:0] holds the led data from ROW[2:0].
VREFP
106
ANA
Positive reference voltage. Should normally be connected to a clean AV
C3
supply.
VREFN
105
ANA
Negative reference voltage. Should normally be connected to a clean AGND.
VIN
104
ANA
Slider analog input. Ranges from VREFN to VREFP. Should hold the
ROW[2:0] or ROW[3:0] slider voltage. Multiple sliders should be connected
through external analog multiplexer(s) like 4051.
LCD Display Interface
(2)
RS
16
OUT
Select instruction (LOW) or data (HIGH).
RW
15
OUT
Select write (LOW) or read (HIGH).
ENB
14
OUT
Enable, active high.
DB[7:0]
6 - 13
I/O
Bi-directional data bus.
Digital Audio Group
(3)
DACLK
93
OUT
Master clock for sigma-delta DAC (256 x Fs).
DABD[1:0]
89, 92
OUT
Serial data for two stereo output channels.
DAAD
88
IN
Serial data for one stereo input channel.
CLBD
86
OUT
Digital audio bit clock.
WSBD
87
OUT
Digital audio left/right select.
Miscellaneous Pins
GPIO[4:0]
108, 109, 112 - 114
I/O
These pins can be used individually as general-purpose I/Os or as alternate
functions. When used as general-purpose I/Os, they can be individually
configured as inputs or outputs. When used as alternate functions their
meaning changes as follows:
GPIO0 = ROW3 expands switches to 176, sliders to 16
GPIO2 = DBCLK (input)
GPIO3 = DBACK (output)
GPIO4 = DBDATA (I/O) (DBDATA input = DBIN, DBDATA output = DBOUT)
DBCLK, DBACK, DBDATA are used for debugging or external Flash memory
programming when DEBUG is low
DEBUG
85
IN
Configuration pin, low for CodeView debugging/external Flash memory
programming. Should be tied to V
CC
for normal operation.
RESET
83
IN
Reset input, active low. This is a Schmitt trigger input, allowing direct
connection of a RC network.
RUN
118
OUT
Indicates that the DSP is up and running. Can be used as external DAC
reset.
Table 1. Pin Description by Function (Continued)
Pin Name
Pin Number
Type
Function
5
ATSAM9753
1774DDRMSD11/02
Notes:
1. Like all high-speed HCMOS ICs proper decoupling is mandatory for reliable operation and RFI reduction. The recommended
decoupling is 100 nF at each corner of the IC with an additional 10 F bulk capacitor close to the X1, X2 pins.
2. The LCD display interface signals are controlled by firmware, therefore, their timing relationship is determined by firmware
only.
3. The ATSAM9753 connects to a variety of stereo DACs or Codecs from 16 to 20 bits, with Japanese or I
2
S format. This
includes AD1857JRS, AK4352, AK4393, AK4528, PCM1718, PCM1739, PCM3001, TDA1543, TDA1545 . When Japanese
format is used, only 16 bits is supported without external circuitry.
PDWN
84
IN
Power down, active low. When power down is active, all output pins are
floating except GPIO1. The crystal oscillator is stopped. To exit from power-
down mode, PDWN should be high and RESET applied.
X1
X2
98, 99
11.2896 MHz (nominal) crystal connection. An external clock can also be
used at X1.
TEST[3:0]
79 - 82
IN
Test pins, should be grounded
LFT
100
PLL external RC network
Table 1. Pin Description by Function (Continued)
Pin Name
Pin Number
Type
Function
PDF 
ZIP