1
Features
Compatible with an Embedded ARM7TDMI
TM
Processor
Interfaces the ARM7TDMI Core and Atmel 32-bit Peripherals
One Wait State Inserted
Direct Interface with Peripheral Data Controller
Fully Scan Testable up to 98% Fault Coverage
Three Series of Peripheral Selects (16k, 512, 256)
Parametrizable Features on Request:
PDC Interface
Number of Peripherals to be Connected
Access Protection
Address Mapping
Access Protection
Description
The Atmel implementation of the AMBA
TM
Bridge translates ARM7TDMI system bus
(ASB) signals to peripheral bus (APB) signals.
The Bridge has direct access to the ARM7TDMI core to provide access protection for
each peripheral. The ARM7TDMI core makes its internal operating modes available
through its nM [4:0] port, which the Bridge analyzes before enabling or inhibiting
access to the peripherals.
The Bridge can also interface with the PDC to enable the transfer of data between on-
chip peripherals and on- or off-chip memories. The logic concerned can easily be
removed on request.
The p_stb_rising signal generated by the Bridge can be used as the clock pin for the
APB peripheral configuration registers, reducing the power consumption for static
values.
The test_clock pin must be accessible through a top level circuit pin in order to be
driven by ATPG vectors. The leading/trailing edges of this clock must be different from
the system clock ones in order to avoid races with the ATPG vectors.
32-bit
Embedded ASIC
Core Peripheral
Bridge
Rev. 1286CCASIC03/02
2
Bridge
1286CCASIC03/02
Figure 1. Bridge Symbol
test_so1[2:1]
AMBA
PERIPHERAL
BUS (APB)
clock
nreset
CHIP
WIDE
AMBA
BRIDGE
SCAN
bridge_sel
add_master[20:0]
write_master
data_from_master[31:0]
ARM7TDMI Core
A7TDMI_Negmode[4:0]
PDC
pdc_add[20:0]
pdc_sel
pdc_size[1:0]
pdc_write
pdc_data[31:0]
data_from_periph[31:0]
p_sel_aic
p_sel_wdt
p_sel_pmc
p_sel_pio[3:0]
p_sel_timer[7:0]
p_sel_usart[7:0]
p_sel_spi[3:0]
p_sel_analog[7:0]
p_sel_digital[7:0]
p_sel_sfr
p_sel_ebi
periph_add[13:0]
periph_write
periph_stb
p_stb_rising
data_to_periph[31:0]
p_sel_ssc[3:0]
periph_enable
SCAN
scan_test_mode
test_se
test_si1[2:1]
wait_1c
data_to_master[31:0]
AMBA
SYSTEM
BUS (ASB)
AMBA
SYSTEM
BUS (ASB)
AMBA
PERIPHERAL
BUS (APB)
test_clock
nreset_f
(Connected to ARM7TDMI nM[4:0])
nclock
p_sel_512b[5:0]
p_sel_256b[3:0]
3
Bridge
1286CCASIC03/02
Peripheral Protection
The user can select parameters for the protection level of each peripheral from the fol-
lowing list: User, FIQ, IRQ Supervisor, Abort, Undefined, System, Privilege, Not Protect.
All these modes, apart from Privilege and Not Protect are defined by the ARM7TDMI
core.
When Privilege is selected, access is denied if the core is in User mode. Access is
enabled when the ARM7TDMI core is in any of the other modes.
When Not Protect is selected, access is enabled when the ARM7TDMI core is in any
mode; the
A7TDMI_negmode [4:0]
port values are ignored.
When a non-authorized access is attempted, the peripheral select control signal
(
p_selL_xxxx
) is not sent.
Peripheral address mapping is user-defined, each peripheral being allocated a 16K slot.
Peripheral select vectored signals (USART, SPI, TIMER, PIO) must be located in con-
secutive slots.
PDC Connection
If the Bridge is connect data bus contains four copies of the eight selected bits of the
PDC data. For example:
When a transfer is from peripherals to memories, the peripheral data bus is organized
as in Table 2.
Note:
1.
Y = PDC_DATA
Note:
1. Z = PDC_DATA
pdc_data
= 0xAA551177 (Y in Table 1; Z in Table 2)
Assuming that
pdc_size[1:0] = 00, and ADD_MASTER[1:0] = 00 and
data_to_periph
= 0x77777777
Table 1. Peripheral Data Organization in Memories to Peripherals Transfers
PDC_SIZE[1:0]
Transfer Type
ADD_MASTER[1:0]
DATA_TO_PERIPH[31:0]
(1)
00
Byte
00
Y[7:0], Y[7:0], Y[7:0], Y[7:0],
01
Y[15:8], Y[15:8], Y[15:8], Y[15:8],
10
Y[23:16], Y[23:16], Y[23:16], Y[23:16],
11
Y[31:24], Y[31:24], Y[31:24], Y[31:24],
01
Half-word
0X
Y[15:0], Y[15:0]
1X
Y[31:16], Y[31:16]
1X
Word
XX
Y[31:0]
Table 2. Peripheral Data Organization in Peripherals to Memories Transfers
PDC_SIZE[1:0]
Transfer Type
DATA_TO_MASTER[31:0]
(1)
00
Byte
Z[7:0], Z[7:0], Z[7:0], Z[7:0]
01
Half-word
Z[15:0], Z[15:0]
1X
Word
Z[31:0]
4
Bridge
1286CCASIC03/02
Table 3. Pin Description
Name
Definition
Type
Active
Level
Comments
Chip-wide
nreset
System Reset
Input
Low
Resets all counters and signals. Clocked on
rising edge of clock
nreset_f
System Reset
Input
Low
Resets all counters and signals. Clocked on
falling edge of clock.
clock
System Clock
Input
System clock for rising edge DFFs.
nclock
System Clock
Input
System clock for falling edge DFFs.
ARM7TDMI Core
A7TDMI_negmode [4:0]
ARM7TDMI
Core Operation
Mode
Input
Must be connected to negmode[4:0] of the
ARM7TDMI core
AMBA System Bus (ASB)
bridge_sel
Bridge Select
Input
High
From address decoder of system bus
add_master[20:0]
Address System Bus
Input
High
Address bus generated by master (except
PDC addresses)
write_master
Write Operation
Input
High
Master writes data to peripheral
data_from_master[31:0]
Receive Operation
Input
High
Master receives data from peripheral
(except PDC)
data_to_master[31:0]
Receive Operation
Output
High
wait_1c
Wait Cycle
Output
High
Wait one cycle
Peripheral Data Controller Interface
pdc_add[20:0]
PDC Address Bus
Input
High
Used by the Bridge to access the
peripherals
pdc_sel
PDC Select
Input
High
Used by the Bridge to access the
peripherals
pdc_size[1:0]
PDC Size of Transfer
Input
High
Size for SPI data transfer (provided by
PDC):
00 = 8 bit, 01 = 16 bit, 10 = 32 bit,
11 = reserved
pdc_write
PDC Write
Input
High
Used by the Bridge to access the
peripherals
pdc_data[31:0]
PDC Data
Input
High
PDC data bus
AMBA Peripheral Bus (APB)
p_sel_256b[3:0]
256 Address Location Selects
Output
High
Selection control signal addressing only
256 address locations, others address 16K
p_sel_512b[5:0]
512 Address Location Selects
Output
High
Selection control signal addressing only
512 address locations, others address 16K
p_sel_aic
AIC Select
Output
High
AIC selection control signal
p_sel_wdt
Watchdog Timer Select
Output
High
Watchdog selection control signal
5
Bridge
1286CCASIC03/02
Note:
* These parameters are easily modified on request. It is possible to configure up to 8 USARTs, 4 SPIs, 8 Timer Counters,
4 PIOs, 8 Analog blocks and 8 Digital blocks.
Scan Test
Configuration
The fault coverage is maximum if all non-scan inputs can be controlled and all non-scan
outputs can be observed. In order to achieve this, the ATPG vectors must be generated
on the entire circuit (top-level).
p_sel_pmc
Power Management Controller
Select
Output
High
Power Management Controller selection
control signal
p_sel_pio[3*:0]
Parallel Input/Output Select
Output
High
PIO selection control signal
p_sel_timer[7*:0]
Timers Select
Output
High
Timers selection control signal
p_sel_ssc[3*:0]
SSC Select
Output
High
SSC selection control signal
p_sel_usart[7*:0]
USART Select
Output
High
USART selection control signal
p_sel_spi[3*:0]
SPI Select
Output
High
SPI selection control signal
p_sel_analog[7*:0]
Analog Peripheral Select
Output
High
(User peripherals)
p_sel_digital[7*:0]
Digital Peripheral Select
Output
High
(User peripherals)
p_sel_sfr
Special Function Register
Select
Output
High
Special Function Register selection control
signal
p_sel_ebi
External Bus Interface Select
Output
High
EBI selection control signal
periph_add[20:0]
Address Bus for Peripherals
Output
High
periph_write
Peripheral Write Enable
Output
High
Set to 1 when a master writes data to a
peripheral
periph_stb
Peripheral Strobe
Output
High
Set when the data transfer is stable
periph_enable
Peripheral Enable
Output
High
Set on second APB cycle
p_stb_rising
Output
High
Used as a clock for all the peripheral
configuration registers
data_from_periph
[31:0]
Input
High
data_to_periph[31:0]
Data to Peripheral
Output
High
Test Scan
scan_test_mode
Must be Set When Running the
Scan Vectors
Input
High
test_se
Scan Test Enable
Input
High/Low
Scan shift/scan capture
test_si[2:1]
Scan Test Input
Input
High
Entry of scan chain
test_so[2:1]
Scan Test Output
Output
Output of scan chain
test_clock
Scan Test Clock
Input
Must be accessible from ASIC top level pin
for scan test vectors
Table 3. Pin Description (Continued)
Name
Definition
Type
Active
Level
Comments
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