1
Features
Compatible with an Embedded 32-bit ARM7TDMI
TM
Processor
Up to 32 Programmable I/O Lines
Interrupt Generation on Event
Glitch Filter
Fully Scan Testable (up to 98% Fault Coverage)
Can be Directly Connected to the Atmel Implementation
of the AMBA
TM
Peripheral Bus (APB) of the ARM7TDMI Microcontroller
Multi-driver (Open Drain) Option
Certain Options "Parametrizable" on Request:
Number of Programmable Lines
Glitch Filter Option
Multi-driver (Open Drain) Option
Reset State of PIO Status and Glitch Filter Status
Description
The Parallel Input/Output 1 (PIO1) 32-bit embedded core peripheral features 32 fully-
programmable input/output lines, each of which may be dedicated as general purpose
I/O or be multiplexed with a signal generated by another embedded peripheral, in
order to optimize the use of available package pins in the overall system-on-chip
design. The PIO1 controller provides a bit-maskable event driven internal interrupt
signal.
The PIO1 and other analog and digital modular embedded peripherals, together with a
choice of microprocessor and DSP cores, on-chip RAM, ROM, EEPROM and Flash
memory, as well as special purpose analog or digital user-developed blocks, allow
rapid and cost-effective design and implementation of an optimized system-on-chip.
The large range of functional blocks offers a realistic and efficient design pathway to
system-level integration (SLI).
The PIO1 is bus-compatible with the ARM7TDMI 32-bit microcontroller core. It can
also be used with other 32-bit MCU or DSP cores.
The PIO1 is supplied with comprehensive test vector sets. Atmel's proprietary foundry
interface tools ensure a smooth transition from design to fabrication.
32-bit
Embedded Core
Peripheral
Parallel
Input/Output 1
(PIO1)
Rev. 1321C03/01
2
PIO1
1321C03/01
Figure 1. PIO1 Terminal Connections
p_d_in [31:0]
nreset
p_a [13:0]
p_write
p_stb
clock
p_sel_pio
scan_test_mode
pio_int
test_so[2:1]
p_d_out[31:0]
PIO1
APB
APB
test_se
test_si[2:1]
Scan Test
Scan Test
p_stb_rising
Pad
d_from_pad[31*:0]
Chip-wide
Peripheral
d_from_periph[31*:0]
en_periph_n[31*:0]
Interrupt
d_to_pad[31*:0]
oen_to_pad[31*:0]
d_to_periph[31*:0]
Pad
Peripheral
nreset_f
Note: *Depends on "On Request" parameters. For example, if 20 lines are requested, it will be [19:0].
3
PIO1
1321C03/01
Note:
1. Depends on "On Request" parameters. For example, if 20 lines are requested, it will be [19:0].
Table 1. PIO Terminal Description
Name
Function
Type
Active
Level
Comments
Chip-wide
nreset
System reset
Input
Low
Resets all counters and signals
Clocked on rising edge of clock
nreset_f
System reset
Input
Low
Resets all counters and signals
Clocked on falling edge of clock
clock
System clock
Input
System clock
Atmel Peripheral Bus (APB)
p_a [13:0]
Address bus
Input
The address takes into account the 2
LSBs [1:0], but the PIO1 macrocell
does not decode these bits
p_d_in [31:0]
Input data bus
Input
From host (bridge)
p_d_out [31:0]
Output data bus
Output
To host (bridge)
p_write
Write enable
Input
High
From host (bridge)
p_stb
Peripheral strobe
Input
High
From host (bridge)
p_stb_rising
User interface clock signal
Input
From host (bridge)Clock for all DFFs
controlling the configuration registers
p_sel_pio
Selects the PIO1 block
Input
High
From host (bridge)
Pad
d_from_pad [31
1
:0]
Pad input data
Input
Data from an I/O pad
d_to_pad [31
1
:0]
Pad output data
Output
Data to an I/O pad
oen_to_pad [31
1
:0]
Pad output enable
Output
Low
Output enable for a bidirectional pad
Peripheral
d_from_periph [31
1
:0]
Peripheral data input
Input
Data from an on-chip peripheral
d_to_periph [31
1
:0]
Peripheral data output
Output
Data to an on-chip peripheral
en_periph_n [31
1
:0]
Peripheral data enable
Input
Low
Enables data from an on-chip
peripheral to a pad when a peripheral
connection is enabled
Interrupt
pio_int
PIO1 generated Interrupt
Output
High
Any I/O line may be programmed to
generate an event driven interrupt
Test Scan
scan_test_mode
Clock selection for test purposes
Input
High
test_se
Scan test enable
Input
High/Low
Scan shift/scan capture
test_si[2:1]
Scan test input
Input
High
Entry of scan chain
test_so [2:1]
Scan test output
Output
Ouput of scan chain
5
PIO1
1321C03/01
Functional
Description
The 32-bit PIO1 peripheral is fully compatible with an embedded ARM7TDMI processor.
The PIO peripheral features 32 fully-programmable I/O lines, each of which may be mul-
tiplexed with an on-chip peripheral signal.
The device can also provide a bit-maskable event driven on-chip interrupt signal.
The PIO1 peripheral is fully-controllable via five sets of three 32-bit registers; pin data
and interrupt source conditions are available to user software via two 32-bit regis-
ters.Figure 3 illustrates PIO1 functionality and the effect of register programming as
described in the following sections
Figure 3. .PIO1 Control and Status Register Architecture
Pad
PIO_OSR
1
0
1
0
PIO_PSR
PIO_ODSR
0
1
1
0
Filter
PIO_IFSR
PIO_PSR
Event
Detection
PIO_PDSR
PIO_ISR
PIO_IMR
0
1
PIO_MDSR
Peripheral
Output
Enable
Peripheral
Output
Peripheral
Input
PIOIRQ
Pad Output Enable
Pad Output
Pad Input
0
1
PIO_MDSR
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