1
Features
Pixel Size: 13 m x 13 m (13 m pitch)
High Data Output Rate: 20 MHz typ
High Responsivity and Resolution over a Wide Spectral Range: from Blue (400 nm) up
to Near Infrared (1100 nm)
Improved Dark Signal and Photo Response Uniformity
Low Temporal Noise and High Dynamic Range: Over 6000/1
Ease and Flexibility of Operation:
Only two External Basic Drive Clocks
Internal or External Sample and Reset Clocks
24-lead DIL Package
Pin Identification
Pin Number
Symbol
Designation
1
V
OSA
Video Output Signal A (Odd Channel)
2
ECHA
A Channel Sample-and-hold Gate Input
3
S
ECHA
A Channel Internal Sample Clock-output
4
RA
A Channel External Reset Clock Input
8
V
DD
Output Amplifier Drain And Internal Logic Supply
9
TP3
Test Point 3
10
TP2
Test Point 2
11
VT
Register And Photosensitive Zone DC Bias
12
TP1
Test Point 1
13
V
SS
Substrate Bias (Ground)
15
P
Transfer Clock
16
T
Register Transport Clock
17
V
GS
Output Gate DC Bias
18
RB
B Channel External Reset Clock Input
19
V
INH
Internal Sample Clock Inhibition
21
S
ECHB
B Channel Internal Sample Clock Input
22
ECHB
B Channel Sample-and-hold Gate Input
23
V
OSB
Video Output Signal B (Even Channel)
24
V
DR
Reset DC Bias
5, 6, 7, 14, 20
DNC
Do Not Connected
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VOSA
ECHA
S ECHA
RA
DNC
DNC
DNC
VDD
TP3
TP2
VT
TP1
VDR
VOSB
ECHB
S ECHB
DNC
VINH
RB
VGS
T
P
DNC
VSS
TH7804A
Linear Charged
Couple Device
(CCD) Image
Sensor 1024
Pixels
TH7804A
Rev. 1989AIMAGE05/02
2
TH7804A
1989AIMAGE05/02
Operating Range
The operating range defines the temperature limits between which functionality is guar-
anteed: 0C to 70C.
Operating Precautions
Shorting the video output to V
SS
or V
DD
, even temporarily, can permanently damage the
output amplifier.
Absolute Maximum Ratings*
Storage Temperature ..................................... -55C to +150C
*NOTICE:
Stresses above those listed under absolute max-
imum ratings may cause permanent device fail-
ure. Functionality at or above these limits is not
implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
Operating Temperature ....................................... 0C to +70C
Thermal Cycling..........................................................15C/mn
Maximum Voltage:
Pins: 2, 4, 8,12,15,16,18,19, 22, 24 ................-0.3V to +18V
Pins: 9,10,11,17 .............................................. -0.3V to +18V
Pin: 13 .............................................................................. 0V
3
TH7804A
1989AIMAGE05/02
Operating Conditions (T = 25)
Notes:
1. Nominal value of V
T
:
V
TN
= 6.7V if
T
clock levels are at their typical value.
2. No use for operation. For testing purpose only.
Basic Internal
Configuration
Note:
1. Make the straps as short as possible to avoid any parasitic coupling to these connections. The load capacitance introduced
by the strap should not exceed 5 pF.
Table 1. DC Bias Characteristics
Parameter
Symbol
Value
Unit
Remark
Min.
Typ.
Max
Output Amplifier Drain Supply
V
DD
14
15
16
V
Reset DC Bias
V
DR
V
DD
- 2.4
V
DD
- 2
V
DD
- 1
V
Output Gate DC Bias
V
GS
5.5
6
6.5
V
Photosensitive Zone And
Register DC Bias
V
T
0.95 V
TN
V
TN
1.05 V
TN
V
(1)
Substrate Bias
V
SS
0.0
0.0
V
Test Point 1
TP1
V
DD
V
(2)
Tests Points 2 And 3
TP2, TP3
V
SS
V
(2)
V
TN
V
T
(
)HIGH
V
T
(
)LOW
+
2
----------------------------------------------------------------------
5%
=
S
ECHA
and
RA
internal to TH7804A
S
ECHB
and
RA
Table 2. Selection of Nominal Mode
Option
Implementation
Remarks
Internal Sampling
V
INH
(19) Connected to V
SS
S
ECHA
(3) and
ECHA
(2) Strapped
S
ECHB
(21) and
ECHB
(22) Strapped
(1)
see note
Internal Reset
RA
(4) and
RB
(18) Connected to V
DD
4
TH7804A
1989AIMAGE05/02
Figure 1. Basic Test Configuration
Figure 2. Timing Diagram in Basic Mode
5
TH7804A
1989AIMAGE05/02
Note:
1. Transients under 0.0V in the clock pulses will lead to charge injection, causing a localized increase in the dark signal. If such
spurious negative transients are present, they can be suppressed by inserting a serial resistor of appropriate value (typically
20 to 100
) in the corresponding driver output.
Notes:
1. V
OS
= average video output voltage.
2. Fs = 2 F
T
. The minimum clock frequency is limited by the increase in dark signal.
Electro-optical
Performance
General measurement conditions: T
C
= 25C; T
i
= 1 ms; F
T = 2.5 MHz (F
DATA
= 5 MHz)
Light source: tungsten filament lamp (2854 K) + B6 38 filter (2 mm thick), F/3.5 aperture.
The filter limits the spectrum to 700 nm; in these conditions 1J/cm
2
corresponds to 3.5
lux.s.
Operating conditions (see Figure 1).
First and last pixels, as well as reference elements, are excluded from the specification.
Measurements taken on each output in succession.
Table 3. Drive Clock Characteristics (see Figure 2)
Parameter
Symbol
Logic
Value
Unit
Remark
Min.
Typ.
Max.
Transfer Clock
P
,
T
High
11
13
14
V
(1)
Register Transport Clock
Low
0.0
0.4
0.6
Register Transport Clock
Capacitance
C
T
400
700
pF
Transfer Clock Capacitance
C
P
130
200
pF
Table 4. Static and Dynamic Electrical Characteristics
Parameter
Symbol
Value
Logic
Remark
Min.
Typ.
Max.
DC Output Level
V
REF
8
10
12
V
Output Impedance
Z
S
500
Register Single-stage Transfer
Efficiency
CTE
99.992
99.998
%
V
OS
= 1V
(1)
Max. Data Output Frequency
F
S max
12
20
MHz
(2)
Input Current On Pins: 2, 9, 10,
11, 12, 15, 16, 17, 18, 22
I
e
2
A
V
IN
= 15V
All other pins: 0V
Peak Current Sink on
T
Clock
(I
T
)
P
250
mA
t
RISE
= 15 ns
Peak Current Sink on
P
Clock
(I
P
)
P
80
mA
t
RISE
= 15 ns
Output Amplifier + Internal Logic
Supply Current
I
DD
17
mA
V
INH
= 0V
V
DD
= 15V
Static Power Dissipation
P
D
255
300
mW
V
INH
= 0V
V
DD
= 15V
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