1
Features
Compatible with an Embedded ARM7TDMI
TM
Processor
16-bit Down Counter
4 Clock Sources
Programmable Time-out Period
Prevents System Lock-up if the Software Becomes Trapped in a Deadlock
Write Access Protection by Control Access Keys
Full Scan Testable (up to 99%)
Can be Directly Connected to the Atmel Implementation of the AMBA
TM
Peripheral Bus
(APB)
Description
The Watchdog Timer (WD) can be used with any 32-bit microcontroller core if the tim-
ing diagram shown on page 5 is respected. When using an ARM7TDMI as the core,
the Atmel Bridge must be used to provide the correct bus interface to the peripheral.
The Watchdog Timer is used to prevent system lock-up if the software becomes
trapped in a deadlock. In normal operation the user reloads the watchdog at regular
intervals before the timer overflow occurs. If an overflow does occur, the Watchdog
Timer generates one or a combination of the following signals, depending on the
parameters in WD_OMR (Overflow Mode Register):
If RSTEN is set, an internal reset is generated
(NWD_RESET as shown in Figure 2).
If IRQEN is set, a pulse is generated on the signal WDIRQ which is connected to
the Advanced Interrupt Controller
If EXTEN is set, a low level is driven on the NWD_OVF signal for a duration of 8
CLOCK cycles.
The Watchdog Timer has a 16-bit down counter. Bits 12-15 of the value loaded when
the watchdog is restarted are programmable using the HPVC parameter in WD_CMR
(Clock Mode). Four clock sources are available to the watchdog counter: FDIV1,
FDIV2, FDIV3 or FDIV4. These must be derived by dividing the system clock
(CLOCK). The dividing factor can be from 4 to any required value. The high level
period of any of these inputs must be greater than 1 CLOCK period.
The time-out period is calculated as follows:
where HPCV is in range 0 to 15.
Below are examples of the time-out period obtained in relation to the dividing factor
using a 33 MHz clock.
The selection between the clock sources is made using the WDCLKS parameter in
WD_CMR.
Clock
Dividing Factor on FDIV
Time-out Period
33 MHz
4
0.5 ms
1024
2 sec
16384
32 sec
Period
1
CLOCK Hz
(
)
---------------------------------
DIVFAC
2
12
HPCV
1
+
(
)
=
32-bit
Embedded Core
Peripheral
Watchdog
Timer (WD)
Rev. 1241B03/01
2
Watchdog Timer
1241B03/01
All write accesses are protected by control access keys to help prevent corruption of the
watchdog should an error condition occur. To update the contents of the mode and control
registers it is necessary to write the correct bit pattern to the control access key bits at the
same time as the control bits are written (the same write access).
Figure 1. WD Pin Configuration
P_D_IN[31:0]
P_A[13:0]
P_WRITE
P_STB
CLOCK
P_SEL_WD
SCAN_TEST_MODE
WDIRQ
TEST_SO[2:1]
WD
Functional
Functional
TEST_SE
TEST_SI[2:1]
Scan Test
Scan Test
NRESET
P_D_OUT[31:0]
NWD_OVF
NWD_RESET_RISE
NWD_RESET_FALL
P_STB_RISING
FDIV1
FDIV2
FDIV3
FDIV4
3
Watchdog Timer
1241B03/01
Note:
1. One scan chain uses the clock P_STB_RISING while the other uses CLOCK.
Scan Test
Configuration
The coverage is maximum if all non-scan inputs can be controlled and all non-scan outputs
can be observed. In order to acheive this, the ATPG vectors must be generated on the entire
circuit (top level) which includes the Watchdog Timer or all WD I/Os must have a top level
access and ATPG vectors must be applied to these pins.
Table 1. WD Pin Description
Name
Function
Direction
Comments
Functional
NRESET
System reset
Input
Asynchronous, active low.
CLOCK
System clock
Input
Everything is clocked on this signal except the configuration registers.
P_A[13:0]
Software user
interface address bus
Input
The address takes into account the 2 LSBs [1:0], but the macrocell
does not take into account these bits (left unconnected).
P_D_IN[31:0]
Software user
interface data bus
Input
From host (bridge).
P_D_OUT[31:0]
Software user
interface data bus.
Output
To host (bridge).
P_WRITE
Transfer enable
(from host to
peripheral)
Input
When high, indicates that the host processor is writing to a register or
executing a command.
P_STB_RISING
Peripheral strobe
Input
Clock for all DFFs controlling configuration registers.
P_STB
Peripheral strobe
Input
When high, indicates that data and address buses are stable.
NWD_RESET_RISE
Output
For DFF clocked on falling edge.
NWD_RESET_FALL
Output
For DFF clocked on rising edge.
WDIRQ
Interrupt
Output
Active high.
NWD_OVF
Overflow
Output
Active low.
P_SEL_WD
Peripheral selection
Input
Active high.
FDIV1
Clock enable
Input
System clock (CLOCK) frequency divided
FDIV2
Clock enable
Input
System clock (CLOCK) frequency divided
FDIV3
Clock enable
Input
System clock (CLOCK) frequency divided
FDIV4
Clock enable
Input
System clock (CLOCK) frequency divided
Scan Test
SCAN_TEST_MODE
Scan test mode
Input
Must be tied to 1 during scan test.
Must be tied to 0 in functional mode.
TEST_SE
Test scan shift enable
Input
Scan shift enabled when tied to 1.
TEST_SI[2:1]
(1)
Test scan input
Input
Entry of scan chain.
TEST_SO[2:1]
(1)
Test scan output
Output
Output of scan chain.
4
Watchdog Timer
1241B03/01
Figure 2. Watchdog Timer Block Diagram
Figure 3. Connecting the WD to an ARM-based Microcontroller
Notes:
1. P_D_FRBR = signal name from Atmel Bridge, P_D_IN[31:0] = signal name from WD peripheral.
2. P_D_TOBR = signal name from Atmel Bridge, P_D_OUT[31:0] = signal name from WD peripheral.
Bus Interface
NWD_RESET_RISE
WDIRQ
FDIV1
FDIV2
FDIV3
FDIV4
Control Logic
Clock Select
16-Bit
Programmable
Down Counter
CLK_CNT
Clear
Overflow
NWD_OVF
NWD_RESET_FALL
NRESET
CLOCK
32-bit
Core
(ARM)
Atmel Bridge
P_WRITE
P_D_FRBR / P_D_IN[31:0
](1)
P_D_TOBR / P_D_OUT[31:0]
(2)
P_STB
P_A[13:0]
P_SEL_WD
Atmel Bus Interface
ASB
WD
To Advanced
Interrupt
Controller (AIC)
WDIRQ
NRESET
CLOCK
NRESET
Reset Control
NWD_RESET_RISE
NWD_RESET_FALL
NRESET
Clock Generator/
Power Management
FDIV1
FDIV2
FDIV3
FDIV4
External
Reset
5
Watchdog Timer
1241B03/01
Timing Diagram
Figure 4. WD Timing Diagram
CLOCK
Valid
P_STB
P_A[13:0]
P_D_IN[31:0]
P_WRITE
P_D_OUT[31:0]
t
PD1
t
PD2
WDIRQ
t
PD_IRQ
t
SU_WRITE
t
HOLD_WRITE
t
HOLD_DIN
t
SU_DIN
t
PD_OVF,
t
PD_RESET
NWD_OVF,
NWD_RESET_RISE,
NWD_RESET_FALL
FDIV1, FDIV2,
FDIV3, FDIV4
t
SU_FDIV
t
HOLD_FDIV
P_STB_RISING
t
SU_A
t
HOLD_A
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