SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008(LL)
Ultra Low Power
Austin Semiconductor, Inc.
MT5C1008(LL)
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
OPTIONS
MARKING
Timing
30ns access
-30
Package(s)
Ceramic DIP (400 mil)
C
No. 111
Temperature
Military (-55C to +125C)
MIL
Options
2V data retention/very low power LL
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
MIL-STD-883, para. 1.2.2 compliant
32-Pin DIP (C)
GENERAL DESCRIPTION
The MT5C1008 SRAM is a high-performance CMOS
static RAM organized as 131, 072 words by 8 bits, offering low
active power and ultra low standby and data retention current
levels. Easy memory expansion is provided by an active LOW
Chip Enable (CE1\), an active HIGH Chip Enable (CE2), and
active Low Output Enable (OE\), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
One (CE1\) and Write Enable (WE\) inputs LOW and Chip
Enable Two (CE2) input HIGH. Data on the eight I/O pins (I/O0
through I/O7) is then written into the location specified on the
address pins (A0 through A16).
Reading from the device is accomplished by taking
Chip Enable One (CE
1
\) and Output Enable (OE\) LOW while
forcing Write Enable (WE\) and Chip Enable Two (CE
2
) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output (I/O0 through I/O7) are placed
in a high-impedance state when the device is deselected (CE1\)
HIGH or CE2 LOW), the outputs are disabled (OE\ HIGH), or
during a write operation (CE1\ LOW, CE2 HIGH, and WE\ LOW).
128K x 8 SRAM
WITH DUAL CHIP ENABLE
ULTRA LOW POWER
FEATURES
High Speed: 30 ns
Low active power: 715 mW worst case
Low CMOS standby power: 3.3 mW worst case
2.0V data retention, Ultra Low 0.3mW worst
case power dissipation
Battery backup applications
Automatic power-down when deselected
TTL-compatible inputs and outputs
Easy memory expansion with CE1\, CE2, and OE\ options
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
32
31
30
29
28
26
27
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCC
A15
CE2
WE\
A13
A8
A9
A11
OE\
A10
CE1\
I/O7
I/O6
I/O5
I/O4
I/O3
For more products and information
please visit our web site at
www.austinsemiconductor.com
SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008(LL)
Ultra Low Power
Austin Semiconductor, Inc.
MT5C1008(LL)
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
MODE
OE\
CE1\
CE2
WE\
I/O0 - I/O7
POWER
Power-Down
X
H
X
X
High Z
Standby (I
SB
)
Power-Down
X
X
L
X
High Z
Standby (I
SB
)
Read
L
L
H
H
Data Out
Active (I
CC
)
Write
X
L
H
L
Data In
Active (I
CC
)
Selected, Outputs Disabled
H
L
H
H
High Z
Active (I
CC
)
SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008(LL)
Ultra Low Power
Austin Semiconductor, Inc.
MT5C1008(LL)
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage Range on Vcc to Relative GND
1
..-0.5V to +7.0V
Storage Temperature .............................................-65
C to +150
C
Ambient Temperature with Power Applied........-55C to +125C
DC Voltage Applied to Outputs
in High Z State
1
.................................................-0.5V to Vcc + 0.5V
DC Input Voltage
1
.............................................-0.5V to Vcc + 0.5V
*Stresses at or greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
in the operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods will affect reliability. Refer to page 17 of this data sheet
for a technical note on this subject.
** Junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow, and humidity.
PARAMETER
CONDITIONS
SYM
MIN
MAX
UNITS
NOTES
Output HIGH Voltage
Vcc = MIN, I
OH
= -4.0 mA
V
OH
2.4
V
Output LOW Voltage
Vcc = MIN, I
OL
= 8.0 mA
V
OL
0.4
V
Input HIGH Voltage
V
IH
2.2
V
CC
+0.3
V
Input LOW Voltage
V
IL
-0.3
0.8
V
1
Input Load Current
GND < V
I
< Vcc
I
IX
-10
+10
A
Output Leakage Current
GND < V
I
< Vcc,
Output Disabled
I
OZ
-10
+10
A
Vcc Operating Supply
Current
Vcc = MAX, I
OUT
= 0 mA
f = f = 1/t
RC
I
CC
130
mA
Automatic CE Power-
Down Current - TTL
Inputs
MAX Vcc, CE1\ > V
IH
or
CE2 < V
IL
, V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
I
SB1
4
mA
Automatic CE Power-
Down Current - CMOS
Inputs
MAX Vcc, CE1\ > Vcc - 0.3V, or
CE2 < 0.3V, V
IN
> Vcc - 0.3V, or
V
IN
< 0.3V, f = 0
I
SB2
0.6
mA
-30
ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5.0V +10%)
NOTES:
1. VIL(MIN) = -2.0V for pulse durations of less than 20ns.
SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008(LL)
Ultra Low Power
Austin Semiconductor, Inc.
MT5C1008(LL)
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
AC TEST LOADS AND WAVEFORMS
CAPACITANCE
1
PARAMETER
CONDITIONS
SYM
MAX
UNITS
Input Capacitance (A0 - A16)
C
IN
8
pF
Input Capacitance (CE\, WE\, OE\)
C
CLK
10
pF
Output Capacitance
C
OUT
12
pF
TA = 25C, f = 1MHz,
Vcc = 5.0V
DATA RETENTION CHARACTERISTICS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5.0V +10%)
PARAMETER
CONDITIONS
SYM
MIN
MAX
UNITS
Vcc for Data Retention
V
DR
2.0
V
Data Retention Current
I
CCDR
150
A
Chip Deselect to Data Retention Time
t
CDR
0
ns
Operation Recovery Time
t
R
200
s
0.2V, Vcc = V
DR
= 2.0V,
CE1\ > Vcc - 0.3V or CE2 < 0.3V,
V
IN
> Vcc - 0.3V or V
IN
< 0.3V
NOTES:
1. Tested initially and after any design or process changes that may effect these parameters.
DATA RETENTION WAVEFORM
SRAM
SRAM
SRAM
SRAM
SRAM
MT5C1008(LL)
Ultra Low Power
Austin Semiconductor, Inc.
MT5C1008(LL)
Rev. 1.0 7/02
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
NOTES:
1. Test conditions assume signal transition time of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30pF load capacitance.
2. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5pF as in part (b) of AC Test Loads. Transition is measured 500mV from steady-state voltage.
3. At any given temperature and voltage condition, t
HZCE
< t
LZCE
, t
HZOE
< t
LZOE
, and t
HZWE
< t
LZWE
for any given device.
4. The internal write time of the memory is defined by the overlap of CE1\ LOW, CE2 HIGH, and WE\ LOW. CE1\ and WE\ must be LOW and CE2 HIGH to initiate a write, and the transition of any of
these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write.
5. The minimum write cycle time for Write Cycle No. 3 (WE\ controlled, OE\ LOW) is the sum of t
HZWE
and t
SD
.
SWITCHING CHARACTERISTICS
1
(-55
o
C < T
C
< 125
o
C; V
CC
= 5.0V +10%)
PARAMETER
SYM
MIN
MAX
UNITS
NOTES
Read Cycle Time
t
RC
30
ns
Address to Data Valid
t
AA
30
ns
Data Hold from Address Change
t
OHA
3
ns
CE1\ LOW to Data Valid, CE2 HIGH to Data Valid
t
ACE
30
ns
OE\ LOW to Data Valid
t
DOE
12
ns
OE\ LOW to Low Z
t
LZOE
0
ns
OE\ HIGH to High Z
t
HZOE
8
ns
2, 3
CE1\ LOW to Low Z, CE2 HIGH to Low Z
t
LZCE
3
ns
3
CE1\ HIGH to High Z, CE2 LOW to High Z
t
HZCE
15
ns
2, 3
Write Cycle Time
t
WC
30
ns
5
CE1\ LOW to Write End, CE2 HIGH to Write End
t
SCE
22
ns
Address Set-Up to Write End
t
AW
22
ns
Address Hold from Write End
t
HA
0
ns
Address Set-Up to Write Start
t
SA
0
ns
WE\ Pulse Width
t
PWE
22
ns
Data Set-up to Write End
t
SD
18
ns
Data Hold from Write End
t
HD
0
ns
WE\ HIGH to Low Z
t
LZWE
5
ns
3
WE\ LOW to High Z
t
HZWE
8
ns
2, 3
-30
READ CYCLE
WRITE CYCLE
4
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