SRAM
MT5C2561
Austin Semiconductor, Inc.
MT5C2561
Rev. 2.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
FEATURES
High Speed: 35, 45, 55, and 70
Battery Backup: 2V data retention
Low power standby
High-performance, low-power, CMOS double-metal
process
Single +5V (+10%) Power Supply
Easy memory expansion with CE\
All inputs and outputs are TTL compatible
OPTIONS
MARKING
Timing
35ns access
-35
45ns access
-45
55ns access
-55*
70ns access
-70*
Package(s)
Ceramic DIP (300 mil)
C
No. 106
Ceramic LCC
EC
No. 204
Operating Temperature Ranges
Industrial (-40
o
C to +85
o
C)
IT
Military (-55
o
C to +125
o
C)
XT
2V data retention/low power
L
*Electrical characteristics identical to those provided for the 45ns
access devices.
PIN ASSIGNMENT
(Top View)
AVAILABLE AS MILITARY
SPECIFICATIONS
SMD 5962-88725
SMD 5962-88544
MIL-STD-883
24-Pin DIP (C)
(300 MIL)
GENERAL DESCRIPTION
The Austin Semiconductor SRAM family employs
high-speed, low-power CMOS and are fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications,
Austin Semiconductor offers chip enable (CE\) on all organiza-
tions. This enhancement can place the outputs in High-Z for
additional flexibility in system design. The x1 configuration
features separate data input and output.
Writing to these devices is accomplished when write
enable (WE\) and CE\ inputs are both LOW. Reading is accom-
plished when WE\ remains HIGH and CE\ goes LOW. The
device offers a reduced power standby mode when disabled.
This allows system designs to achieve low standby power re-
quirements.
These devices operate from a single +5V power sup-
ply and all inputs and outputs are fully TTL compatible.
256K x 1 SRAM
SRAM MEMORY ARRAY
For more products and information
please visit our web site at
www.austinsemiconductor.com
28-Pin LCC (EC)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A6
A7
A8
A9
A10
A11
A14
A15
A0
Q
WE\
Vss
Vcc
A5
A4
A3
A2
A1
A17
A16
A13
A12
D
CE\
3 2 1 28 27
13 14 15 16 17
4
5
6
7
8
9
10
11
12
26
25
24
23
22
21
20
19
18
NC
A9
A10
A11
A14
A15
A0
Q
NC
NC
A4
A3
A2
A1
A17
A16
A13
NC
A12
D
CE\
Vss
WE\
A8
A7
A6
Vcc
A17
SRAM
MT5C2561
Austin Semiconductor, Inc.
MT5C2561
Rev. 2.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
ROW DECODER
262,144-BIT
MEMORY ARRAY
I/O CONTROL
V
CC
GND
D
Q
CE\
WE\
A13
A14
A15
A16
A17
A0
A1
A2
A3
A4
COLUMN DECODER
A5 A6 A7 A8 A9 A10 A11 A12
POWER
DOWN
MODE
CE\
WE\
DQ
POWER
STANDBY
H
X
HIGH-Z
STANDBY
READ
L
H
Q
ACTIVE
WRITE
L
L
HIGH-Z
ACTIVE
SRAM
MT5C2561
Austin Semiconductor, Inc.
MT5C2561
Rev. 2.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
ABSOLUTE MAXIMUM RATINGS
*
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
CAPACITANCE
Voltage on Any Pin Relative to Vss..................................-0.5V to +7V
Voltage on Vcc Supply Relative to Vss.............................-0.5V to +7V
Voltage Applied to Q.........................................................-0.5V to +6V
Storage Temperature......................................................-65
o
C to +150
o
C
Power Dissipation..............................................................................1W
Short Circuit Output Current.........................................................50mA
Lead Temperature (soldering 10 seconds)....................................+260
o
C
Junction Temperature..................................................................+175
o
C
SYM
-35
-45
UNITS NOTES
I
CCSP
120
120
mA
3
I
CCLP
100
100
mA
3
Power Supply
Current: Standby
I
SBT1
25
25
mA
I
SBCSP
20
20
mA
"L" Version Only
I
SBCLP
3
3
mA
CE\ > V
CC
-0.2V; V
CC
= MAX
V
IL
< V
SS
+0.2V
V
IH
> V
CC
-0.2V; f = 0 Hz
CE\ > V
IH
; All Other Inputs
< V
IL
or > V
IH
, V
CC
= MAX
f = 0 Hz
MAX
CONDITIONS
Power Supply
Current: Operating
PARAMETER
CE\ < V
IL
; V
CC
= MAX
f = MAX = 1/t
RC
(MIN)
Output Open
DESCRIPTION
CONDITIONS
SYM
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
2.2
V
CC
+0.5
V
1
Input Low (Logic 0) Voltage
V
IL
-0.5
0.8
V
1, 2
Input Leakage Current
0V<V
IN
<V
CC
IL
I
-10
10
A
Output Leakage Current
Output(s) disabled
0V<V
OUT
<V
CC
IL
O
-10
10
A
Output High Voltage
I
OH
= -4.0mA
V
OH
2.4
V
1
Output Low Voltage
I
OL
= 8.0mA
V
OL
0.4
V
1
PARAMETER
CONDITIONS
SYM
MAX
UNITS
NOTES
Input Capacitance
C
I
10
pF
4
Output Capacitance
C
O
12
pF
4
T
A
= 25
o
C, f = 1MHz
Vcc = 5V
SRAM
MT5C2561
Austin Semiconductor, Inc.
MT5C2561
Rev. 2.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55
o
C < T
C
< 125
o
C; V
CC
= 5V +10%)
MIN
MAX
MIN
MAX
UNITS
NOTES
READ CYCLE
READ cycle time
t
RC
35
45
ns
Address access time
t
AA
35
45
ns
Chip Enable access time
t
ACE
35
45
ns
Output hold from address change
t
OH
3
3
ns
Chip Enable to output in Low-Z
t
LZCE
3
3
ns
7
Chip disable to output in High-Z
t
HZCE
20
20
ns
6, 7
Chip Enable to power-up time
t
PU
0
0
ns
4
Chip disable to power-down time
t
PD
35
45
ns
4
WRITE CYCLE
WRITE cycle time
t
WC
35
45
ns
Chip Enable to end of write
t
CW
30
40
ns
Address valid to end of write
t
AW
30
40
ns
Address setup time
t
AS
0
0
ns
Address hold from end of write
t
AH
5
5
ns
WRITE pulse width
t
WP
30
40
ns
Data setup time
t
DS
20
20
ns
Data hold time
t
DH
0
0
ns
Write disable to output in Low-Z
t
LZWE
0
0
ns
7
Write Enable to output in High-Z
t
HZWE
0
15
0
20
ns
6, 7
-35
-45
DESCRIPTION
SYMBOL
SRAM
MT5C2561
Austin Semiconductor, Inc.
MT5C2561
Rev. 2.5 1/01
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
AC TEST CONDITIONS
Input pulse levels ...................................... Vss to 3.0V
Input rise and fall times ......................................... 5ns
Input timing reference levels ................................ 1.5V
Output reference levels ....................................... 1.5V
Output load ................................. See Figures 1 and 2
NOTES
1.
All voltages referenced to V
SS
(GND).
2.
-3V for pulse width < 20ns
3.
I
CC
is dependent on output loading and cycle rates.
The specified value applies with the outputs
unloaded, and f = 1 Hz.
t
RC (MIN)
4.
This parameter is guaranteed but not tested.
5.
Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
6.
t
LZCE
, t
LZWE
, t
LZOE
, t
HZCE
, t
HZOE
and t
HZWE
are
specified with CL = 5pF as in Fig. 2. Transition is
measured 200mV typical from steady state voltage,
allowing for actual tester RC time constant.
7.
At any given temperature and voltage condition, t
HZCE
is
less than t
LZCE
, and t
HZWE
is less than t
LZWE
and t
HZOE
is
less than t
LZOE
.
8.
WE\ is HIGH for READ cycle.
9.
Device is continuously selected. Chip enable is held in
its active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
11. t
RC
= Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
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DON'T CARE
UNDEFINED
LOW Vcc DATA RETENTION WAVEFORM
V
TH
= 1.73V
Q
167
30pF
V
TH
= 1.73V
Q
167
5pF
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DATA RETENTION MODE
V
DR
> 2V
4.5V
4.5V
V
DR
t
CDR
t
R
V
IH
V
IL
V
CC
CE\
DESCRIPTION
CONDITIONS
SYM
MIN
MAX
UNITS
NOTES
VCC for Retention Data
V
DR
2
---
V
Data Retention Current
CE\ > (V
CC
- 0.2V)
V
IN
> (V
CC
- 0.2V)
or < 0.2V
V
CC
= 2V
I
CCDR
900
A
Chip Deselect to Data
Retention Time
t
CDR
0
---
ns
4
Operation Recovery Time
t
R
t
RC
ns
4, 11
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