Revision 1.1
Jan.
2004
1
R0201-BS62LV4006
Very Low Power/Voltage CMOS SRAM
512K X 8 bit
Wide Vcc operation voltage : 2.4V ~ 5.5V
Very low power consumption :
Vcc = 3.0V C-grade: 29mA (@55ns) operating current
I -grade: 30mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
0.45uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade: 68mA (@55ns) operating current
I -grade: 70mA (@55ns) operating current
C-grade: 58mA (@70ns) operating current
I -grade: 60mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
High speed access time :
-55 55ns
-70 70ns
Automatic power down when chip is deselected
Fully static operation
The BS62LV4006 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.45uA at
3.0V/25
o
C
and maximum access time of 55ns at
3.0V/85
o
C
.
Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4006 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4006 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.
DESCRIPTION
FEATURES
BLOCK DIAGRAM
PRODUCT FAMILY
PIN CONFIGURATIONS
Brilliance Semiconductor, Inc
. reserves the right to modify document contents without notice.
Address
Input
Buffer
Row
Decoder
Memory Array
2048 X 2048
Column I/O
Write Driver
Sense Amp
Column Decoder
Data
Buffer
Output
Address Input Buffer
Data
Buffer
Input
Control
GND
Vdd
OE
WE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
8
8
8
8
16
256
2048
2048
22
A11 A9 A8 A3 A2 A1 A0 A10
BS62LV4006
BSI
POWER DISSIPATION
SPEED
( ns )
STANDBY
( I
CCSB1
, Max )
Operating
( I
CC
, Max )
PKG
TYPE
BS62LV4006TC
TSOP
-
32
BS62LV4006STC
STSOP
-
32
BS62LV4006SC
SOP
-
32
BS62LV4006EC
TSOP2
-
32
BS62LV4006PC
+0
O
C to +70
O
C
2.4V ~ 5.5V
55 / 70
5uA
30uA
24mA
58mA
PDIP
-
32
BS62LV4006TI
TSOP
-
32
BS62LV4006STI
STSOP
-
32
BS62LV4006SI
SOP
-
32
BS62LV4006EI
TSOP2
-
32
BS62LV4006PI
-
40
O
C to +85
O
C
2.4V ~ 5.5V
55 / 70
10uA
60uA
25mA
60mA
PDIP
-
32
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
BS62LV4006TC
BS62LV4006STC
BS62LV4006TI
BS62LV4006STI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BS62LV4006SC
BS62LV4006SI
BS62LV4006EC
BS62LV4006EI
BS62LV4006PC
BS62LV4006PI
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
55ns :3.0~5.5V
Vcc = 3.0V
Vcc = 3.0V Vcc =5.0V
Data retention supply voltage as low as 1.5V
Easy expansion with CE and OE options
Three state outputs and TTL compatible
70ns :2.7~5.5V
Vcc =5.0V
70ns
70ns
Revision 1.1
Jan.
2004
2
R0201-BS62LV4006
Name
Function
A0-A18 Address Input
These 19 address inputs select one of the 524,288 x 8-bit words in the RAM
CE Chip Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
GND
Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI
MODE
WE
CE
OE
I/O OPERATION
Vcc CURRENT
Not selected
X
H
X
High Z
I
CCSB
, I
CCSB1
Output Disabled
H
L
H
High Z
I
CC
Read
H
L
L
D
OUT
I
CC
Write
L
L
X
D
IN
I
CC
SYMBOL
PARAMETER
CONDITIONS
MAX.
UNIT
C
IN
Input
Capacitance
V
IN
=0V
6 pF
C
DQ
Input/Output
Capacitance
V
I/O
=0V
8 pF
ABSOLUTE MAXIMUM RATINGS
(1)
OPERATING RANGE
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not 100% tested.
SYMBOL
PARAMETER
RATING
UNITS
V
TERM
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
T
BIAS
Temperature Under Bias
-40 to +85
O
C
T
STG
Storage Temperature
-60 to +150
O
C
P
T
Power Dissipation
1.0 W
I
OUT
DC Output Current
20
mA
BS62LV4006
RANGE
AMBIENT
TEMPERATURE
Vcc
Commercial 0
O
C to +70
O
C
2.4V ~ 5.5V
Industrial -40
O
C to +85
O
C
2.4V ~ 5.5V
Revision 1.1
Jan.
2004
3
R0201-BS62LV4006
1. Typical characteristics are at T
A
= 25
o
C.
2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. I
cc
SB1_MAX.
is 5uA/30uA at Vcc=3.0V/5.0V and T
A
=70
o
C. 5. Icc_
MAX.
is 30mA(@3.0V)/70mA(@5.0V) under 55ns operation.
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. I
cc
DR
_
MAX.
is 0.8uA at T
A
=70
O
C.
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
BSI
LOW V
CC
DATA RETENTION WAVEFORM
( CE Controlled )
CE
Data Retention Mode
Vcc
t
CDR
Vcc
t
R
V
IH
V
IH
Vcc
V
DR
1.5V
CE Vcc - 0.2V
BS62LV4006
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
DR
Vcc for Data Retention
CE Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
1.5 -- --
V
I
CCDR
Data Retention Current
CE Vcc - 0.2V
V
IN
Vcc - 0.2V or V
IN
0.2V
-- 0.3 1.3
uA
t
CDR
Chip Deselect to Data
Retention Time
0 -- --
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-- --
ns
PARAMETER
NAME
PARAMETER
TEST CONDITIONS
MIN. TYP.
(1)
MAX.
UNITS
V
IL
Guaranteed Input Low
Voltage
(3)
-0.5
--
0.8
V
V
IH
Guaranteed Input High
Voltage
(3)
2.2
--
Vcc+0.3
V
I
IL
Input Leakage Current
Vcc = Max, V
IN
= 0V to Vcc
--
--
1
uA
I
LO
Output Leakage Current
Vcc = Max, CE = V
IH
, or OE = V
IH
,
V
I/O
= 0V to Vcc
--
--
1
uA
V
OL
Output Low Voltage
--
--
V
V
OH
Output High Voltage
Vcc = Min, I
OH
= -1.0mA
--
--
V
I
CC
Operating Power Supply
Current
CE = V
IL
, I
DQ
= 0mA,
F=Fmax
(2)
--
--
25
mA
I
CCSB
Standby Current-TTL
CE = V
IH
, I
DQ
= 0mA
--
--
1.0
mA
I
CCSB1
CE Vcc-0.2V,
V
IN
Vcc - 0.2V or V
IN
0.2V
--
0.45
60
uA
Vcc = 3.0 V
Vcc = 3.0 V
Vcc = 5.0 V
Vcc = 5.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 3.0 V
Standby Current-CMOS
Vcc = 5.0 V
Vcc = 5.0 V
Vcc = 3.0 V
10
60
Vcc = 5.0 V
Vcc = 5.0 V
Vcc = 3.0 V
Vcc = 3.0 V
0.8
2.0
2.4
0.4
0.5
2.0
2.4
0.4
Vcc = Max, I
OL
= 2.0mA
(5)
(4)
70ns
70ns
Revision 1.1
Jan.
2004
4
R0201-BS62LV4006
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
"OFF "STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI
BS62LV4006
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
UNIT
t
AVAX
t
RC
Read Cycle Time
55
--
--
70
--
--
ns
t
AVQV
t
AA
Address Access Time
--
--
55
--
--
70
ns
t
ELQV
t
ACS
Chip Select Access Time
--
--
55
--
--
70
ns
t
GLQV
t
OE
Output Enable to Output Valid
--
--
30
--
--
35
ns
t
ELQX
t
CLZ
Chip Select to Output Low Z
10
--
--
10
--
--
ns
t
GLQX
t
OLZ
Output Enable to Output in Low Z
10
--
--
10
--
--
ns
t
EHQZ
t
CHZ
Chip Deselect to Output in High Z
--
--
30
--
--
35
ns
t
GHQZ
t
OHZ
Output Disable to Output in High Z
--
--
25
--
--
30
ns
t
AXOX
t
OH
Data Hold from Address Change
10
--
--
10
--
--
ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
CYCLE TIME : 55ns
MIN. TYP. MAX.
(Vcc = 3.0~5.5V)
MIN. TYP. MAX.
(Vcc = 2.7~5.5V)
CYCLE TIME : 70ns
Revision 1.1
Jan.
2004
5
R0201-BS62LV4006
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
BSI
BS62LV4006
READ CYCLE3
(1,4)
READ CYCLE2
(1,3,4)
t
CLZ
t
CHZ
(5)
D
OUT
CE
(5)
t
ACS
t
OH
t
RC
t
OE
D
OUT
CE
OE
ADDRESS
t
CLZ
(5)
t
ACS
t
CHZ
(1,5)
t
OHZ
(5)
t
OLZ
t
AA
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