ADC80MAH-12
Monolithic12-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
INDUSTRY-STANDARD 12-BIT ADC
q
MONOLITHIC CONSTRUCTION
q
LOW COST
q
0.012% LINEARITY
q
25
s max CONVERSION TIME
q
12V OR
15V OPERATION
q
NO MISSING CODES: 25
C to +85
C
q
HERMETIC 32-PIN PACKAGE
q
PARALLEL OR SERIAL OUTPUTS
q
705mW max DISSIPATION
DESCRIPTION
The ADC80MAH-12 is a 12-bit single-chip succes-
sive-approximation analog-to-digital converter for low
cost converter applications. It is complete with a
comparator, a 12-bit DAC which includes a 6.3V
reference laser-trimmed for minimum temperature
coefficient, a successive approximation register (SAR),
clock, and all other associated logic functions.
Internal scaling resistors are provided for the selection
of analog input signal ranges of
2.5V,
5V,
10V, 0
to +5V, or 0 to +10V. Gain and offset errors may be
externally trimmed to zero, enabling initial end-point
accuracies of better than
0.12% (
1/2LSB).
The maximum conversion time of 25
s makes the
ADC80MAH-12 ideal for a wide range of 12-bit
applications requiring system throughput sampling
rates up to 40kHz. In addition, this A/D converter may
be short-cycled for faster conversion speed with re-
duced resolution, and an external clock may be used to
synchronize the converter to the system clock or to
obtain higher-speed operation. The convert command
circuits have been redesigned to allow simplified free-
running operation with internal or external clock.
Data is available in parallel and serial form with
corresponding clock and status signals. All digital
input and output signals are TTL/LSTTL-compatible,
with internal pull-up resistors included on all digital
inputs to eliminate the need for external pull-up resis-
tors on digital inputs not requiring connection. The
ADC80MAH-12 operates equally well with either
15V or
12V analog power supplies, and also re-
quires use of a +5V logic power supply. However,
unlike many ADC80-type products, a +5V analog
power supply is not required. It is packaged in a
hermetic 32-pin side-brazed ceramic dual-in-line pack-
age.
Bipolar
Offset
Successive
Approximation
Register
Clock
12-Bit D/A
Converter
Clock
Inhibit
External
Clock
Short
Cycle
Comparator
In
20V Range
10V Range
Reference Out
Serial
Out
Comparator
Clock
Out
Parallel
Data
Output
International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1986 Burr-Brown Corporation
PDS-694A
Printed in U.S.A. October, 1993
2
ADC80MAH-12
SPECIFICATIONS
ELECTRICAL
At T
A
= +25
C,
V
CC
= 12V or 15V, V
DD
= +5V, unless otherwise specified.
ADC80MAH-12
PARAMETER
MIN
TYP
MAX
UNITS
RESOLUTION
12
Bits
INPUT
ANALOG
Voltage Ranges: Unipolar
0 to +5, 0 to +10
V
Bipolar
2.5,
5,
10
V
Impedance: 0 to +5V,
2.5V
2.45
2.5
2.55
k
0 to +10V,
5V
4.9
5
5.1
k
10V
9.8
10
10.2
k
DIGITAL
Logic Characteristics (Over specification temperature range)
V
IH
(Logic "1")
2
5.5
V
V
IL
(Logic "0")
0.3
+0.8
V
I
IH
(V
IN
= +2.7V)
20
A
I
IL
(V
IN
= +0.4V)
20
A
Convert Command Pulse Width
(1)
100ns
20
s
TRANSFER CHARACTERISTICS
ACCURACY
Gain Error
(2)
0.01
0.3
% of FSR
(3)
Offset Error
(2)
: Unipolar
0.05
0.2
% of FSR
Bipolar
0.1
0.3
% of FSR
Linearity Error
0.012
% of FSR
Differential Linearity Error
1/2
3/4
LSB
Inherent Quantization Error
1/2
LSB
POWER SUPPLY SENSITIVITY
11.4V
V
CC
16.5V
0.003
0.009
% of FSR/%V
CC
+4.5V
V
DD
+5.5V
0.002
0.005
% of FSR/%V
DD
DRIFT
Total Accuracy, Bipolar
(4)
10
23
ppm/
C
Gain
15
30
ppm/
C
Offset: Unipolar
3
ppm of FSR/
C
Bipolar
7
15
ppm of FSR/
C
Linearity Error Drift
1
3
ppm of FSR/
C
Differential Linearity over Temperature Range
3/4
LSB
No Missing Code Temperature Range
25
85
C
Monotonicity Over Temperature Range
Guaranteed
CONVERSION TIME
(5)
22
25
s
OUTPUT
DIGITAL (Bits 1-12 , Clock Out, Status, Serial Out)
Output Codes
(6)
Parallel: Unipolar
CSB
Bipolar
COB, CTC
Serial (NRZ)
(7)
CSB, COB
Logic Levels: Logic 0 (I
SINK
3.2mA)
+0.4
V
Logic 1 (I
SOURCE
80
A)
+2.4
V
Internal Clock Frequency
520
kHz
INTERNAL REFERENCE VOLTAGE
Voltage
+6.20
+6.3
+6.40
V
Source Current Available for External Loads
(8)
200
A
Temperature Coefficient
10
30
ppm/
C
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
ADC80MAH-12
3
BURN-IN TEMPERATURE
MODEL
(160h)
(1)
ADC80MAH-12-BI
12
RESOLUTION
MODEL
(Bits)
ADC80MAH-12
12
SPECIFICATIONS
(CONT)
ELECTRICAL
At T
A
= +25
C,
V
CC
= 12V or 15V, V
DD
= +5V, unless otherwise specified.
ADC80MAH-12
PARAMETER
MIN
TYP
MAX
UNITS
POWER SUPPLY REQUIREMENTS
Rated Supply Voltages
+5,
12 or
15
V
Supply Ranges:
V
CC
11.4
+16.5
V
V
DD
+4.5
+5.5
V
Supply Drain: +I
CC
(+V
CC
= 15V)
8.5
11
mA
I
CC
(V
CC
= 15V)
21
24
mA
I
DD
(V
CC
= 5V)
30
36
mA
Power Dissipation (
V
CC
= 15V, V
DD
= 5V)
593
705
mW
Thermal Resistance,
JA
50
C/W
TEMPERATURE RANGE (Ambient)
Specification
25
+85
C
Operating (derated specs)
55
+125
C
Storage
65
+150
C
NOTES: (1) Accurate conversion will be obtained with any convert command pulse width of greater than 100ns; however, it must be limited to 20
s (max) to assure
the specified conversion time. (2) Gain and offset errors are adjustable to zero. See "Optional External Gain and Offset Adjustment" section. (3) FSR means Full-
Scale Range and is 20V for
10V range, 10V for
5V and 0 to +10V ranges, etc. (4) Includes drift due to linearity, gain, and offset drifts. (5) Conversion time is
specified using internal clock. For operation with an external clock see "Clock Options" section. This converter may also be short-cycled to less than 12-bit resolution
for shorter conversion time; see "Short Cycle Feature" section. (6) CSB means Complementary Straight Binary, COB means Complementary Offset Binary, and
CTC means Complementary Two's Complement coding. See Table I for additional information. (7) NRZ means Non-Return-to-Zero coding. (8) External loading
must be constant during conversion, and must not exceed 200
A for guaranteed specification.
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
+V
CC
to Analog Common ........................................................ 0 to +16.5V
V
CC
to Analog Common ........................................................ 0 to 16.5V
V
DD
to Digital Common ................................................................ 0 to +7V
Analog Common to Digital Common ................................................
0.5V
Logic Inputs (Convert Command, Clock In)
to Digital Common ........................................................... 0.3V to +V
CC
Analog Inputs (Analog In, Bipolar Offset)
to Analog Common .....................................................................
16.5V
Reference Output ......................................... Indefinite Short to Common,
Momentary Short to V
CC
Lead Temperature, (soldering, 10s) .............................................. +300
C
Maximum Junction Temperature .................................................. +160
C
NOTE: (1) Or equivalent.
BURN-IN SCREENING OPTION
ABSOLUTE MAXIMUM RATINGS PCM1760
ORDERING INFORMATION
PACKAGE INFORMATION
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER
(1)
ADC80MAH-12
32-Pin Hermetic
212
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
4
ADC80MAH-12
CONNECTION DIAGRAM
PIN ASSIGNMENTS
PIN
DESCRIPTION
PIN
DESCRIPTION
1
Bit 6
32
Bit 7
2
Bit 5
31
Bit 8
3
Bit 4
30
Bit 9
4
Bit 3
29
Bit 10 (LSB-10 Bits)
5
Bit 2
28
Bit 11
6
Bit 1 (MSB)
27
Bit 12 (LSB-12 Bits)
7
NC
(1)
26
Serial Out
8
Bit 1 (MSB)
25
V
CC
9
+5V Digital Supply
24
Reference Out (+6.3V)
10
Digital Common
23
Clock Out
11
Comparator In
22
Status
12
Bipolar Offset
21
Short Cycle
13
R
1
10V Range
20
Clock Inhibit
14
R
2
20V Range
19
External Clock
15
Analog Common
18
Convert Command
16
Gain Adjust
17
+V
CC
NOTE: (1) +5V applied to pin 7 has no effect on circuit.
SYMBOL
PARAMETER
TYP
UNITS
t
CD
Clock delay from convert command
153
ns
t
CP
Nominal clock period
1.81
s
t
CW
Nominal clock pulse width
0.87
s
t
SD
Status delay from convert command
186
ns
t
R
All bits reset delay from convert command
141
ns
t
DV
Data valid time from clock pulse high
15
ns
FIGURE 1. Timing Diagram (nominal values at +25
C with internal clock).
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9 Bit 10 Bit 11 Bit 12
Data Invalid
Serial
Data
Bit 12
Bit 4
Bit 3
Bit 2
Bit 1
Covert
Command
Internal
Clock
Status
t
SD
t
R
t
CD
t
CP
t
CW
t
DV
12-Bit Successive
Approximation Register
12-Bit D/A
Converter
6.3k
5k
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
R
2
R
1
5k
Clock
Reference
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