1
ADS1210, 1211
ADS1210
ADS1211
24-Bit ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
DELTA-SIGMA A/D CONVERTER
q
23 BITS EFFECTIVE RESOLUTION AT 10Hz
AND 20 BITS AT 1000Hz
q
DIFFERENTIAL INPUTS
q
PROGRAMMABLE GAIN AMPLIFIER
q
FLEXIBLE SPI COMPATIBLE SSI
INTERFACE WITH 2-WIRE MODE
q
PROGRAMMABLE CUT-OFF FREQUENCY
UP TO 15.6kHz
q
INTERNAL/EXTERNAL REFERENCE
q
ON CHIP SELF-CALIBRATION
q
ADS1211 INCLUDES 4 CHANNEL MUX
DESCRIPTION
The ADS1210 and ADS1211 are precision, wide
dynamic range, delta-sigma analog-to-digital converters
with 24-bit resolution operating from a single +5V
supply. The differential inputs are ideal for direct
connection to transducers or low level voltage sig-
nals. The delta-sigma architecture is used for wide
dynamic range and to guarantee 22 bits of no missing
code performance. An effective resolution of 23 bits
is achieved through the use of a very low-noise input
amplifier at conversion rates up to 10Hz. Effective
resolutions of 20 bits can be maintained up to a
sample rate of 1kHz through the use of the unique
Turbo modulator mode of operation. The dynamic
range of the converters is further increased by provid-
ing a low-noise programmable gain amplifier with a
gain range of 1 to 16 in binary steps.
The ADS1210 and ADS1211 are designed for high
resolution measurement applications in smart trans-
mitters, industrial process control, weigh scales, chro-
matography and portable instrumentation. Both con-
verters include a flexible synchronous serial interface
which is SPI compatible and also offers a two-wire
control mode for low cost isolation.
The ADS1210 is a single channel converter and is
offered in both 18-pin DIP and 18-lead SOIC pack-
ages. The ADS1211 includes a 4 channel input multi-
plexer and is available in 24-pin DIP, 24-lead SOIC,
and 28-lead SSOP packages.
APPLICATIONS
q
INDUSTRIAL PROCESS CONTROL
q
INSTRUMENTATION
q
BLOOD ANALYSIS
q
SMART TRANSMITTERS
q
PORTABLE INSTRUMENTS
q
WEIGH SCALES
q
PRESSURE TRANSDUCERS
ADS1211 Only
ADS1210/11
ADS1210
ADS1211
ADS1210
ADS1211
ADS1211
PGA
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
Serial Interface
Second-Order
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Third-Order
Digital Filter
Micro Controller
Modulator Control
AGND AV
DD
REF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
MODE
DSYNC
CS
DRDY
A
IN
P
A
IN
N
SCLK
DGND
DV
DD
SDIO
SDOUT
MUX
A
IN
1P
A
IN
1N
A
IN
2P
A
IN
2N
A
IN
3P
A
IN
3N
A
IN
4P
A
IN
4N
1996 Burr-Brown Corporation
PDS-1284E
Printed in U.S.A. May, 2000
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
SBAS034
2
ADS1210, 1211
All specifications T
MIN
to T
MAX
, AV
DD
= DV
DD
= +5V, f
XIN
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REF
OUT
disabled,V
BIAS
disabled,
and external 2.5V reference, unless otherwise specified.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
SPECIFICATIONS
ADS1210U, P/ADS1211U, P, E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ANALOG INPUT
Input Voltage Range
(1)
0
+5
V
With V
BIAS
(2)
10
+10
V
Input Impedance
G = Gain, TMR = Turbo Mode Rate
4/(G TMR)
(3)
M
Programmable Gain Amplifier
User Programmable: 1, 2, 4, 8, or 16
1
16
Input Capacitance
8
pF
Input Leakage Current
At +25
C
5
50
pA
At T
MIN
to T
MAX
1
nA
SYSTEMS PERFORMANCE
Resolution
24
Bits
No Missing Codes
f
DATA
= 60Hz
22
Bits
Integral Linearity
f
DATA
= 60Hz
0.0015
%FSR
f
DATA
= 1000Hz, TMR of 16
0.0015
%FSR
Unipolar Offset Error
(4)
See Note 5
Unipolar Offset Drift
(6)
1
V/
C
Gain Error
(4)
See Note 5
Gain Error Drift
(6)
1
V/
C
Common-Mode Rejection
(9)
At DC, +25
C
100
115
dB
At DC, T
MIN
to T
MAX
90
115
dB
50Hz, f
DATA
= 50Hz
(7)
160
dB
60Hz, f
DATA
= 60Hz
(7)
160
dB
Normal-Mode Rejection
50Hz, f
DATA
= 50Hz
(7)
100
dB
60Hz, f
DATA
= 60Hz
(7)
100
dB
Output Noise
See Typical Performance Curves
Power Supply Rejection
DC, 50Hz, and 60Hz
65
dB
VOLTAGE REFERENCE
Internal Reference (REF
OUT
)
2.4
2.5
2.6
V
Drift
25
ppm/
C
Noise
50
Vp-p
Load Current
Source or Sink
1
mA
Output Impedance
2
External Reference (REF
IN
)
2.0
3.0
V
Load Current
2.5
A
V
BIAS
Output
Using Internal Reference
3.15
3.3
3.45
V
Drift
50
ppm/
C
Load Current
Source or Sink
10mA
DIGITAL INPUT/OUTPUT
Logic Family
TTL Compatible CMOS
Logic Level: (all except X
IN
)
V
IH
I
IH
= +5
A
2.0
DV
DD
+0.3
V
V
IL
I
IL
= +5
A
0.3
0.8
V
V
OH
I
OH
= 2 TTL Loads
2.4
V
V
OL
I
OL
= 2 TTL Loads
0.4
V
X
IN
Input Levels: V
IH
3.5
DV
DD
+0.3
V
V
IL
0.3
0.8
V
X
IN
Frequency Range (f
XIN
)
0.5
10
MHz
Output Data Rate (f
DATA
)
User Programmable
2.4
15,625
Hz
f
XIN
= 500kHz
0.12
781
Hz
Data Format
User Programmable
Two's Complement
or Offset Binary
SYSTEM CALIBRATION
Offset and Full-Scale Limits
V
FS
= Full-Scale Differential Voltage
(8)
0.7 (2 REF
IN
)/G
V
FS
| V
OS
|
V
OS
= Offset Differential Voltage
(8)
1.3 (2 REF
IN
)/G
3
ADS1210, 1211
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
4.75
5.25
V
Power Supply Current:
Analog Current
2
mA
Digital Current
3.5
mA
Additional Analog Current with
REF
OUT
Enabled
1.6
mA
V
BIAS
Enabled
No Load
1
mA
Power Dissipation
26
40
mW
TMR of 16
37
60
mW
f
XIN
= 2.5MHz
17
mW
f
XIN
= 2.5MHz, TMR of 16
27
mW
Sleep Mode
11
mW
TEMPERATURE RANGE
Specified
40
+85
C
Storage
60
+125
C
NOTES: (1) In order to achieve the converter's full-scale range, the input must be fully differential (A
IN
N = 2 REF
IN
A
IN
P). If the input is single-ended (A
IN
N or
A
IN
P is fixed), then the full scale range is one-half that of the differential range. (2) This range is set with external resistors and V
BIAS
(as described in the text).
Other ranges are possible. (3) Input impedance is higher with lower f
XIN
. (4) Applies after calibration. (5) After system calibration, these errors will be of the order
of the effective resolution of the converter. Refer to the Typical Performance Curves which apply to the desired mode of operation. (6) Recalibration can remove
these errors. (7) The specification also applies at f
DATA
/i, where i is 2, 3, 4, etc. (8) Voltages at the analog inputs must remain within AGND to AV
DD
. (9) The common-
mode rejection test is performed with a 100mV differential input.
SPECIFICATIONS
(CONT)
ADS1210U, P/ADS1211U, P, E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
TEMPERATURE
PRODUCT
PACKAGE
NUMBER
(1)
RANGE
ADS1210P
18-Pin Plastic DIP
218
40
C to +85
C
ADS1210U
18-Lead SOIC
219
40
C to +85
C
ADS1211P
24-Pin Plastic DIP
243
40
C to +85
C
ADS1211U
24-Lead SOIC
239
40
C to +85
C
ADS1211E
28-Lead SSOP
324
40
C to +85
C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits be
handled and stored using appropriate ESD protection
methods.
Analog Input: Current ................................................
100mA, Momentary
10mA, Continuous
Voltage ................................... AGND 0.3V to AV
DD
+0.3V
AV
DD
to DV
DD
........................................................................... 0.3V to 6V
AV
DD
to AGND ......................................................................... 0.3V to 6V
DV
DD
to DGND ......................................................................... 0.3V to 6V
AGND to DGND ................................................................................
0.3V
REF
IN
Voltage to AGND ............................................ 0.3V to AV
DD
+0.3V
Digital Input Voltage to DGND .................................. 0.3V to DV
DD
+0.3V
Digital Output Voltage to DGND ............................... 0.3V to DV
DD
+0.3V
Lead Temperature (soldering, 10s) .............................................. +300
C
Power Dissipation (Any package) .................................................. 500mW
ABSOLUTE MAXIMUM RATINGS
All specifications T
MIN
to T
MAX
, AV
DD
= DV
DD
= +5V, f
XIN
= 10MHz, programmable gain amplifier setting of 1, Turbo Mode Rate of 1, REF
OUT
disabled,V
BIAS
disabled,
and external 2.5V reference, unless otherwise specified.
4
ADS1210, 1211
PGA
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
Serial Interface
Second-Order
Modulator
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Third-Order
Digital Filter
Micro Controller
Modulator Control
11
9
10
12
13
AGND
AV
DD
REF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
3
1
2
16
17
18
4
7
8
6
5
14
15
DSYNC
CS
DRDY
MODE
A
IN
P
A
IN
N
SCLK
DGND
DV
DD
SDIO
SDOUT
ADS1210
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
A
IN
P
A
IN
N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
ADS1210 SIMPLIFIED BLOCK DIAGRAM
ADS1210 PIN DEFINITIONS
PIN NO
NAME
DESCRIPTION
1
A
IN
P
Noninverting Input.
2
A
IN
N
Inverting Input.
3
AGND
Analog Ground.
4
V
BIAS
Bias Voltage Output, +3.3V nominal.
5
CS
Chip Select Input.
6
DSYNC
Control Input to Synchronize Serial Output Data.
7
X
IN
System Clock Input.
8
X
OUT
System Clock Output (for Crystal or Resonator).
9
DGND
Digital Ground.
10
DV
DD
Digital Supply, +5V nominal.
11
SCLK
Clock Input/Output for serial data transfer.
12
SDIO
Serial Data Input (can also function as Serial Data
Output).
13
SDOUT
Serial Data Output.
14
DRDY
Data Ready.
15
MODE
SCLK Control Input (Master = 1, Slave = 0).
16
AV
DD
Analog Supply, +5V nominal.
17
REF
OUT
Reference Output, +2.5V nominal.
18
REF
IN
Reference Input.
TOP VIEW
DIP/SOIC
ADS1210 PIN CONFIGURATION
5
ADS1210, 1211
PGA
+2.5V
Reference
+3.3V Bias
Generator
Clock Generator
Serial Interface
Second-Order
Modulator
Third-Order
Digital Filter
Modulator Control
14
12
13
15
16
AGND
AV
DD
REF
OUT
REF
IN
V
BIAS
X
IN
X
OUT
6
19
20
21
7
10
11
9
8
17
18
DSYNC
CS
DRDY
MODE
SCLK
DGND
DV
DD
SDIO
SDOUT
4
5
2
3
24
1
22
23
MUX
A
IN
1P
A
IN
1N
A
IN
2P
A
IN
2N
A
IN
3P
A
IN
3N
A
IN
4P
A
IN
4N
Instruction Register
Command Register
Data Output Register
Offset Register
Full-Scale Register
Micro Controller
ADS1211 SIMPLIFIED BLOCK DIAGRAM
ADS1211P AND ADS1211U PIN DEFINITIONS
TOP VIEW
DIP/SOIC
ADS1211P AND ADS1211U PIN CONFIGURATION
PIN NO
NAME
DESCRIPTION
1
A
IN
3N
Inverting Input Channel 3.
2
A
IN
2P
Noninverting Input Channel 2.
3
A
IN
2N
Inverting Input Channel 2.
4
A
IN
1P
Noninverting Input Channel 1.
5
A
IN
1N
Inverting Input Channel 1.
6
AGND
Analog Ground.
7
V
BIAS
Bias Voltage Output, +3.3V nominal.
8
CS
Chip Select Input.
9
DSYNC
Control Input to Synchronize Serial Output Data.
10
X
IN
System Clock Input.
11
X
OUT
System Clock Output (for Crystal or Resonator).
12
DGND
Digital Ground.
13
DV
DD
Digital Supply, +5V nominal.
14
SCLK
Clock Input/Output for serial data transfer.
15
SDIO
Serial Data Input (can also function as Serial Data
Output).
16
SDOUT
Serial Data Output.
17
DRDY
Data Ready.
18
MODE
SCLK Control Input (Master = 1, Slave = 0).
19
AV
DD
Analog Supply, +5V nominal.
20
REF
OUT
Reference Output: +2.5V nominal.
21
REF
IN
Reference Input.
22
A
IN
4P
Noninverting Input Channel 4.
23
A
IN
4N
Inverting Input Channel 4.
24
A
IN
3P
Noninverting Input Channel 3.
ADS1211P
ADS1211U
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
A
IN
3N
A
IN
2P
A
IN
2N
A
IN
1P
A
IN
1N
AGND
V
BIAS
CS
DSYNC
X
IN
X
OUT
DGND
A
IN
3P
A
IN
4N
A
IN
4P
REF
IN
REF
OUT
AV
DD
MODE
DRDY
SDOUT
SDIO
SCLK
DV
DD
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