ADS1286
DESCRIPTION
The ADS1286 is a 12-bit, 20kHz analog-to-digital
converter with a differential input and sample and hold
amplifier and consumes only 250
A of supply cur-
rent. The ADS1286 offers an SPI and SSI compatible
serial interface for communications over a two or three
wire interface. The combination of a serial two wire
interface and micropower consumption makes the
ADS1286 ideal for remote applications and for those
requiring isolation.
The ADS1286 is available in a 8-pin plastic mini DIP
and a 8-lead SOIC.
12-Bit Micro Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
SERIAL INTERFACE
q
GUARANTEED NO MISSING CODES
q
20kHz SAMPLING RATE
q
LOW SUPPLY CURRENT: 250
A
SAR
Control
Serial
Interface
D
OUT
Comparator
S/H Amp
CS/SHDN
DCLOCK
+In
V
REF
In
CDAC
ADS1286
ADS1286
APPLICATIONS
q
REMOTE DATA ACQUISITION
q
ISOLATED DATA ACQUISITION
q
TRANSDUCER INTERFACE
q
BATTERY OPERATED SYSTEMS
1996 Burr-Brown Corporation
PDS-1335B
Printed in U.S.A. October, 1998
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
2
ADS1286
SPECIFICATIONS
At T
A
= T
MIN
to T
MAX
, +V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 12.5kHz, , f
CLK
= 16 f
SAMPLE
, unless otherwise specified.
TIMING CHARACTERISTICS
f
CLK
= 200kHz, T
A
= T
MIN
to T
MAX
.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t
SMPL
Analog Input Sample Time
See Operating Sequence
1.5
2.0
Clk Cycles
t
SMPL (MAX)
Maximum Sampling Frequency
ADS1286
20
kHz
t
CONV
Conversion Time
See Operating Sequence
12
Clk Cycles
t
dDO
Delay TIme, DCLOCK
to D
OUT
Data Valid
See Test Circuits
85
150
ns
t
dis
Delay TIme, CS
to D
OUT
Hi-Z
See Test Circuits
25
50
ns
t
en
Delay TIme, DCLOCK
to D
OUT
Enable
See Test Circuits
50
100
ns
t
hDO
Output Data Remains Valid After DCLOCK
C
LOAD
= 100pF
15
30
ns
t
f
D
OUT
Fall Time
See Test Circuits
70
100
ns
t
r
D
OUT
Rise Time
See Test Circuits
60
100
ns
t
CSD
Delay Time, CS
to DCLOCK
See Operating Sequence
0
ns
t
SUCS
Delay Time, CS
to DCLOCK
See Operating Sequence
30
ns
ADS1286, ADS1286A
ADS1286K, ADS1286B
ADS1286C, ADS1286L
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Range
+In (In)
0
V
REF
T
T
T
T
V
Absolute Input Voltage
+In
0.2
V
CC
+0.2
T
T
T
T
V
In
0.2
+0.2
T
T
T
T
V
Capacitance
25
T
T
pF
Leakage Current
1
T
T
A
SYSTEM PERFORMANCE
Resolution
12
T
T
Bits
No Missing Codes
12
T
T
Bits
Integral Linearity
1
2
T
T
0.5
1
LSB
Differential Linearity
0.5
1.0
T
0.75
0.25
0.75
LSB
Offset Error
0.75
3
T
T
T
T
LSB
Gain Error
2
8
T
T
T
T
LSB
Noise
50
T
T
Vrms
Power Supply Rejection
82
T
T
dB
SAMPLING DYNAMICS
Conversion Time
12
T
T
Clk Cycles
Acquisition Time
1.5
T
T
Clk Cycles
Small Signal Bandwidth
500
T
T
kHz
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
V
IN
= 5.0Vp-p at 1kHz
85
T
T
dB
V
IN
= 5.0Vp-p at 5kHz
83
T
T
dB
SINAD
V
IN
= 5.0Vp-p at 1kHz
72
T
T
dB
Spurious Free Dynamic Range
V
IN
= 5.0Vp-p at 1kHz
90
T
T
dB
REFERENCE INPUT
REF Input Range
1.25
2.5
V
CC
+0.05V
T
T
T
T
T
T
V
Input Resistance
CS = V
CC
5000
T
T
M
CS = GND, f
CLK
= 0Hz
5000
T
T
M
Current Drain
CS = V
CC
0.01
2.5
T
T
T
T
A
t
CYC
640
s, f
CLK
25kHz
2.4
20
T
T
T
T
A
t
CYC
= 80
s, f
CLK
= 200kHz
2.4
20
T
T
T
T
A
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
T
T
Logic Levels:
V
IH
I
IH
= +5
A
3
+V
CC
T
T
T
T
V
V
IL
I
IL
= +5
A
0.0
0.8
T
T
T
T
V
V
OH
I
OH
= 250
A
3
+V
CC
T
T
T
T
V
V
OL
I
OL
= 250
A
0.0
0.4
T
T
T
T
V
Data Format
Straight Binary
T
T
POWER SUPPLY REQUIREMENTS
Power Supply Voltage
V
CC
+4.50
5
5.25
T
T
T
T
T
T
V
Quiescent Current, V
ANA
t
CYC
640
S, f
CLK
25kHz
200
400
T
T
T
T
A
t
CYC
= 90
S, f
CLK
= 200kHz
250
500
T
T
T
T
A
Power Down
CS = V
CC
3
T
T
A
TEMPERATURE RANGE
Specified Performance
ADS1286, K, L
0
+70
T
T
T
T
C
ADS1286A, B, C
40
+85
T
T
T
T
C
T
Specifications same as grade to the left.
3
ADS1286
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
ABSOLUTE MAXIMUM RATINGS
(1)
+V
CC
..................................................................................................... +6V
Analog Input ....................................................... 0.3V to (+V
CC
+ 300mV)
Logic Input ......................................................... 0.3V to (+V
CC
+ 300mV)
Case Temperature ......................................................................... +100
C
Junction Temperature .................................................................... +150
C
Storage Temperature ..................................................................... +125
C
External Reference Voltage .............................................................. +5.5V
NOTE: (1) Stresses above these ratings may permanently damage the device.
PIN CONFIGURATION
1
2
3
4
8
7
6
5
+V
CC
DCLOCK
D
OUT
CS/SHDN
V
REF
+In
In
GND
ADS1286
8-Pin Mini PDIP
8-Lead SOIC
PIN ASSIGNMENTS
PIN
NAME
DESCRIPTION
1
V
REF
Reference Input.
2
+In
Non Inverting Input.
3
In
Inverting Input. Connect to ground or remote ground sense point.
4
GND
Ground.
5
CS/SHDN
Chip Select when low, Shutdown Mode when high.
6
D
OUT
The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.
7
DCLOCK
Data Clock synchronizes the serial data transfer and determines conversion speed.
8
+V
CC
Power Supply.
PACKAGE
INTEGRAL
TEMPERATURE
DRAWING
PRODUCT
LINEARITY
RANGE
PACKAGE
NUMBER
(1)
ADS1286P
2
0
C to +70
C
Plastic DIP
006
ADS1286PK
2
0
C to +70
C
Plastic DIP
006
ADS1286PL
1
0
C to +70
C
Plastic DIP
006
ADS1286U
2
0
C to +70
C
SOIC
182
ADS1286UK
2
0
C to +70
C
SOIC
182
ADS1286UL
1
0
C to +70
C
SOIC
182
ADS1286PA
2
40
C to +85
C
Plastic DIP
006
ADS1286PB
2
40
C to +85
C
Plastic DIP
006
ADS1286PC
1
40
C to +85
C
Plastic DIP
006
ADS1286UA
2
40
C to +85
C
SOIC
182
ADS1286UB
2
40
C to +85
C
SOIC
182
ADS1286UC
1
40
C to +85
C
SOIC
182
PACKAGE/ORDERING INFORMATION
NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix
C of Burr-Brown IC Data Book.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
4
ADS1286
TYPICAL PERFORMANCE CURVES
At T
A
= +25, V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 12.5kHz, f
CLK
= 16 f
SAMPLE
, unless otherwise specified.
REFERENCE CURRENT vs TEMPERATURE
4.0
3.5
3.0
2.5
2.0
1.5
1.0
Reference Current (
A)
55
40
25
0
25
70
85
Temperature (C)
CHANGE IN OFFSET vs REFERENCE VOLTAGE
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
Change in Offset (LSB)
1
2
3
4
5
Reference Voltage (V)
CHANGE IN OFFSET vs TEMPERATURE
0.6
0.4
0.2
0
0.2
0.4
0.6
Delta from 25C (LSB)
55
40
25
0
25
70
85
Temperature (C)
CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL
LINEARITY vs REFERENCE VOLTAGE
0.10
0.05
0.00
0.05
0.10
0.15
0.20
Delta from +5V Reference (LSB)
1
2
3
4
5
Reference Voltage (V)
Change in Differential
Linearity (LSB)
Change in Integral
Linearity (LSB)
CHANGE IN GAIN vs REFERENCE VOLTAGE
4
3.5
3
2.5
2
1.5
1
0.5
0
Change in Gain (LSB)
1
2
3
4
5
Reference Voltage (V)
REFERENCE CURRENT vs SAMPLE RATE
2.5
2.0
1.5
1.0
0.5
0
Reference Current (
A)
0
2
4
6
8
10
12
Sample Rate (kHz)
5
ADS1286
DIFFERENTIAL LINEARITY ERROR vs CODE
3.0
2.0
1.0
0
1.0
2.0
3.0
Differential Linearity Error (LSB)
0
2048
4095
Code
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25, V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 12.5kHz, f
CLK
= 16 f
SAMPLE
, unless otherwise specified.
EFFECTIVE NUMBER OF BITS
vs REFERENCE VOLTAGE
12
11.75
11.5
11.25
11
10.75
10.5
10.25
10
Effective Number of Bits (rms)
0.1
1
10
Reference Voltage (V)
SPURIOUS FREE DYNAMIC RANGE
AND SIGNAL-TO-NOISE RATIO vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
Spurious Free Dynamic Range
and Signal-to-Noise Ratio (dB)
0.1
1
10
Frequency (kHz)
Spurious Free Dynamic Range
Signal-to-Noise Ratio
TOTAL HARMONIC DISTORTION vs FREQUENCY
0
10
20
30
40
50
60
70
80
90
100
Total Harmonic Distortion (dB)
0.1
1
10
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION)
vs FREQUENCY
100
90
80
70
60
50
40
30
20
10
0
Signal-to-(Noise + Distortion) (dB)
0.1
1
10
Frequency (kHz)
SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL
80
70
60
50
40
30
20
10
0
Signal-to-(Noise + Distortion) (dB)
40
35
30
25
20
15
10
5
0
Input Level (dB)
6
ADS1286
4096 POINT FFT
0
25
50
75
100
125
Magnitude (dB)
0
2
4
6
Frequency (kHz)
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25, V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 12.5kHz, f
CLK
= 16 f
SAMPLE
, unless otherwise specified.
PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE
10
9
8
7
6
5
4
3
2
1
0
Peak-to-Peak Noise (LSB)
0.1
1
10
Reference Voltage (V)
POWER SUPPLY REJECTION vs RIPPLE FREQUENCY
0
10
20
30
40
50
60
70
80
90
Power Supply Rejection (dB)
1
10
100
1000
10000
Ripple Frequency (kHz)
V
RIPPLE
= 20mV
CHANGE GAIN vs TEMPERATURE
0.15
0.1
0.05
0
0.05
0.1
0.15
Delta from 25C (LSB)
55
40
25
0
25
70
85
Temperature (C)
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
3
2.5
2
1.5
1
0.5
0
Supply Current (
A)
55
40
25
0
25
70
85
Temperature (C)
SUPPLY CURRENT vs TEMPERATURE
400
350
300
250
200
150
100
Supply Current (
A)
55
40
25
0
25
70
85
Temperature (C)
f
SAMPLE
= 1.6kHz
f
SAMPLE
= 12.5kHz
7
ADS1286
INTEGRAL LINEARITY ERROR vs CODE
3.0
2.0
1.0
0
1.0
2.0
3.0
Integral Linearity Error (LSB)
0
2048
4095
Code
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25, V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 12.5kHz, f
CLK
= 16 f
SAMPLE
, unless otherwise specified.
DIGITAL INPUT LINE THRESHOLD
vs SUPPLY VOLTAGE
3
2.5
2
1.5
1
0.5
0
Digital Input Threshold Voltage (V)
3
3.25
3.5
3.75
4
4.25
4.5
4.75
5
5.25
5.5
Supply Voltage (V)
INPUT LEAKAGE CURRENT vs TEMPERATURE
10
1
0.1
0.01
Leakage Current (nA)
55
40
25
0
25
70
85
Temperature (C)
8
ADS1286
TIMING DIAGRAMS AND TEST CIRCUITS
D
OUT
1.4V
Test Point
3k
100pF
C
LOAD
t
r
D
OUT
V
OH
V
OL
t
f
t
dDO
t
hDO
D
OUT
DCLOCK
V
OH
V
OL
V
IL
D
OUT
Test Point
t
dis
Waveform 2, t
en
t
dis
Waveform 1
100pF
C
LOAD
3k
t
dis
CS/SHDN
D
OUT
Waveform 1
(1)
D
OUT
Waveform 2
(2)
90%
10%
V
IH
1
B11
2
t
en
CS/SHDN
DCLOCK
V
OL
D
OUT
V
CC
Load Circuit for t
dDO
, t
r
, and t
f
Voltage Waveforms for D
OUT
Rise and Fall Times t
r
, and t
f
Voltage Waveforms for D
OUT
Delay Times, t
dDO
Load Circuit for t
dis
and t
den
Voltage Waveforms for t
en
Voltage Waveforms for t
dis
NOTES: (1) Waveform 1 is for an output with internal conditions such that
the output is HIGH unless disabled by the output control. (2) Waveform 2
is for an output with internal conditions such that the output is LOW unless
disabled by the output control.
9
ADS1286
CS/SHDN
D
OUT
DCLOCK
t
DATA
t
SUCS
t
CSD
t
CYC
t
CONV
POWER
DOWN
t
SMPL
Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output LSB-First data then followed with zeroes indefinitely.
B11
(MSB)
B10 B9
B8
B7
B6
B5
B4
B3
B2
B1 B0
(1)
NULL
BIT
HI-Z
HI-Z
B11 B10
B9
B8
NULL
BIT
CS/SHDN
D
OUT
DCLOCK
t
CONV
t
DATA
t
SUCS
t
CYC
POWER DOWN
t
SMPL
Note: (2) After completing the data transfer, if further clocks are applied with CS
LOW, the ADC will output zeroes indefinitely.
t
DATA
: During this time, the bias current and the comparator power down and the reference input
becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.
B11
(MSB)
B10 B9
B8
B7
B6
B5
B4
B4
B3
B3
B2
B2
B1
B1
B0
NULL
BIT
HI-Z
HI-Z
B5
B6
B7
B8
B9
B10 B11
(2)
t
CSD
leaving the DCLOCK running to clock out the LSB first
data or zeroes. If the CS input is not running rail-to-rail, the
input logic buffer will draw current. This current may be
large compared to the typical supply current. To obtain the
lowest supply current, bring the CS pin to ground when it is
low and to supply voltage when it is high.
SERIAL INTERFACE
The ADS1286 communicates with microprocessors and other
external digital systems via a synchronous 3-wire serial inter-
face. DCLOCK synchronizes the data transfer with each bit
being transmitted on the falling DCLOCK edge and captured
on the rising DCLOCK edge in the receiving system. A falling
CS initiates data transfer as shown in Figure 1. After CS falls,
the second DCLOCK pulse enables D
OUT
. After one null bit,
the A/D conversion result is output on the D
OUT
line. Bringing
CS high resets the ADS1286 for the next data exchange.
MICROPOWER OPERATION
With typical operating currents of 250
A and automatic
shutdown between conversions, the ADS1286 achieves ex-
tremely low power consumption over a wide range of
sample rates (see Figure 2). The auto-shutdown allows the
supply current to drop with sample rate.
SHUTDOWN
The ADS1286 is equipped with automatic shutdown fea-
tures. The device draws power when the CS pin is LOW and
shuts down completely when the pin is HIGH. The bias
circuit and comparator powers down and the reference input
becomes high impedance at the end of each conversion
1000
100
10
1
Supply Current (
A)
0.1k
1k
10k
100k
Sample Rate (kHz)
T
A
= 25C
V
CC
= 5V
V
REF
= 5V
f
CLK
= 16 f
SAMPLE
FIGURE 2. Automatic Power Shutdown Between Conver-
sions Allows Power Consumption to Drop with
Sample Rate.
FIGURE 1. ADS1286 Operating Sequence.
10
ADS1286
MINIMIZING POWER DISSIPATION
In systems that have significant time between conversions,
the lowest power drain will occur with the minimum CS
LOW time. Bringing CS LOW, transferring data as quickly
as possible, and then bringing it back HIGH will result in the
lowest current drain. This minimizes the amount of time the
device draws power. After a conversion the A/D automati-
cally shuts down even if CS is held LOW. If the clock is left
running to clock out LSB-data or zero, the logic will draw a
small amount of current (see Figure 3).
REDUCED REFERENCE
OPERATION
The effective resolution of the ADS1286 can be increased
by reducing the input span of the converter. The ADS1286
exhibits good linearity and gain over a wide range of
reference voltages (see Typical Performance Curves " Change
in Linearity vs Reference Voltage" and "Change in Gain vs
Reference Voltage"). However, care must be taken when
operating at low values of V
REF
because of the reduced LSB
size and the resulting higher accuracy requirement placed on
the converter. The following factors must be considered
when operating at low V
REF
values:
1. Offset
2. Noise
OFFSET WITH REDUCED V
REF
The offset of the ADS1286 has a larger effect on the output
code. When the ADC is operated with reduced reference
voltage. The offset (which is typically a fixed voltage)
becomes a larger fraction of an LSB as the size of the LSB
is reduced. The Typical Performance Curve "Change in
Offset vs Reference Voltage" shows how offset in LSBs is
related to reference voltage for a typical value of V
OS
. For
example, a V
OS
of 122
V which is 0.1 LSB with a 5V
reference becomes 0.5LSB with a 1V reference and 2.5LSBs
with a 0.2V reference. If this offset is unacceptable, it can be
corrected digitally by the receiving system or by offsetting
the negative input of the ADS1286.
NOISE WITH REDUCED V
REF
The total input referred noise of the ADS1286 can be
reduced to approximately 200
V peak-to-peak using a ground
plane, good bypassing, good layout techniques and minimiz-
ing noise on the reference inputs. This noise is insignificant
with a 5V reference but will become a larger fraction of an
LSB as the size of the LSB is reduced.
For operation with a 5V reference, the 200
V noise is only
0.15LSB peak-to-peak. In this case, the ADS1286 noise will
contribute virtually no uncertainty to the output code. How-
ever, for reduced references, the noise may become a signifi-
cant fraction of an LSB and cause undesirable jitter in the
output code. For example, with a 2.5V reference this same
200
V noise is 0.3LSB peak-to-peak. If the reference is
further reduced to 1V, the 200
V noise becomes equal to
0.8LSBs and a stable code may be difficult to achieve. In
this case averaging multiple readings may be necessary.
FIGURE 3. Shutdown Current with CS HIGH is Lower than
with CS LOW.
RC INPUT FILTERING
It is possible to filter the inputs with an RC network as
shown in Figure 4. For large values of C
FILTER
(e.g., 1
F),
the capacitive input switching currents are averaged into a
net DC current. Therefore, a filter should be chosen with a
small resistor and large capacitor to prevent DC drops across
the resistor. The magnitude of the DC current is approxi-
mately I
DC
= 20pF x V
IN
/t
CYC
and is roughly proportional to
V
IN
. When running at the minimum cycle time of 64
s, the
input current equals 1.56
A at V
IN
= 5V. In this case, a filter
resistor of 75
will cause 0.1LSB of full-scale error. If a
larger filter resistor must be used, errors can be eliminated
by increasing the cycle time.
FIGURE 4. RC Input Filtering.
R
FILTER
I
DC
ADS1286
C
FILTER
V
IN
6.00
5.00
4.00
3.00
2.00
1.00
0.00
Supply Current (
A)
0.1
1
10
100
Sample Rate (kHz)
T
A
= 25C
V
CC
= +5V
V
REF
= +5V
f
CLK
= 16 f
SAMPLE
CS = LOW
(GND)
CS HIGH
(V
CC
)
11
ADS1286
ADS1286
P
DCLOCK
D
OUT
CS/SHDN
A
0
A
1
U
3
U
4
U
1
U
2
Thermocouple
ISO Thermal Block
MUX
OPA237
0.3V
0.4V
0.2V
0.1V
+5V
R
2
59k
R
4
1k
R
3
500k
R
5
500
R
7
10
C
3
0.1F
C
4
10F
C
5
0.1F
R
6
1M
R
1
150k
D
1
TC
2
TC
1
TC
3
+5V
C
2
0.1F
C
1
10F
+5V
R
8
46k
R
9
1k
R
10
1k
R
11
1k
R
12
1k
V
REF
3-Wire
Interface
FIGURE 5. Thermocouple Application Using a MUX to Scale the Input Range of the ADS1286.
ADS1286
REF200
(100
A)
P
D
OUT
RTD
DCLOCK
CS/SHDN
+V
CC
V
REF
8
1
2
3
4
0.1
F
FIGURE 6. ADS1286 with RTD Sensor.
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