FEATURES

High Speed:

Data Rate: 2.5MSPS
Bandwidth: 1.23MHz

Outstanding Performance:

SNR: 91dB at f

= 100kHz, -1dBFS

THD: -101dB at f

= 100kHz, -6dBFS

SFDR: 103dB at f

= 100kHz, -6dBFS

Ease-of-Use:

High-Speed 3-Wire Serial Interface
Directly Connects to TMS320 DSPs
On-Chip Digital Filter Simplifies Anti-Alias

Requirements

Simple Pin-Driven Control--No On-Chip

Registers to Program

Selectable On-Chip Voltage Reference
Simultaneous Sampling with Multiple

ADS1602s

Low Power:

530mW at 2.5MSPS
Power-Down Mode

APPLICATIONS

Sonar

Vibration Analysis

Data Acquisition

FSO

Reference and Bias Circuits

Serial

Interface

Linear Phase

FIR Digital Filter

Modulator

VREFP VREFN

RBIAS

VMID

VCAP

AVDD

DVDD

IOVDD

DGND

AGND

AINP

AINN

FSO

SCLK

DOUT

SCLK

SYNC

CLK

DOUT

OTR

REFEN

ADS1602

DESCRIPTION

The ADS1602 is a high-speed, high-precision,
delta-sigma analog-to-digital converter (ADC)
manufactured on an advanced CMOS process. The
ADS1602 oversampling topology reduces clock jitter
sensitivity during the sampling of high-frequency, large
amplitude signals by a factor of four over that achieved by
Nyquist-rate ADCs. Consequently, signal-to-noise ratio
(SNR) is particularly improved. Total harmonic distortion
(THD) is -101dB, and the spurious-free dynamic range
(SFDR) is 103dB.

Optimized for power and performance, the ADS1602
dissipates only 530mW while providing a full-scale
differential input range of

3V. Having such a wide input

range makes out-of-range signals unlikely. The OTR pin
indicates if an analog input out-of-range condition does
occur. The differential input signal is measured against the
differential reference, which can be generated internally or
supplied externally on the ADS1602.

The ADS1602 uses an inherently stable advanced
modulator with an on-chip decimation filter. The filter stop
band extends to 38.6MHz, which greatly simplifies the
anti-aliasing circuitry. The modulator samples the input
signal up to 40MSPS, depending on f

CLK

, while the 16x

decimation filter uses a series of four half-band FIR filter
stages to provide 75dB of stop band attenuation and
0.001dB of passband ripple.

Output data is provided over a simple 3-wire serial
interface at rates up to 2.5MSPS, with a -3dB bandwidth
of 1.23MHz. The output data or its complementary format
directly connects to DSPs such as TI's TMS320 family,
FPGAs, or ASICs. A dedicated synchronization pin
enables simultaneous sampling with multiple ADS1602s
in multi-channel systems. Power dissipation is set by an
external resistor that allows a reduction in dissipation
when operating at slower speeds. All of the ADS1602
features are controlled by dedicated I/O pins, which
simplify operation by eliminating the need for on-chip
registers.

The high performing, easy-to-use ADS1602 is especially
suitable for demanding measurement applications in
sonar, vibration analysis, and data acquisition. The
ADS1602 is offered in a small, 7mm x 7mm TQFP-48
package and is specified from -40

C to +85

All other trademarks are the property of their respective owners.

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

16-Bit, 2.5MSPS

Analog-to-Digital Converter

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

www.ti.com

2004-2005, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

PACKAGE/ORDERING INFORMATION

For the most current package and ordering information see
the Package Option Addendum located at the end of this
datasheet or visit the TI web site at www.ti.com.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)

ADS1602

UNIT

AVDD to AGND

-0.3 to +6

DVDD to DGND

-0.3 to +3.6

IOVDD to DGND

-0.3 to +6

AGND to DGND

-0.3 to +0.3

Input Current

100mA, Momentary

Input Current

10mA, Continuous

Analog I/O to AGND

-0.3 to AVDD + 0.3

Digital I/O to DGND

-0.3 to IOVDD + 0.3

Maximum Junction Temperature

+150

Operating Temperature Range

-40 to +105

Storage Temperature Range

-60 to +150

Lead Temperature (soldering, 10s)

+260

(1) Stresses above these ratings may cause permanent damage.

Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.

This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe

proper handling and installation procedures can cause damage.
ADS1602 passes standard 200V machine model and 1.5K CDM
testing. ADS1602 passes 1kV human body model testing (TI Standard
is 2kV).

ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

ELECTRICAL CHARACTERISTICS

All specifications at TA = -40

C to +85

C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V,

and RBIAS = 37k

, unless otherwise noted.

ADS1602

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Analog Input

Differential input voltage (V

)

(AINP - AINN)

0dBFS

REF

Common-mode input voltage (V

)

(AINP + AINN) / 2

1.45

Absolute input voltage
(AINP or AINN with respect to AGND)

-0.1

4.6

Dynamic Specifications

Data Rate

2.50

CLK

40MHz

MSPS

= 10kHz, -1dBFS

= 10kHz, -3dBFS

= 10kHz, -6dBFS

= 100kHz, -1dBFS

Signal-to-noise ratio (SNR)

= 100kHz, -3dBFS

Signal-to-noise ratio (SNR)

= 100kHz, -6dBFS

= 800kHz, -1dBFS

= 800kHz, -3dBFS

= 800kHz, -6dBFS

= 10kHz, -1dBFS

-94

= 10kHz, -3dBFS

-106

-92

= 10kHz, -6dBFS

-108

-93

= 100kHz, -1dBFS

-90

Total harmonic distortion (THD)

= 100kHz, -3dBFS

-96

-90

Total harmonic distortion (THD)

= 100kHz, -6dBFS

-101

-92

= 800kHz, -1dBFS

-116

= 800kHz, -3dBFS

-114

= 800kHz, -6dBFS

-110

= 10kHz, -1dBFS

= 10kHz, -3dBFS

= 10kHz, -6dBFS

= 100kHz, -1dBFS

Signal-to-noise + distortion (SINAD)

= 100kHz, -3dBFS

Signal-to-noise + distortion (SINAD)

= 100kHz, -6dBFS

= 800kHz, -1dBFS

= 800kHz, -3dBFS

= 800kHz, -6dBFS

= 10kHz, -1dBFS

= 10kHz, -3dBFS

107

= 10kHz, -6dBFS

112

= 100kHz, -1dBFS

Spurious-free dynamic range (SFDR)

= 100kHz, -3dBFS

Spurious-free dynamic range (SFDR)

= 100kHz, -6dBFS

103

= 800kHz, -1dBFS

120

= 800kHz, -3dBFS

119

= 800kHz, -6dBFS

114

Intermodulation distortion (IMD)

= 995kHz, -6dBFS

Intermodulation distortion (IMD)

= 1005kHz, -6dBFS

Aperture delay

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = -40

C to +85

C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V,

and RBIAS = 37k

, unless otherwise noted.

ADS1602

PARAMETER

UNIT

MAX

TYP

MIN

TEST CONDITIONS

Digital Filter Characteristics

Passband

1.1

CLK

40MHz

MHz

Passband ripple

0.001

Passband transition

-0.1dB attenuation

1.15

CLK

40MHz

MHz

Passband transition

-3.0dB attentuation

1.23

CLK

40MHz

MHz

Stop band

1.4

CLK

40MHz

38.6

CLK

40MHz

MHz

Stop band attenuation

Group delay

10.4

40MHZ

CLK

Settling time

Complete settling

20.4

40MHZ

CLK

Static Specifications

Resolution

Bits

No missing codes

Bits

Input-referred noise

0.5

0.85

LSB, rms

Integral nonlinearity

-1dBFS signal

0.75

LSB

Differential nonlinearity

0.25

LSB

Offset error

-0.1

%FSR

Offset error drift

-0.1

ppmFSR/

Gain error

0.25

Gain error drift

Excluding reference drift

ppm/

Common-mode rejection

At DC

Power-supply rejection

At DC

Internal Voltage Reference

REFEN = low

REF

= (VREFP - VREFN)

2.75

3.25

VREFP

3.5

4.0

4.3

VREFN

0.5

1.0

1.3

VMID

2.3

2.5

2.7

REF

drift

ppm/

Startup time

External Voltage Reference

REFEN = high

REF

= (VREFP - VREFN)

2.0

3.25

VREFP

3.5

4.25

VREFN

0.5

1.5

VMID

2.3

2.5

2.6

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

ELECTRICAL CHARACTERISTICS (continued)

All specifications at TA = -40

C to +85

C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V,

and RBIAS = 37k

, unless otherwise noted.

ADS1602

PARAMETER

UNIT

MAX

TYP

MIN

TEST CONDITIONS

Clock Input

Frequency (f

CLK

)

MHz

Duty Cycle

CLK

= 40MHz

Digital Input/Output

0.7 x IOVDD

IOVDD

DGND

0.3 x IOVDD

= 50

IOVDD - 0.5

= 50

DGND + 0.5

Input leakage

DGND < V

DIGIN

< IOVDD

Power-Supply Requirements

AVDD

4.75

5.25

DVDD

2.7

3.3

IOVDD

= 50

2.7

5.25

AVDD current (I

AVDD

)

REFEN = low

110

125

AVDD current (I

AVDD

)

REFEN = high

DVDD current (I

DVDD

)

IOVDD = 3V

IOVDD current (I

IOVDD

)

IOVDD = 3V

Power dissipation

AVDD = 5V, DVDD = 3V,

IOVDD = 3V, REFEN = high

530

610

Power dissipation

PD = low, CLK disabled

Temperature Range

Specified

-40

+85

Operating

-40

+105

Storage

-60

+150

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

DEFINITIONS

Absolute Input Voltage

Absolute input voltage, given in volts, is the voltage of each
analog input (AINN or AINP) with respect to AGND.

Aperture Delay

Aperture delay is the delay between the rising edge of CLK
and the sampling of the input signal.

Common-Mode Input Voltage

Common-mode input voltage (V

) is the average voltage

of the analog inputs:

(AINP

)

AINN)

Differential Input Voltage

Differential input voltage (V

) is the voltage difference

between the analog inputs (AINP-AINN).

Differential Nonlinearity (DNL)

DNL, given in least-significant bits of the output code
(LSB), is the maximum deviation of the output code step
sizes from the ideal value of 1LSB.

Full-Scale Range (FSR)

FSR is the difference between the maximum and minimum
measurable input signals (FSR = 2V

REF

Gain Error

Gain error, given in %, is the error of the full-scale input
signal with respect to the ideal value.

Gain Error Drift

Gain error drift, given in ppm/

C, is the drift over

temperature of the gain error. The gain error is specified as
the larger of the drift from ambient (T = 25

C) to the

minimum or maximum operating temperatures.

Integral Nonlinearity (INL)

INL, given in least-significant bits of the output code (LSB),
is the maximum deviation of the output codes from a best
fit line.

Intermodulation Distortion (IMD)

IMD, given in dB, is measured while applying two input
signals of the same magnitude, but with slightly different
frequencies. It is calculated as the difference between the
rms amplitude of the input signal to the rms amplitude of
the peak spurious signal.

Offset Error

Offset Error, given in % of FSR, is the output reading when
the differential input is zero.

Offset Error Drift

Offset error drift, given in ppm of FSR/

C, is the drift over

temperature of the offset error. The offset error is specified
as the larger of the drift from ambient (T = 25

C) to the

minimum or maximum operating temperatures.

Signal-to-Noise Ratio (SNR)

SNR, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
f

CLK

/2 (the Nyquist frequency) excluding the first six

harmonics of the input signal and the dc component.

Signal-to-Noise and Distortion (SINAD)

SINAD, given in dB, is the ratio of the rms value of the input
signal to the sum of all the frequency components below
f

CLK

/2 (the Nyquist frequency) including the harmonics of

the input signal but excluding the dc component.

Spurious-Free Dynamic Range (SFDR)

SFDR, given in dB, is the difference between the rms
amplitude of the input signal to the rms amplitude of the
peak spurious signal.

Total Harmonic Distortion (THD)

THD, given in dB, is the ratio of the sum of the rms value
of the first six harmonics of the input signal to the rms value
of the input signal.

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

PIN ASSIGNMENTS

TQFP PACKAGE

(TOP VIEW)

DGND

DVDD

DGND

FSO

DOUT

SCLK

I
D

AGND

AVDD

AGND

AINN

AINP

AGND

AVDD

RBIAS

AGND

AVDD

AGND

AVDD

ADS1602

Terminal Functions

TERMINAL

FUNCTION

DESCRIPTION

NAME

NO.

FUNCTION

DESCRIPTION

AGND

1, 3, 6, 9, 11, 39, 41

Analog

Analog ground

AVDD

2, 7, 10, 12, 42

Analog

Analog supply

AINN

Analog input

Negative analog input

AINP

Analog input

Positive analog input

RBIAS

Analog

Terminal for external analog bias setting resistor.

REFEN

Digital input: active low

Internal reference enable. Internal pull-down resistor of 170k

to DGND.

14, 16, 24-26, 35

Do not connect

These terminals must be left unconnected.

RPULLUP

Digital Input

Pull-up to DVDD with 10k

resistor (see Figure 53).

Digital input: active low

Power down all circuitry. Internal pull-up resistor of 170k

to DGND.

DVDD

18, 23, 34

Digital

Digital supply

DGND

19, 22, 33, 36, 38

Digital

Digital ground

SYNC

Digital input

Synchronization control input

OTR

Digital output

Indicates analog input signal is out of range.

SCLK

Digital output

Serial clock output

SCLK

Digital output

Serial clock output, complementary signal.

DOUT

Digital output

Data output

DOUT

Digital output

Data output, complementary signal.

FSO

Digital output

Frame synchronization output

FSO

Digital output

Frame synchronization output, complementary signal.

IOVDD

Digital

Digital I/O supply

CLK

Digital input

Clock input

VCAP

Analog

Terminal for external bypass capacitor connection to internal bias voltage.

VREFN

44, 45

Analog

Negative reference voltage

VMID

Analog

Midpoint voltage

VREFP

47, 48

Analog

Positive reference voltage

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

TIMING DIAGRAMS

SYNC

FSO

CLK

SYPW

STL

Figure 1. Initialization Timing

TIMING REQUIREMENTS

For TA = -40

C to +85

C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

tSYPW

SYNC positive pulse width

CLK periods

tSTL

Settling time of ADS1602(1)

Conversions

tSTL

Settling time of ADS1602(1)

816

832

CLK periods

NOTE: (1) An FSO pulse occuring prior to TSTL

816 CLK period should be ignored.

FSO

SCLK

CLK

DOUT

CPW

FPW

Bit 0 (LSB)

Old Data

Bit 1

Bit 0 (LSB)

Bit 15 (MSB)

Bit 14

DHD

DPD

New Data

Figure 2. Data Retrieval Timing

TIMING REQUIREMENTS

For TA = -40

C to +85

C, DVDD = 2.7V to 3.6V, IOVDD = 2.7V to 5.25V.

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNIT

CLK period (1/fCLK)

tCPW

CLK positive or negative pulse width

11.25

tCF

Rising edge of CLK to rising edge of FSO

tFPW

FSO positive pulse width

CLK period

tCS

Rising edge of CLK to rising edge of SCLK

tDHD

SCLK rising edge to old DOUT invalid (hold time)

tDPD

SCLK rising edge to new DOUT valid (propagation delay)

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

TYPICAL CHARACTERISTICS

All specifications at TA = 25

C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37k

unless otherwise noted.

Figure 3

100

120

140

160

SPECTRAL RESPONSE

l
i
t
ud

(
dB

)

= 10kHz,

1dBFS

SNR = 92dB
THD =

94dB

SFDR = 95dB

200

400

600

Frequency (kHz)

800

1000

1200

Figure 4

100

120

140

160

SPECTRAL RESPONSE

= 10kHz,

6dBFS

SNR = 87dB
THD =

108dB

SFDR = 112dB

200

400

600

Frequency (kHz)

800

1000

1200

lit

(
d

)

Figure 5

100

120

140

160

SPECTRAL RESPONSE

= 10kHz,

10dBFS

SNR = 83dB
THD =

105dB

SFDR = 110dB

200

400

600

Frequency (kHz)

800

1000

1200

i
t
ude

(
d

)

Figure 6

100

120

140

160

SPECTRAL RESPONSE

= 100kHz,

1dBFS

SNR = 90dB
THD =

90dB

SFDR = 91dB

200

400

600

Frequency (kHz)

800

1000

1200

i
t
u

(
dB

)

Figure 7

100

120

140

160

SPECTRAL RESPONSE

= 100kHz,

6dBFS

SNR = 86dB
THD =

101dB

SFDR = 103dB

200

400

600

Frequency (kHz)

800

1000

1200

i
t
u

(
dB

)

Figure 8

100

120

140

160

SPECTRAL RESPONSE

= 100kHz,

10dBFS

SNR = 82dB
THD =

100dB

SFDR = 102dB

200

400

600

Frequency (kHz)

800

1000

1200

i
t
u

(
dB

)

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at TA = 25

C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37k

unless otherwise noted.

Figure 9

100

120

140

160

200

400

600

Frequency (kHz)

SPECTRAL RESPONSE

800

1000

1200

= 504kHz,

1dBFS

SNR = 91dB
THD =

119dB

SFDR = 119dB

i
t
u

(
dB

)

Figure 10

100

120

140

160

200

400

600

Frequency (kHz)

SPECTRAL RESPONSE

800

1000

1200

= 504kHz,

6dBFS

SNR = 86dB
THD =

103dB

SFDR = 103dB

i
t
u

(
dB

)

Figure 11

100

120

140

160

200

400

600

Frequency (kHz)

SPECTRAL RESPONSE

800

1000

1200

= 504kHz,

10dBFS

SNR = 82dB
THD =

96dB

SFDR = 96dB

l
i
t
ude

(
d

)

Figure 12

100

120

140

160

200

400

600

Frequency (kHz)

SPECTRAL RESPONSE

800

1000

1200

= 799kHz,

1dBFS

SNR = 91dB
THD =

116dB

SFDR = 120dB

i
t
ude

(
d

)

Figure 13

100

120

140

160

200

400

600

Frequency (kHz)

SPECTRAL RESPONSE

800

1000

1200

= 799kHz,

6dBFS

SNR = 86dB
THD =

110dB

SFDR = 114dB

i
t
ude

(
d

)

Figure 14

100

120

140

160

200

400

600

Frequency (kHz)

SPECTRAL RESPONSE

800

1000

1200

= 799kHz,

10dBFS

SNR = 82dB
THD =

107dB

SFDR = 112dB

i
t
ud

(
d

)

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at TA = 25

C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37k

unless otherwise noted.

Figure 15

Input Signal Amplitude, V

(dB)

SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE

I
S

I
O

NIC

URIO

I
C

(
d

)

SFDR

SNR

THD

140

120

100

= 10kHz

Figure 16

Input Signal Amplitude, V

(dB)

SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE

I
S

I
O

NIC

URIO

I
C

(
d

)

SFDR

SNR

THD

120

110

100

= 50kHz

Figure 17

140

120

100

Input Signal Amplitude, V

(dB)

SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE

I
GN

O-

I
S

I
O

I
S

URI

I
C

(
d

)

SFDR

SNR

= 100kHz

THD

Figure 18

140

120

100

Input Signal Amplitude, V

(dB)

SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE

I
GN

O-

I
S

I
O

I
S

URI

I
C

(
d

)

SFDR

SNR

= 500kHz

THD

Figure 19

140

120

100

Input Signal Amplitude, V

(dB)

SNR, THD, and SFDR vs INPUT SIGNAL AMPLITUDE

I
S

I
O

NIC

I
O

S-

I
C

(
d

SFDR

SNR

THD

= 800kHz

Figure 20

10k

100k

Input Frequency, f

(Hz)

SIGNAL-TO-NOISE RATIO

vs INPUT FREQUENCY

(
d

)

1dB

6dB

10dB

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at TA = 25

C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37k

unless otherwise noted.

Figure 21

100

105

110

115

120

10k

100k

Input Frequency, f

(Hz)

TOTAL HARMONIC DISTORTION

vs INPUT FREQUENCY

(
d

)

1dB

6dB

10dB

Figure 22

SPURIOUS-FREE DYNAMIC RANGE

vs INPUT FREQUENCY

(
d

)

Input Frequency, f

(Hz)

130

120

110

100

10k

100k

10dB

6dB

1dB

Figure 23

SIGNAL-TO-NOISE RATIO

vs INPUT COMMON-MODE VOLTAGE

(
d

)

Input Common-Mode Voltage, V

(V)

1.0

1.4

1.8

2.2

2.6

3.0

3.4

= 10kHz, V

1dB

= 100kHz, V

6dB

= 100kHz, V

1dB

= 10kHz, V

6dB

Figure 24

TOTAL HARMONIC DISTORTION

vs INPUT COMMON-MODE VOLTAGE

(
d

)

Input Common-Mode Voltage, V

(V)

100

110

1.0

1.4

1.8

2.2

2.6

3.0

3.4

= 10kHz, V

1dB

= 100kHz, V

1dB

= 10kHz, V

6dB

= 100kHz, V

6dB

Figure 25

SPURIOUS-FREE DYNAMIC RANGE

vs INPUT COMMON-MODE VOLTAGE

(
d

)

Input Common-Mode Voltage, V

(V)

1.0

1.4

1.8

2.2

2.6

3.0

3.4

110

105

100

= 100kHz, V

6dB

= 100kHz, V

1dB

= 10kHz, V

6dB

= 10kHz

1dB

Figure 26

100

200

300

400

500

600

700

800

900 1000

Time Interval (s)

OFFSET DRIFT OVER TIME

ffs

(
L

)

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at TA = 25

C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37k

unless otherwise noted.

Figure 27

SIGNAL-TO-NOISE RATIO

vs CLOCK FREQUENCY

(
d

)

Clock Frequency, f

CLK

(MHz)

100

6dBFS, f

= 10kHz

BIAS

= 210k

BIAS

= 267k

BIAS

= 140k

BIAS

= 100k

BIAS

= 60k

BIAS

= 37k

BIAS

= 30k

Figure 28

TOTAL HARMONIC DISTORTION

vs CLOCK FREQUENCY

(
d

)

Clock Frequency, f

CLK

(MHz)

110

100

6dBFS, f

= 10kHz

BIAS

= 267k

BIAS

= 210k

BIAS

= 140k

BIAS

= 100k

BIAS

= 30k

BIAS

= 60k

BIAS

= 37k

Figure 29

SPURIOUS-FREE DYNAMIC RANGE

vs CLOCK FREQUENCY

(
d

)

Clock Frequency, f

CLK

(MHz)

110

100

6dBFS, f

= 10kHz

BIAS

= 267k

BIAS

= 210k

BIAS

= 140k

BIAS

= 100k

BIAS

= 30k

BIAS

= 60k

BIAS

= 37k

Figure 30

1000

100

0.1

Input DC Voltage (V)

NOISE vs DC INPUT VOLTAGE

i
s

(
L

)

Figure 31

1540
1400
1300
1200

1100

1000

900
800
700
600
500
400
300
200
100

Output Code (LSB)

NOISE HISTOGRAM

r
r
e

= 0

Figure 32

120

100

Temperature (

POWER-SUPPLY CURRENT

vs TEMPERATURE

r
r
e

(
m

)

AVDD

(REFEN = low)

AVDD

(

REFEN = high)

BIAS

= 37k

, f

CLK

= 40MHz

DVDD

+ I

IOVDD

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

TYPICAL CHARACTERISTICS (continued)

All specifications at TA = 25

C, AVDD = 5V, DVDD = IOVDD = 3V, fCLK = 40MHz, External VREF = +3V, VCM = +1.45V, and RBIAS = 37k

unless otherwise noted.

Figure 33

140

120

100

Clock Frequency, f

CLK

(MHz)

SUPPLY-CURRENT vs CLOCK FREQUENCY

l
y

r
r
ent

(
m

)

AVDD

(REFEN = low)

AVDD

(REFEN = high)

IOVDD

+ I

DVDD

6dBFS, f

= 10kHz, R

BIAS

= 37k

Figure 34

130

110

100

150

200

250

300

BIAS

)

ANALOG SUPPLY CURRENT vs R

BIAS

l
y

r
r
ent

)

AVDD

(REFEN = low)

AVDD

(REFEN = high)

6dBFS, f

= 10kHz, f

CLK

= 40MHz

Figure 35

100

Temperature (

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

(
d

)

1dB

6dB

10dB

= 100kHz

Figure 36

Temperature (

TOTAL HARMONIC DISTORTION vs TEMPERATURE

(
d

)

1dB

6dB

100

105

10dB

Figure 37

Temperature (

SPURIOUS-FREE DYNAMIC RANGE

vs TEMPERATURE

(
d

)

1dB

120

115

110

105

100

10dB

6dB

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

OVERVIEW

The ADS1602 is a high-performance delta-sigma ADC.
The modulator uses an inherently stable 2-1-1 multi-stage
architecture incorporating proprietary circuitry that allows
for very linear high-speed operation. The modulator
samples the input signal at 40MSPS (when f

CLK

= 40MHz).

A low-ripple linear phase digital filter decimates the
modulator output by 16 to provide high resolution 16-bit
output data.

Conceptually, the modulator and digital filter measure the
differential input signal, V

= (AINP AINN), against the

scaled differential reference, V

REF

= (VREFP VREFN),

as shown in Figure 38. The voltage reference can either be
generated internally or supplied externally. A 3-wire serial
interface, designed for direct connection to DSPs, outputs
the data. A separate power supply for the I/O allows flexi-
bility for interfacing to different logic families. Out-of-range
conditions are indicated with a dedicated digital output pin.
Analog power dissipation is controlled using an external
resistor. This control allows reduced dissipation when op-
erating at slower speeds. When not in use, power con-
sumption can be dramatically reduced by setting the PD
pin low to enter Power-Down mode.

ANALOG INPUTS (AINP, AINN)

The ADS1602 measures the differential signal,
V

= (AINP AINN), against the differential reference,

REF

= (VREFP VREFN). The most positive measurable

differential input is V

REF

, which produces the most positive

digital output code of 7FFFh. Likewise, the most negative
measurable differential input is V

REF

, which produces the

most negative digital output code of 8000h.

The ADS1602 supports a very wide range of input signals.
For V

REF

= 3V, the full-scale input voltages are

3V.

Having such a wide input range makes out-of-range
signals unlikely. However, should an out-of-range signal
occur, the digital output OTR will go high.

The analog inputs must be driven with a differential signal
to achieve optimum performance. For the input signal:

AINP

)

AINN

the recommended common-mode voltage is 1.5V. In
addition to the differential and common-mode input
voltages, the absolute input voltage is also important. This
is the voltage on either input (AINP or AINN) with respect
to AGND. The range for this voltage is:

0.1V

(AINN or AINP)

4.6V

If either input is taken below 0.1V, ESD protection diodes
on the inputs will turn on. Exceeding 4.6V on either input
will result in degradation in the linearity performance. ESD
protection diodes will also turn on if the inputs are taken
above AVDD (+5V).

The recommended absolute input voltage is:

0.1V

(AINN or AINP)

4.2V

Keeping the inputs within this range provides for optimum
performance.

Modulator

Digital

Filter

Serial

Interface

VREFN

IOVDD

VREFP

REF

AINP

AINN

FSO
FSO

DOUT

SCLK
SCLK

CLK

Figure 38. Conceptual Block Diagram

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

INPUT CIRCUITRY

The ADS1602 uses switched-capacitor circuitry to measure
the input voltage. Internal capacitors are charged by the
inputs and then discharged internally with this cycle
repeating at the frequency of CLK. Figure 39 shows a
conceptual diagram of these circuits. Switches S2 represent
the net effect of the modulator circuitry in discharging the
sampling capacitors; the actual implementation is different.
The timing for switches S1 and S2 is shown in Figure 40.

10pF

AINP

ADS1602

8pF

VMID

10pF

AINN

8pF

VMID

AGND

Figure 39. Conceptual Diagram of Internal

Circuitry Connected to the Analog Inputs

Off

SAMPLE

= 1/f

CLK

Figure 40. Timing for the Switches in Figure 39

DRIVING THE INPUTS

The external circuits driving the ADS1602 inputs must be
able to handle the load presented by the switching capacitors
within the ADS1602. The input switches S1 in Figure 39 are
closed for approximately one-half of the sampling period,
t

sample

, allowing only

11ns for the internal capacitors to be

charged by the inputs when f

CLK

= 40MHz.

Figure 41 and Figure 42 show the recommended circuits
when using single-ended or differential op amps,
respectively. The analog inputs must be driven
differentially to achieve optimum performance. The

external capacitors, between the inputs and from each
input to AGND, improve linearity and should be placed as
close to the pins as possible. Place the drivers close to the
inputs and use good capacitor bypass techniques on their
supplies, such as a smaller high-quality ceramic capacitor
in parallel with a larger capacitor. Keep the resistances
used in the driver circuits low--thermal noise in the driver
circuits degrades the overall noise performance. When the
signal can be ac-coupled to the ADS1602 inputs, a simple
RC filter can set the input common-mode voltage. The
ADS1602 is a high-speed, high-performance ADC.
Special care must be taken when selecting the test
equipment and setup used with this device. Pay particular
attention to the signal sources to ensure they do not limit
performance when measuring the ADS1602.

392

OPA 28 22

ADS1602

A GN D

OPA 28 22

40pF

(1)

100pF

AINP

AINN

100pF

(3)

392

40pF

100pF

(1) Recommended V

= 1.5V.

(2) Optional ac-coupling circuit provides common-mode input voltage.
(3) Increase to 390pF when f

100kHz for improved SNR and THD.

(2)

392

0.01

392

49.9

Figure 41. Recommended Driver Circuit Using the

OPA2822

ADS1602

THS4503

22pF

100pF

AINP

AINN

100pF

24.9

392

24.9

392

22pF

Figure 42. Recommended Driver Circuit Using the

THS4503 Differential Amplifier

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

REFERENCE INPUTS (VREFN, VREFP, VMID)

The ADS1602 can operate from an internal or external
voltage reference. In either case, the reference voltage
V

REF

is set by the differential voltage between VREFN and

VREFP: V

REF

= (VREFP VREFN). VREFP and VREFN

each use two pins, which should be shorted together.
VMID equals approximately 2.5V and is used by the
modulator. VCAP connects to an internal node and must
also be bypassed with an external capacitor.

INTERNAL REFERENCE (REFEN = LOW)

To use the internal reference, set the REFEN pin low. This
activates the internal circuitry that generates the reference
voltages. The internal reference voltages are applied to
the pins. Good bypassing of the reference pins is critical
to achieve optimum performance and is done by placing
the bypass capacitors as close to the pins as possible.
Figure 43 shows the recommended bypass capacitor
values. Use high-quality ceramic capacitors for the smaller
values. Avoid loading the internal reference with external
circuitry. If the ADS1602 internal reference is to be used by
other circuitry, buffer the reference voltages to prevent
directly loading the reference pins.

0.1

ADS1602

AGND

VREFP

VMID

VCAP

VREFN

Figure 43. Reference Bypassing When Using the

Internal Reference

EXTERNAL REFERENCE (REFEN = HIGH)

To use an external reference, set the REFEN pin high. This
deactivates the internal generators for VREFP, VREFN
and VMID, and saves approximately 25mA of current on
the analog supply (AVDD). The voltages applied to these
pins must be within the values specified in the Electrical
Characteristics table. Typically, VREFP = 4V, VMID = 2.5V
and VREFN = 1V. The external circuitry must be capable

of providing both a dc and a transient current. Figure 44
shows a simplified diagram of the internal circuitry of the
reference when the internal reference is disabled. As with
the input circuitry, switches S1 and S2 open and close as
shown by the timing in Figure 40.

ADS1602

VREFP

50pF

300

VREFN

VREFP

VREFN

Figure 44. Conceptual Internal Circuitry for the

Reference When REFEN = High

Figure 45 shows the recommended circuitry for driving
these reference inputs. Keep the resistances used in the
buffer circuits low to prevent excessive thermal noise from
degrading performance. Layout of these circuits is critical;
be sure to follow good high-speed layout practices. Place
the buffers, and especially the bypass capacitors, as close
to the pins as possible. VCAP is unaffected by the setting
on REFEN and must be bypassed when using the internal
or an external reference.

0.1

VREFP

VMID

VCAP

VREFN

392

OPA2822

ADS1602

0.001

392

OPA2822

0.001

392

OPA2822

0.001

2.5V

AGND

Figure 45. Recommended Buffer Circuit When

Using an External Reference

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

CLOCK INPUT (CLK)

The ADS1602 requires an external clock signal to be
applied to the CLK input pin. The sampling of the
modulator is controlled by this clock signal. As with any
high-speed data converter, a high quality clock is essential
for optimum performance. Crystal clock oscillators are the
recommended CLK source; other sources, such as
frequency synthesizers, are usually inadequate. Make
sure to avoid excess ringing on the CLK input; keeping the
trace as short as possible will help.

Measuring high-frequency, large amplitude signals
requires tight control of clock jitter. The uncertainty during
sampling of the input from clock jitter limits the maximum
achievable SNR. This effect becomes more pronounced
with higher frequency and larger magnitude inputs.
Fortunately, the ADS1602 oversampling topology reduces
clock jitter sensitivity over that of Nyquist rate converters
such as pipeline and successive approximation

converters by a factor of

In order to not limit the ADS1602 SNR performance, keep
the jitter on the clock source below the values shown in
Table 1. When measuring lower frequency and lower
amplitude inputs, more CLK jitter can be tolerated. In
determining the allowable clock source jitter, select the
worst-case input (highest frequency, largest amplitude)
that will be seen in the application.

Table 1. Maximum Allowable Clock Source Jitter

for Different Input Signal Frequencies and

Amplitude

INPUT SIGNAL

MAXIMUM

ALLOWABLE

MAXIMUM

FREQUENCY

MAXIMUM

AMPLITUDE

ALLOWABLE

CLOCK SOURCE

JITTER

1MHz

-2dB

3.8ps

1MHz

-20dB

28ps

500kHz

-2dB

7.6ps

500kHz

-20dB

57ps

100kHz

-2dB

38ps

100kHz

-20dB

285ps

DATA FORMAT

The 16-bit output data is in binary two's complement
format as shown in Table 2. When the input is positive
out-of-range, exceeding the positive full-scale value of
V

REF

, the output clips to all 7FFFh and the OTR output

goes high.

Likewise, when the input is negative out-of-range by going
below the negative full-scale value of V

REF

, the output

clips to 8000h and the OTR output goes high. The OTR
remains high while the input signal is out-of-range.

Table 2. Output Code Versus Input Signal

INPUT SIGNAL

(INP INN)

IDEAL OUTPUT

CODE(1)

OTR

+VREF (> 0dB)

7FFFh

VREF (0dB)

7FFFh

REF

0001h

0000h

-V

REF

FFFFh

-V

REF

8000h

-V

REF

8000h

(1) Excludes effects of noise, INL, offset and gain errors.

OUT-OF-RANGE INDICATION (OTR)

If the output code exceeds the positive or negative
full-scale, the out-of-range digital output OTR will go high
on the falling edge of SCLK. When the output code returns
within the full-scale range, OTR returns low on the falling
edge of SCLK.

DATA RETRIEVAL

Data retrieval is controlled through a simple serial
interface. The interface operates in a master fashion by
outputting both a frame sync indicator (FSO) and a serial
clock (SCLK). Complementary outputs are provided for
the frame sync output (FSO), serial clock (SCLK) and data
output (DOUT). When not needed, leave the
complementary outputs unconnected.

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

INITIALIZING THE ADS1602

After the power supplies have stabilized, you must
initialize the ADS1602 by issuing a SYNC pulse as shown
in Figure 1. This operation needs only to be done once
after power-up and does not need to be performed when
exiting the Power-Down mode.

SYNCHRONIZING MULTIPLE ADS1602s

The SYNC input can be used to synchronize multiple
ADS1602s to provide simultaneous sampling. All devices
to be synchronized must use a common CLK input. With
the CLK inputs running, pulse SYNC on the falling edge of
CLK, as shown in Figure 46. Afterwards, the converters
will be converting synchronously with the FSO outputs
updating simultaneously. After synchronization, FSO is
held low until the digital filter has fully settled.

SYNC

ADS1602

CLK

FSO

DOUT

FSO

DOUT

SYNC

CLK

SYNC

ADS1602

CLK

FSO

DOUT

FSO

DOUT

CLK

...

SYNC

...

STL

FSO

Figure 46. Synchronizing Multiple Converters

STEP RESPONSE

Figure 47 plots the normalized step response for an input
applied at t = 0. The x-axis units of time are conversions
cycles. It takes 51 cycles to fully settle; for f

CLK

= 40MHz,

this corresponds to 20.4

1.2

1.0

0.8

0.6

0.4

0.2

Time (Conversion Cycles)

t
e

ons

Figure 47. Step Response

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

FREQUENCY RESPONSE

The linear phase FIR digital filter sets the overall frequency
response. Figure 48 shows the frequency response from
dc to 20MHz for f

CLK

= 40MHz. The frequency response

of the ADS1602 filter scales directly with CLK frequency.
For example, if the CLK frequency is decreased by half (to
20MHz), the values on the X-axis in Figure 48 would need
to be scaled by half, with the span becoming dc to 10MHz.

Figure 49 shows the passband ripple from dc to 1200kHz
(f

CLK

= 40MHz). Figure 50 shows a closer view of the

passband transition by plotting the response from 900kHz
to 1300kHz (f

CLK

= 40MHz).

100

120

140

Frequency (MHz)

agn

i
t
u

(
dB

)

CLK

= 40MHz

Figure 48. Frequency Response

0.001

0.0008

0.0006

0.0004

0.0002

0.0004

0.0006

0.0008

0.001

200

400

600

Frequency (kHz)

800

1000

i
t
u

(
dB

)

1200

CLK

= 40MHz

Figure 49. Passband Ripple

0.5

1.0

1.5

2.0

2.5

3.0

3.5

800

900

1000

1100

1200

Frequency (kHz)

gni

t
u

(
d

)

1300

CLK

= 40MHz

Figure 50. Passband Transition

ANTI-ALIAS REQUIREMENTS

Higher frequency, out-of-band signals must be eliminated
to prevent aliasing with ADCs. Fortunately, the ADS1602
on-chip digital filter greatly simples this filtering
requirement. Figure 51 shows the ADS1602 response out
to 120MHz (f

CLK

= 40MHz). Since the stop band extends

out to 38.6MHz, the anti-alias filter in front of the ADS1602
only needs to be designed to remove higher frequency
signals than this, which can usually be accomplished with
a simple RC circuit on the input driver.

100

120

140

100

Frequency (MHz)

i
t
ud

(
d

)

120

CLK

= 40MHz

Figure 51. Frequency Response Out to 120MHz

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

ANALOG POWER DISSIPATION

An external resistor connected between the RBIAS pin
and the analog ground sets the analog current level, as
shown in Figure 52. The current is inversely proportional
to the resistor value. Table 3 shows the recommended
values of R

BIAS

for different CLK frequencies. Notice that

the analog current can be reduced when using a slower
frequency CLK input because the modulator has more
time to settle. Avoid adding any capacitance in parallel to
R

BIAS

, since this will interfere with the internal circuitry

used to set the biasing.

BIAS

RBIAS

AGND

ADS1602

Figure 52. External Resistor Used to Set Analog

Power Dissipation

Table 3. Recommended R

BIAS

Resistor Values for

Different CLK Frequencies

fCLK

DATA
RATE

RBIAS

TYPICAL POWER DISSIPATION

WITH REFEN HIGH

16MHz

1MHz

140k

200mW

24MHz

1.5MHz

100k

270mW

32MHz

2MHz

60k

390mW

40MHz

2.5MHz

37k

530mW

POWER DOWN (PD)

When not in use, the ADS1602 can be powered down by
taking the PD pin low. All circuitry will be shut down,
including the voltage reference. To minimize the digital
current during power down, stop the clock signal supplied
to the CLK input. There is an internal pull-up resistor of
170k

on the PD pin, but it is recommended that this pin

be connected to IOVDD if not used. Make sure to allow
time for the reference to start up after exiting power-down
mode. The internal reference typically requires 15ms.
After the reference has stabilized, allow at least 100
conversions for the modulator and digital filter to settle
before retrieving data.

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

POWER SUPPLIES

Three supplies are used on the ADS1602: analog (AVDD),
digital (DVDD) and digital I/O (IOVDD). Each supply must
be suitably bypassed to achieve the best performance. It
is recommended that a 1

F and 0.1

F ceramic capacitor

be placed as close to each supply pin as possible. Connect
each supply-pin bypass capacitor to the associated

ground, as shown in Figure 53. Each main supply bus
should also be bypassed with a bank of capacitors from
47

F to 0.1

F, as shown.

The I/O and digital supplies (IOVDD and DVDD) can be
connected together when using the same voltage. In this
case, only one bank of 47

F to 0.1

F capacitors is needed

on the main supply bus, though each supply pin must still
be bypassed with a 1

F and 0.1

F ceramic capacitor.

DGND

AVDD

AGND

AVDD

AGND

AVDD

4.7

0.1

4.7

10k

ADS1602

If using separate analog and

digital ground planes, connect

together on the ADS1602 PCB.

DGND

NOTE: C

= 1

0.1

AGND

AVDD

IOVDD

DVDD

Figure 53. Recommended Power-Supply Bypassing

ADS1602

SBAS341B - DECEMBER 2004 - REVISED APRIL 2005

www.ti.com

LAYOUT ISSUES AND COMPONENT SELECTION

The ADS1602 is a very high-speed, high-resolution data
converter. In order to achieve maximum performance, the
user must give very careful consideration to both the layout
of the printed circuit board (PCB) in addition to the routing
of the traces. Capacitors that are critical to achieve the
best performance from the device should be placed as
close to the pins of the device as possible. These include
capacitors related the analog inputs, the reference and the
power supplies.

For critical capacitors, it is recommended that Class II
dielectrics such as Z5U be avoided. These dielectrics
have a narrow operating temperature, a large tolerance on
the capacitance and will lose up to 20% of the rated
capacitance over 10,000 hours. Rather, select capacitors
with a Class I dielectric. C0G (also known as NP0), for
example, has a tight tolerance <

30PPM/

C and is very

stable over time. Should Class II capacitors be chosen
because of the size constraints, select an X7R or X5R
dielectric to minimize the variations of the capacitor's
critical characteristics.

The resistors used in the circuits driving the input and
reference should be kept as low as possible to prevent
excess thermal noise from degrading the system
performance.

The digital outputs from the device should always be
buffered. This will have a number of benefits: it will reduce
the loading of the internal digital buffers, which decreases
noise generated within the device, and it will also reduce
device power consumption.

APPLICATIONS INFORMATION

Interfacing the ADS1602 to the TMS320 DSP family.

Since the ADS1602 communicates with the host via a
serial interface, the most suitable method to connect to any
of the TMS320 DSPs is via the Multi-channel Buffered
Serial Port (McBSP). A typical connection to the TMS320
DSP is shown in Figure 54.

The McBSP provides a host of functions including:

Full-duplex communication

Double-buffered data registers

Independent framing and clocking for reception and
transmission of data

The sequence begins with a one-time synchronization of
the serial port by the microprocessor. The ADS1602
recognizes the SYNC signal if it is high for a least 1 CLK
period. Transfers are initiated by the ADS1602 after the
SYNC signal is de-asserted by the microprocessor.

The FSO signal from the ADS1602 indicates that data is
available to be read, and is connected to the Frame Sync
Receive (FSR) pin of the DSP. The Clock Receiver (CLKR)
is derived directly from the ADS1602 serial clock output to
ensure continued synchronization of data with the clock.

FSO

ADS1602

SCLK

DOUT

SYNC

FSR

TMS320

CLKR

FSX

Figure 54. ADS1602--TMS320 Interface

Connection

An Evaluation Module (EVM) is available from Texas
Instruments. The module consists of the ADS1602 and
supporting circuits, allowing users to quickly assess the
performance and characteristics of the ADS1602. The
EVM easily connects to various microcontrollers and DSP
systems. For more details, or to download a copy of the
ADS1602EVM User's Guide, visit the Texas Instruments
web site at www.ti.com.

PACKAGING INFORMATION

Orderable Device

Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish

MSL Peak Temp

(3)

ADS1602IPFBR

ACTIVE

TQFP

PFB

1000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

ADS1602IPFBRG4

ACTIVE

TQFP

PFB

1000 Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

ADS1602IPFBT

ACTIVE

TQFP

PFB

250

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

ADS1602IPFBTG4

ACTIVE

TQFP

PFB

250

Green (RoHS &

no Sb/Br)

CU NIPDAU

Level-2-260C-1 YEAR

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco

Plan

The

planned

eco-friendly

classification:

Pb-Free

(RoHS)

Green

(RoHS

Sb/Br)

please

check

http://www.ti.com/productcontent

for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com

19-Apr-2005

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI's terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products

Applications

Amplifiers

amplifier.ti.com

Audio

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

www.ti.com/broadband

Interface

interface.ti.com

Digital Control

www.ti.com/digitalcontrol

Logic

logic.ti.com

Military

www.ti.com/military

Power Mgmt

power.ti.com

Optical Networking

www.ti.com/opticalnetwork

Microcontrollers

microcontroller.ti.com

Security

www.ti.com/security

Telephony

www.ti.com/telephony

Video & Imaging

www.ti.com/video

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

2005, Texas Instruments Incorporated

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADS1602IPFBTG4

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADS1602IPFBTG4