Burr Brown Products
from Texas Instruments
FEATURES
APPLICATIONS
DESCRIPTION
12- Bit
ADC
PLL
S/H
Serializer
1X ADCLK
6X ADCLK
IN1
P
A DCLK
IN1
N
OUT 1
P
OUT 1
N
12- Bit
ADC
S/H
Serializer
IN2
P
IN2
N
OUT 2
P
OUT 2
N
12- Bit
ADC
S/H
Serializer
IN3
P
IN3
N
OUT 3
P
OUT 3
N
LCLK
P
LCLK
N
ADC LK
P
ADC LK
N
12- Bit
ADC
S/H
Serializer
IN4
P
IN4
N
OUT 4
P
OUT 4
N
Reference
R
E
F
T
INT/E XT
V
C
M
R
E
F
B
Registers
S
C
L
K
S
D
A
T
A
C
S
Control
R
E
S
E
T
P
D
ADS5240
SBAS326C JUNE 2004 REVISED DECEMBER 2004
4-Channel, 12-Bit, 40MSPS ADC
with Serial LVDS Interface
An integrated phase lock loop multiplies the incoming
ADC sampling clock by a factor of 12. This 12x clock
Maximum Sample Rate: 40MSPS
is used in the process of serializing the data output
12-Bit Resolution
from each channel. The 12x clock is also used to
generate a 1x and a 6x clock, both of which are
No Missing Codes
transmitted as LVDS clock outputs. The 6x clock is
Power Dissipation: 607mW
denoted by the differential pair LCLK
P
and LCLK
N
,
CMOS Technology
while the 1x clock is denoted by ADCLK
P
and
Simultaneous Sample-and-Hold
ADCLK
N
. The word output of each ADC channel can
be transmitted either as MSB or LSB first. The bit
70.5dBFS SNR at 10MHz IF
coinciding with the rising edge of the 1x clock output
Internal and External References
is the first bit of the word. Data is to be latched by the
3.3V Digital/Analog Supply
receiver on both the rising and falling edges of the 6x
clock.
Serialized LVDS Outputs
Integrated Frame and Bit Patterns
The ADS5240 provides internal references, or can
optionally be driven with external references. Best
MSB and LSB First Modes
performance can be achieved through the internal
Option to Double LVDS Clock Output Currents
reference mode.
Pin- and Format-Compatible Family
The device is available in an HTQFP-64 PowerPAD
HTQFP-64 PowerPADTM Package
package and is specified over a -40
C to +85
C
operating range.
Portable Ultrasound Systems
Tape Drives
Test Equipment
Optical Networking
The ADS5240 is a high-performance, 4-channel,
40MSPS analog-to-digital converter (ADC). Internal
references are provided, simplifying system design
requirements. Low power consumption allows for the
highest of system integration densities. Serial LVDS
(low-voltage differential signaling) outputs reduce the
number of interface lines and package size.
RELATED PRODUCTS
RESOLUTION
SAMPLE RATE
MODEL
(BITS)
(MSPS)
CHANNELS
ADS5242
(1)
12
65
4
(1) Available Q1 2005.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS
(1)
ADS5240
SBAS326C JUNE 2004 REVISED DECEMBER 2004
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
ADS5240IPAP
Tray, 160
ADS5240
HTQFP-64
(2)
PAP
-40
C to +85
C
ADS5240I
ADS5240IPAPT
Tape and Reel, 1000
(1)
For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
(2)
Thermal pad size: 5.29mm
5.29mm (min), 6.50mm
6.50mm (max).
Supply Voltage Range, AVDD
-0.3V to +3.8V
Supply Voltage Range, LVDD
-0.3V to +3.8V
Voltage Between AVSS and LVSS
-0.3V to +0.3V
Voltage Between AVDD and LVDD
-0.3V to +0.3V
Voltage Applied to External REF Pins
-0.3V to +2.4V
All LVDS Data and Clock Outputs
-0.3V to +2.4V
Analog Input Pins
-0.15V to +3.0V
Peak Total Input Current (all inputs)
30mA
Junction Temperature
+105
C
Operating Free-Air Temperature Range, T
A
-40
C to +85
C
Lead Temperature, 1.6mm (1/16" from case for 10s)
220
C
(1)
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not supported.
2
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RECOMMENDED OPERATING CONDITIONS
ADS5240
SBAS326C JUNE 2004 REVISED DECEMBER 2004
ADS5240
MIN
TYP
MAX
UNITS
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
3.0
3.3
3.6
V
Output Driver Supply Voltage, LVDD
3.0
3.3
3.6
V
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL)
20
40
MSPS
Low-Level Voltage Clock Input
0.6
V
High-Level Voltage Clock Input
2.2
V
ADCLK
P
and ADCLK
N
Outputs (LVDS)
20
40
MHz
LCLK
P
and LCLK
N
Outputs (LVDS)
(1)
120
240
MHz
Operating Free-Air Temperature, T
A
-40
+85
C
Thermal Characteristics:
JA
24
C/W
JC
15
C/W
(1)
6
ADCLK.
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
Internal Reference
1
Full-scale range = 2.0V
PP
. Default with internal pull-up.
0
Internal reference is powered down. Common mode of external reference should be within
External Reference
50mV of V
CM
. V
CM
is derived from the internal bandgap voltage.
3
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ELECTRICAL CHARACTERISTICS
ADS5240
SBAS326C JUNE 2004 REVISED DECEMBER 2004
T
MIN
= -40
C and T
MAX
= +85
C. Typical values are at T
A
= 25
C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V differential, transformer coupled inputs, -1dBFS, I
SET
= 56.2k
, internal voltage reference, and
LDVS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5240
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
No Missing Codes
Assured
DNL Differential Nonlinearity
f
IN
= 5MHz
-0.9
0.4
+0.9
LSB
INL Integral Nonlinearity
f
IN
= 5MHz
-2.0
0.75
+2.0
LSB
Offset Error
(1)
-0.75
0.2
+0.75
%FS
Offset Temperature Coefficient
14
ppm/
C
Fixed Attenuation in Channel
(2)
1
%FS
Variable Attenuation in Channel
(3)
0.2
%FS
Gain Error
(4)
REF
T
- REF
B
-5
1.0
+5
%FS
Attenuation Temperature
44
ppm/
C
Coefficient
(5)
POWER SUPPLY
I
CC
Total Supply Current
V
IN
= FS, F
IN
= 5MHz
184
mA
I(AVDD) Analog Supply Current
V
IN
= FS, F
IN
= 5MHz
142
mA
V
IN
= FS, F
IN
= 5MHz,
I(LVDD) Digital Output Driver Supply Current
42
mA
LVDS into 100
Load
Power Dissipation
607
650
mW
Power-Down
Clock Running
95
mW
REFERENCE VOLTAGES
VREF
T
Reference Top (internal)
1.95
2.0
2.05
V
VREF
B
Reference Bottom (internal)
0.95
1.0
1.05
V
V
CM
Common-Mode Voltage
1.45
1.5
1.55
V
V
CM
Output Current
(6)
50mV Change in Voltage
2
mA
VREF
T
Reference Top (external)
1.875
V
VREF
B
Reference Bottom (external)
1.125
V
External Reference Input Current
(7)
1.0
mA
ANALOG INPUT
Differential Input Capacitance
4.0
pF
Analog Input Common-Mode Range
V
CM
0.05
V
Differential Input Voltage Range
1.5
2.02
V
PP
Differential Input Signal at 4V
PP
Voltage Overhead Recovery Time
4.0
CLK Cycles
Recovery to Within 1% of Code
Input Bandwidth
-3dBFS
300
MHz
DIGITAL DATA OUTPUTS
Data Bit Rate
240
480
MBPS
(1)
Offset error is the deviation of the average code from mid-code for a zero input. Offset error is expressed in terms of % of full-scale.
(2)
Fixed attenuation in the channel arises due to a fixed attenuation of about 1% in the sample-and-hold amplifier. When the differential
voltage at the analog input pins are changed from -V
REF
to +V
REF
, the swing of the output code is expected to deviate from the full-scale
code (4096LSB) by the extent of this fixed attenuation.
NOTE: V
REF
is defined as (REF
T
- REF
B
).
(3)
Variable attenuation in the channel refers to the attenuation of the signal in the channel over and above the fixed attenuation.
(4)
The reference voltages are trimmed at production so that (VREF
T
- VREF
B
) is within
50mV of the ideal value of 1V. It does not include
fixed attenuation.
(5)
The attenuation temperature coefficient refers to the temperature coefficient of the attenuation in the channel. It does not account for the
variation of the reference voltages with temperature.
(6)
V
CM
provides the common-mode current for the inputs of all four channels when the inputs are AC-coupled. The V
CM
output current
specified is the additional drive of the V
CM
buffer if loaded externally.
(7)
Average current drawn from the reference pins in the external reference mode.
4
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AC CHARACTERISTICS
ADS5240
SBAS326C JUNE 2004 REVISED DECEMBER 2004
T
MIN
= -40
C and T
MAX
= +85
C. Typical values are at T
A
= 25
C, clock frequency = 40MSPS, 50% clock duty cycle,
AVDD = 3.3V, LVDD = 3.3V differential, transformer coupled inputs, -1dBFS, I
SET
= 56.2k
, internal voltage reference, and
LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5240
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
f
IN
= 1MHz
87
dBc
SFDR Spurious-Free Dynamic Range
f
IN
= 5MHz
78
85
dBc
f
IN
= 10MHz
85
dBc
f
IN
= 1MHz
95
dBc
HD
2
2nd-Order Harmonic Distortion
f
IN
= 5MHz
85
95
dBc
f
IN
= 10MHz
90
dBc
f
IN
= 1MHz
87
dBc
HD
3
3rd-Order Harmonic Distortion
f
IN
= 5MHz
78
85
dBc
f
IN
= 10MHz
85
dBc
f
IN
= 1MHz
70.5
dBFS
SNR Signal-to-Noise Ratio
f
IN
= 5MHz
68
70.5
dBFS
f
IN
= 10MHz
70
dBFS
f
IN
= 1MHz
70
dBFS
SINAD Signal-to-Noise and Distortion
f
IN
= 5MHz
67
70
dBFS
f
IN
= 10MHz
69.5
dBFS
f
1
= 9.5MHz at -7dBFS
dBc
IMD Two-Tone Intermodulation Distortion
-88
f
2
= 10.2MHz at -7dBFS
ENOB Effective Number of Bits
f
IN
= 5MHz
11.3
Bits
Signal Applied to 3 Channels; Measurement Taken
-90
dBc
Crosstalk
on the Channel with No Input Signal
5
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