Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS(
- ORDERING INFORMATION
- RECOMMENDED OPERATING CONDITIONS
- REFERENCE SELECTION
- ELECTRICAL CHARACTERISTICS
- AC CHARACTERISTICS
- LVDS DIGITAL DATA AND CLOCK OUTPUTS
- SWITCHING CHARACTERISTICS
- SERIAL INTERFACE TIMING
- SERIAL INTERFACT TIMING TABLE
- LVDS TIMING DIAGRAM (PER ADC CHANNEL)
- RESET TIMING
- POWER-DOWN TIMING
- PIN CONFIGURATION
- PIN DESCRIPTIONS
- TYPICAL CHARACTERISTICS
- THEORY OF OPERATION
- OVERVIEW
- DRIVING THE ANALOG INPUTS
- INPUT OVER-VOLTAGE RECOVERY
- REFERENCE CIRCUIT DESIGN
- CLOCKING
- LVDS BUFFERS
- NOISE COUPLING ISSUES
- POWER-DOWN MODE
- SUPPLY SEQUENCE
FEATURES
D
Maximum Sample Rate: 70MSPS
D
12-Bit Resolution
D
No Missing Codes
D
Power Dissipation: 1.1W
D
CMOS Technology
D
Simultaneous Sample-and-Hold
D
70.5dB SNR at 10MHz IF
D
Serialized LVDS Outputs Meet or Exceed the
Requirements of ANSI TIA/EIA-644-A
Standard
D
Internal and External References
D
3.3V Digital/Analog Supply
D
TQFP-80 PowerPAD
Package
APPLICATIONS
D
Portable Ultrasound Systems
D
Tape Drives
D
Test Equipment
DESCRIPTION
The ADS5273 is a high-performance, 70MSPS, 8-channel
parallel analog-to-digital converter (ADC). An internal
reference is provided, simplifying system design
requirements. Low power consumption allows for the
highest of system integration densities. Serial LVDS
outputs reduce the number of interface lines and package
size.
In LVDS (low-voltage differential signaling), an integrated
phase lock loop multiplies the incoming ADC sampling
clock by a factor of 6. This high-frequency LVDS clock is
used in the data serialization and transmission process
and is converted to an LVDS signal for transmission in
parallel with the data. Providing this additional LVDS clock
allows for easy delay matching. The word output of each
internal ADC is serialized and transmitted either MSB or
LSB first. The bit following the rising edge of the ADC clock
output is the first bit of the word.
The ADS5273 provides an internal reference, or can
optionally be driven with an external reference. Best
performance can be achieved through the internal
reference mode.
The device is available in a PowerPAD TQFP-80 package
and is specified over a -40
C to +85
C operating range.
12-Bit
ADC
PLL
S/H
Serializer
1X ADCLK
6X ADCLK
IN1
P
ADCLK
IN1
N
OUT1
P
OUT1
N
12-Bit
ADC
S/H
Serializer
IN2
P
IN2
N
OUT2
P
OUT2
N
12-Bit
ADC
S/H
Serializer
IN3
P
IN3
N
OUT3
P
OUT3
N
LCLK
P
LCLK
N
ADCLK
P
ADCLK
N
12-Bit
ADC
S/H
Serializer
IN4
P
IN4
N
OUT4
P
OUT4
N
12-Bit
ADC
S/H
Serializer
IN5
P
IN5
N
OUT5
P
OUT5
N
12-Bit
ADC
S/H
Serializer
IN6
P
IN6
N
OUT6
P
OUT6
N
12-Bit
ADC
S/H
Serializer
IN7
P
IN7
N
OUT7
P
OUT7
N
12-Bit
ADC
S/H
Serializer
Reference
IN8
P
IN8
N
RE
F
T
INT/EXT
V
CM
RE
F
B
OUT8
P
OUT8
N
Registers
SC
L
K
SD
A
T
A
CS
Control
RE
S
E
T
PD
PRODUCT PREVIEW
ADS5273
SBAS305A - JANUARY 2004 - REVISED FEBRUARY 2004
8-Channel, 12-Bit, 70MSPS ADC
with Serialized LVDS Interface
PRODUCT PREVIEW information concerns products in the formative or design
phase of development. Characteristic data and other specifications are design
goals. Texas Instruments reserves the right to change or discontinue these
products without notice.
www.ti.com
Copyright
2004, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
ADS5273
SBAS305A - JANUARY 2004 - REVISED FEBRUARY 2004
www.ti.com
2
ABSOLUTE MAXIMUM RATINGS
(1)
Supply Voltage Range, AVDD
-0.3V to 3.8V
. . . . . . . . . . . . . . . . . .
Supply Voltage Range, LVDD
-0.3V to 3.8V
. . . . . . . . . . . . . . . . . .
Voltage Between AVSS and LVSS
-0.3V to 0.3V
. . . . . . . . . . . . . .
Voltage Between AVDD and LVDD
-0.3V to 0.3V
. . . . . . . . . . . . . .
Voltages Applied to External REF Pins
-0.3V to 2.4V
. . . . . . . . . .
All LVDS Data and Clock Outputs
-0.3V to 2.4V
. . . . . . . . . . . . . .
ADCLK Peak Input Current
TBD
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak Total Input Current (all inputs)
-30mA
. . . . . . . . . . . . . . . . . . .
Operating Free-Air Temperature Range, TA
-40
C to 85
C
. . . . . .
Lead Temperature 1.6mm (1/16
from case for 10s)
235
C
. . . . . .
(1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not supported.
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handled with appropriate precautions. Failure to observe
proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5273
HTQFP-80
PFP
-40
C to +85
C
ADS5273IPFP
ADS5273IPFP
Tray, 96
ADS5273IPFPT
Tape and Reel, 250
(1) For the most current specification and package information, refer to our web site at www.ti.com.
RECOMMENDED OPERATING CONDITIONS
ADS5273
MIN
TYP
MAX
UNIT
SUPPLIES AND REFERENCES
Analog Supply Voltage, AVDD
3.0
3.3
3.6
V
Output Driver Supply Voltage, LVDD
3.0
3.3
3.6
V
CLOCK INPUT AND OUTPUTS
ADCLK Input Sample Rate (low-voltage TTL), 1/tC
20
70
MSPS
Low Voltage Level Clock
1
V
High Voltage Level Clock
2
V
ADCLKP and ADCLKN Outputs (LVDS)
35
70
MHz
LCLKP and LCLKN Outputs (LVDS)(1)
210
420
MHz
Operating Free-Air Temperature, TA
-40
+85
C
(1) 6
ADCLK.
REFERENCE SELECTION
MODE
INT/EXT
DESCRIPTION
2.0VPP Internal Reference
1
Default with internal pull-up.
External Reference
0
Internal reference is powered down. Common mode of external reference should be within
50mV of VCM. VCM is derived from the internal bandgap voltage.
PRODUCT PREVIEW
ADS5273
SBAS305A - JANUARY 2004 - REVISED FEBRUARY 2004
www.ti.com
3
ELECTRICAL CHARACTERISTICS
TMIN = -40
C, and TMAX = +85
C. Typical values are at TA = 25
C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, -0.5dBFS, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
ADS5273
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
No Missing Codes
Assured
DNL
Differential Nonlinearity
TBD
0.5
TBD
LSB
INL
Integral Nonlinearity
TBD
1
TBD
LSB
Midscale Offset Error(1)
TBD
TBD
mV
Offset Temperature Coefficient
TBD
ppm/
C
Fixed Gain Error(2)
TBD
1.0
TBD
%FS
Gain Temperature Coefficient
TBD
%/
C
POWER SUPPLY
ICC Total Supply Current
VIN = FS, FIN = 10MHz
333
mA
I(AVDD)
Analog Supply Current
VIN = FS, FIN = 10MHz
289
mA
I(LVDD)
Digital Output Driver Supply Current
VIN = FS, FIN = 10MHz,
LVDS Into 100
Load
44
mA
Power Dissipation
VIN = FS, FIN = 10MHz
1.1
W
REFERENCE VOLTAGES
VREFT Reference Top (internal)
2.0
V
VREFN Reference Bottom (internal)
1.0
V
VCM Common-Mode Voltage
1.5
V
VCM Output Current
TBD
mA
VREFT Reference Top (external)
1.875
V
VREFB Reference Bottom (external)
1.125
V
Reference Input Resistance(3)
TBD
ANALOG INPUT
DC
Differential Input Resistance
1.2
k
Differential Input Capacitance
7
pF
Analog Input Common-Mode Range
VCM
0.05
V
Differential Input Voltage Range
1.5
2.0
VPP
Voltage Overload Recovery Time
Differential Input Signal at 4VPP
Recovery to Within 1% of Code
4
CLK
Cycles
Input Bandwidth
-3dBFS
300
MHz
DIGITAL DATA OUTPUTS
Data Bit Rate
420
840
MBPS
SERIAL INTERFACE
SCLK
Serial Clock Input Frequency
20
MHz
VIN LOW Input Low Voltage
0
0.6
V
VIN HIGH Input High Voltage
2.1
VDD
V
Input Current
TBD
A
Input Pin Capacitance
5
pF
(1) Offset Error is the measured deviation of the midscale transition from the ideal midscale transition.
(2) Gain Error is the difference between the nominal and actual offset point on the transfer function after the offset error has been corrected to zero.
The gain point is the mid-step value when the digital output is full-scale.
(3) Average switching current drawn from external reference. DC component of current is internally generated even in external reference mode.
PRODUCT PREVIEW
ADS5273
SBAS305A - JANUARY 2004 - REVISED FEBRUARY 2004
www.ti.com
4
AC CHARACTERISTICS
TMIN = -40
C, TMAX = +85
C. Typical values are at TA = 25
C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, -0.5dBFS, internal voltage reference, and 2VPP differential input, unless otherwise noted.
ADS5273
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC CHARACTERISTICS
fIN = 1MHz
85
dBc
SFDR
Spurious-Free Dynamic Range
fIN = 5MHz
TBD
85
dBc
SFDR
Spurious-Free Dynamic Range
fIN = 10MHz
85
dBc
fIN = 20MHz
80
dBc
fIN = 1MHz
90
dBc
HD2 2nd-Order Harmonic Distortion
fIN = 5MHz
TBD
87
dBc
HD2 2nd-Order Harmonic Distortion
fIN = 10MHz
80
dBc
fIN = 20MHz
76
dBc
fIN = 1MHz
87
dBc
HD3 3rd-Order Harmonic Distortion
fIN = 5MHz
TBD
84
dBc
HD3 3rd-Order Harmonic Distortion
fIN = 10MHz
77
dBc
fIN = 20MHz
73
dBc
fIN = 1MHz
70.5
dBFS
SNR
Signal-to-Noise Ratio
fIN = 5MHz
TBD
70.5
dBFS
SNR
Signal-to-Noise Ratio
fIN = 10MHz
70.5
dBFS
fIN = 20MHz
70.5
dBFS
fIN = 1MHz
70
dBFS
SINAD
Signal-to-Noise and Distortion
fIN = 5MHz
TBD
70
dBFS
SINAD
Signal-to-Noise and Distortion
fIN = 10MHz
70
dBFS
fIN = 20MHz
70
dBFS
ENOB
Effective Number of Bits
fIN = 10MHz
11.3
Bits
Crosstalk
Signal Applied to 7 Channels; Measurement Taken on the
Channel with No Input Signal
-85
dBc
LVDS DIGITAL DATA AND CLOCK OUTPUTS
Test conditions at IO = 3.5mA, RLOAD = 100
, and CLOAD = 9pF. All LVDS specifications are characterized but not tested.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DC SPECIFICATIONS
VOH Output Voltage High, OUTP or OUTN
RLOAD = 100
1%; See LVDS Timing Diagram, Page 7
1340
1475
mV
VOL Output Voltage Low, OUTP or OUTN
RLOAD = 100
1%
925
1038
mV
VOD
Output Differential Voltage
RLOAD = 100
1%
325
350
375
mV
VOS Output Offset Voltage
RLOAD = 100
1%; See LVDS Timing Diagram, Page 7
1.125
1.250
1.275
V
RO Output Impedance, Single-Ended
VCM = 1.0V and 1.4V
TBD
RO Mismatch Between OUTP and OUTN
VCM = 1.0V and 1.4V
TBD
%
CO Output Capacitance
VCM = 1.0V and 1.4V
3
4
5
pF
VOD
Change in
VOD
Between 0 and 1
RLOAD = 100
1%
25
mV
VOS Change Between 0 and 1
RLOAD = 100
1%
25
mV
ISOUTP,
ISOUTN
Output Short-Circuit Current
Drivers Shorted to Ground
40
mA
ISOUTNP Output Current
Drivers Shorted Together
12
mA
IXN
,
IXP
Power-Off Output Leakage
VCC = 0V
10
mA
DRIVER AC SPECIFICATIONS
Clock
Clock Signal Duty Cycle
6
ADCLK
45
50
55
%
tSKEW1
tpHLP - tpLHN
or
tpHLN - tpLHP
,
Differential Skew
Any Differential Pair on Package(1)
50
ps
tSKEW2
tpDIFF[X] - tpDIFF[Y]
,
Channel-to-Channel Skew(3)
Any Two Signals on Package(2)
100
ps
tRISE/tFALL VOD Rise Time or VOD Fall Time
ZLOAD = 100
, CI = 9pF, IO = 2.5mA
400
ZLOAD = 100
, CI = 9pF, IO = 3.5mA
250
ps
ZLOAD = 100
, CI = 9pF, IO = 4.5mA
200
ps
ZLOAD = 100
, CI = 9pF, IO = 6mA
150
ps
(1) Skew measurements are made at the 50% point of the transition.
(2) Skew measurements made at 0V differential (that is, the crossing of single-ended signals).
(3) Where x is any one of the parallel channels and y is any other channel.
PRODUCT PREVIEW
ADS5273
SBAS305A - JANUARY 2004 - REVISED FEBRUARY 2004
www.ti.com
5
SWITCHING CHARACTERISTICS
TMIN = -40
C, TMAX = +85
C. Typical values are at TA = 25
C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V,
LVDD = 3.3V, -0.5dBFS, internal voltage reference, and 2VPP differential input, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SWITCHING SPECIFICATIONS
tSAMPLE
14.3
50
ns
tD(A) Aperture Delay
120
ps
Aperture Jitter (uncertainty)
1
ps
tD(pipeline) Latency
6.5
cycles
tPROP Propagation Delay
5
ns
SERIAL INTERFACE TIMING
Data is shifted in MSB first.
PARAMETER
DESCRIPTION
MIN
TYP
MAX
UNIT
t1
Serial CLK Period
50
ns
t2
Serial CLK High Time
13
ns
t3
Serial CLK Low Time
13
ns
t4
Data Setup Time
5
ns
t5
Data Hold Time
5
ns
PRODUCT PREVIEW
Start Sequence
t
1
MSB
D6
D5
D4
D3
D2
D1
D0
t
2
t
3
t
4
t
5
ADCLK
CS
SCLK
SDATA
Outputs change on
next rising clock edge
after CS goes high.
Data latched on
each rising edge of SCLK.
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