Document Outline
- FEATURES
- DESCRIPTION
- APPLICATIONS
- ABSOLUTE MAXIMUM RATINGS(1)
- EVALUATION BOARD
- PACKAGE/ORDERING INFORMATION(1)
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATION
- PIN DESCRIPTIONS
- TIMING DIAGRAM
- REFERENCE AND FULL-SCALE RANGE SELECT TABLE
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- ANALOG INPUTS
- TYPES OF APPLICATIONS
- DIFFERENTIAL INPUTS
- INPUT FULL- SCALE RANGE VERSUS PERFORMANCE
- INPUT BIASING ( VCM)
- INPUT IMPEDANCE
- ANALOG INPUT DRIVER CONFIGURATIONS
- TRANSFORMER-COUPLED INTERFACE CIRCUITS
- TRANSFORMER- COUPLED, SINGLE- ENDED- TO DIFFERENTIAL CONFIGURATION
- AC-COUPLED, DIFFERENTIAL INTERFACE WITH GAIN
- REFERENCE
- REFERENCE OPERATION
- USING EXTERNAL REFERENCES
- DIGITAL INPUTS AND OUTPUTS
- CLOCK INPUT
- MINIMUM SAMPLING RATE
- DATA OUTPUT FORMAT (BTC)
- OUTPUT ENABLE (OE)\
- POWER DOWN (PD)
- OUTPUT LOADING
- POWER SUPPLIES
- POWER DISSIPATION
- DIGITAL OUTPUT DRIVER SUPPLY (VDRV)
- LAYOUT AND DECOUPLING CONSIDERATIONS
14-Bit, 40MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
HIGH DYNAMIC RANGE:
High SFDR: 83dB at 10MHz f
IN
High SNR: 75dB at 10MHz f
IN
q
PREMIUM TRACK-AND-HOLD:
Differential Inputs
Selectable Full-Scale Input Range
q
LOW POWER: 850mW
q
FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking Down to
0.5Vp-p
Variable Threshold Level
DESCRIPTION
The ADS5421 is a high-dynamic range 14-bit, 40MHz,
pipelined Analog-to-Digital Converter (ADC). It includes a
high-bandwidth linear track-and-hold amplifier that gives
excellent spurious performance up to and beyond the Nyquist
rate. The clock input can accept a low-level differential sine
wave or square wave signal down to 0.5Vp-p, further improving
the Signal-to-Noise Ratio (SNR) performance.
The ADS5421 has a 4Vp-p differential input range
(2Vp-p 2 inputs) for optimum Spurious-Free Dynamic
Range (SFDR). The differential operation gives the lowest
even-order harmonic components. A lower input voltage can
also be selected using the internal references, further
optimizing SFDR.
The ADS5421 is available in a small LQFP-64 package.
APPLICATIONS
q
COMMUNICATIONS RECEIVERS
q
TEST INSTRUMENTATION
q
PROFESSIONAL CCD IMAGING
ADS5421
SBAS237D DECEMBER 2001 REVISED JULY 2004
www.ti.com
Copyright 2001-2004 Texas Instruments, Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ADS5421
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
14-Bit
Pipelined
ADC
Core
Reference and
Mode Select
Reference Ladder
and Driver
Timing Circuitry
Error
Correction
Logic
3-State
Outputs
T&H
D0
D13
+V
S
ADS5421
CLK
DV
CLK
OE
SEL2
REFB
V
REF
REFT
VDRV
IN
1Vp-p
1Vp-p
CM
(+2.5V)
SEL1
IN
ADS5421
2
SBAS237D
www.ti.com
ELECTRICAL CHARACTERISTICS
T
A
= specified temperature range, typical at +25
C, +V
SA
= +V
SD
= +5V, differential input range = 1.5V to 3.5V each input (4Vp-p), sampling rate = 40MHz, internal
reference, VDRV = +3V, and 1dBFS, unless otherwise noted.
ADS5421Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
14 Tested
Bits
SPECIFIED TEMPERATURE RANGE
Ambient Air
40 to +85
C
ANALOG INPUT
Standard Differential Input Range
Full-Scale = 4Vp-p
1.5
3.5
V
Common-Mode Voltage
2.5
V
Optional Input Ranges
Selectable
2Vp-p or 3Vp-p
V
Analog Input Bias Current
1
A
Analog Input Bandwidth
500
MHz
Input Capacitance
9
pF
CONVERSION CHARACTERISTICS
Sample Rate
1M
40M
Samples/sec
Data Latency
10
Clk Cyc
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
0.5
LSB
f = 10MHz
0.5
1.0
LSB
No Missing Codes
Tested
Integral Nonlinearity Error, f = 1MHz
2.5
LSB
Spurious-Free Dynamic Range
(1)
f = 1MHz
88
dBFS
(2)
f = 10MHz
78
85
dBFS
f = 30MHz
82
dBFS
2-Tone Intermodulation Distortion
(3)
f = 14.5MHz and 15.5MHz (7dB each tone)
90
dBc
Signal-to-Noise Ratio (SNR)
f = 1MHz
76
dBFS
f = 10MHz
72
75
dBFS
f = 30MHz
75
dBFS
Signal-to-(Noise + Distortion) (SINAD)
f = 1MHz
75
dB
f = 10MHz
72
74
dB
f = 30MHz
74
dBFS
Effective Number of Bits
(4)
f = 1MHz
12.2
Bits
Output Noise
IN and IN tied to CM
0.4
LSB rms
Aperture Delay Time
3
ns
Aperture Jitter
1
ps rms
Over-Voltage Recovery Time
5
ns
Full-Scale Step Acquisition Time
5
ns
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
+V
SA
, +V
SD
, VDRV ............................................................................... +6V
Analog Input .......................................................... (0.3V) to (+V
S
+ 0.3V)
Logic Input ............................................................ (0.3V) to (+V
S
+ 0.3V)
Case Temperature ......................................................................... +100
C
Junction Temperature .................................................................... +150
C
Storage Temperature ..................................................................... +150
C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the
device at these or any other conditions beyond those specified is not implied.
ABSOLUTE MAXIMUM RATINGS
(1)
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
ADS5421Y
LQFP-64
PM
40
C to +85
C
ADS5421Y
ADS5421Y/T
Tape and Reel, 250
"
"
"
"
"
ADS5421Y/R
Tape and Reel, 1500
PACKAGE/ORDERING INFORMATION
(1)
NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
PRODUCT
DESCRIPTION
USER'S GUIDE
ADS5421EVM
Populated Evaluation Board
SBAU084
EVALUATION BOARD
ADS5421
3
SBAS237D
www.ti.com
DIGITAL INPUTS
Clock Input
Rising Edge of Convert Clock
+0.5
+V
SD
Vp-p
Logic Family (other than clock inputs)
+3V/+5V Compatible CMOS
High Level Input Current
(5)
(V
IN
= 5V)
100
A
Low Level Input Current (V
IN
= 0V)
10
A
High Level Input Voltage
+2.0
V
Low Level Input Voltage
+1.0
V
Input Capacitance
5
pF
DIGITAL OUTPUTS
(6)
Logic Family
+3V/+5V Compatible CMOS
Logic Coding
Straight Offset Binary
Low Output Voltage (I
OL
= 50
A to 0.5mA)
VDRV = 3V
+0.2
V
High Output Voltage (I
OH
= 50
A to 0.5mA)
+2.5
V
Low Output Voltage (I
OL
= 50
A to 1.6mA)
VDRV = 5V
+0.2
V
High Output Voltage (I
OH
= 50
A to 1.6mA)
+2.5
V
3-State Enable Time
OE = LOW
20
40
ns
3-State Disable Time
OE = HIGH
2
10
ns
Output Capacitance
5
pF
ACCURACY
Zero Error (Referred to FS)
at +25
C
0.5
1.0
%FS
Zero Error Drift (Referred to FS)
15
ppm/
C
Gain Error
(7)
at +25
C
0.2
1.0
%FS
Gain Error Drift
(7)
35
ppm/
C
Power-Supply Rejection of Gain
V
S
=
5%
68
dB
Internal REF Tolerance (V
REFT
, V
REFB
)
Deviation from Ideal
10
50
mV
External REF Voltage Range
0.9
2
2.025
V
Reference Input Resistance
1.0
k
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +V
SA
, +V
SD
Operating, f
IN
= 10MHz
+4.75
+5.0
+5.25
V
Supply Current: +I
S
Operating, f
IN
= 10MHz
170
mA
Output Driver Supply Current (VDRV)
12
mA
Power Dissipation: VDRV = 5V
900
mW
VDRV = 3V
850
925
mW
Power Down
Operating
40
mW
Thermal Resistance,
JA
LQFP-64
48
C/W
NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) 2-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the 2-tone fundamental envelope.
(4) Effective Number of Bits (ENOB) is defined by (SINAD 1.76)/6.02. (5) A 50k
pull-down resistor is inserted internally. (6) Recommended maximum
capacitance loading, 15pF. (7) Includes internal reference.
ELECTRICAL CHARACTERISTICS
(Cont.)
T
A
= specified temperature range, typical at +25
C, +V
SA
= +V
SD
= +5V, differential input range = 1.5V to 3.5V each input (4Vp-p), sampling rate = 40MHz, internal
reference, VDRV = +3V, and 1dBFS, unless otherwise noted.
ADS5421Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
ADS5421
4
SBAS237D
www.ti.com
1
+V
SA
Analog Supply Voltage
2
+V
SA
Analog Supply Voltage
3
+V
SD
Digital Supply Voltage
4
+V
SD
Digital Supply Voltage
5
+V
SD
Digital Supply Voltage
6
+V
SD
Digital Supply Voltage
7
GND
Ground
8
GND
Ground
9
I
CLK
Clock Input
10
I
CLK
Complementary Clock Input
11
GND
Ground
12
GND
Ground
13
GNDRV
Ground
14
GNDRV
Ground
15
DNC
Do Not Connect
16
DV
Data Valid Pulse: HI = Data Valid
17
O
B1
Data Bit 1 (D13) (MSB)
18
O
B2
Data Bit 2 (D12)
19
O
B3
Data Bit 3 (D11)
20
O
B4
Data Bit 4 (D10)
21
O
B5
Data Bit 5 (D9)
22
O
B6
Data Bit 6 (D8)
23
O
B7
Data Bit 7 (D7)
24
O
B8
Data Bit 8 (D6)
25
O
B9
Data Bit 9 (D5)
26
O
B10
Data Bit 10 (D4)
27
O
B11
Data Bit 11 (D3)
28
O
B12
Data Bit 12 (D2)
29
O
B13
Data Bit 13 (D1)
30
O
B14
Data Bit 14 (D0) (LSB)
31
NC
No Internal Connection
32
NC
No Internal Connection
33
VDRV
Output Driver Supply Voltage
34
VDRV
Output Driver Supply Voltage
35
VDRV
Output Driver Supply Voltage
36
GNDRV
Ground
37
GNDRV
Ground
38
GNDRV
Ground
39
OE
Output Enable: HI = High Impedance
40
I
PD
Power Down: HI = Power Down; LO = Normal
41
I
BTC
HI = Binary Two's Complement
42
GND
Ground
43
GND
Ground
44
SEL2
Reference Select 2: See Table on Page 5
45
SEL1
Reference Select 1: See Table on Page 5
46
V
REF
Internal Reference Voltage
47
GND
Ground
48
GND
Ground
49
GND
Ground
50
REFB
Bottom Reference Voltage Bypass
51
CM
Common-Mode Voltage (Midscale)
52
REFT
Top Reference Voltage Bypass
53
GND
Ground
54
GND
Ground
55
GND
Ground
56
GND
Ground
57
I
IN
Complementary Analog Input
58
GND
Ground
59
I
IN
Analog Input
60
GND
Ground
61
REFBY
Reference Bypass
62
GND
Ground
63
+V
SA
Analog Supply Voltage
64
+V
SA
Analog Supply Voltage
PIN
I/O
DESIGNATOR
DESCRIPTION
PIN
I/O
DESIGNATOR
DESCRIPTION
PIN DESCRIPTIONS
PIN CONFIGURATION
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
GND
V
REF
SEL1
SEL2
GND
GND
BTC
PD
OE
GNDRV
GNDRV
GNDRV
VDRV
VDRV
VDRV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+V
SA
+V
SA
+V
SD
+V
SD
+V
SD
+V
SD
GND
GND
CLK
CLK
GND
GND
GNDRV
GNDRV
DNC
DV
+V
SA
+V
SA
GND
REFBY
GND
IN
GND
IN
GND
GND
GND
GND
REFT
CM
REFB
GND
B1 (MSB)
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14 (LSB)
NC
NC
64
63
62
61
60
59
58
57
56
55
54
17
18
19
20
21
22
23
24
25
26
27
53
52
51
50
49
28
29
30
31
32
ADS5421Y
Top View
TQFP
ADS5421
5
SBAS237D
www.ti.com
10 Clock Cycles
Data Invalid
t
D
t
DV
t
L
t
H
t
CONV
N 10
N 9
N 8
N 7
N 6
N 5
N 4
N 3
N 2
N 1
N
Data Out
Data Valid Output
Clock
Analog In
N
t
2
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 9
N + 10
t
1
TIMING DIAGRAM
REFERENCE AND FULL-SCALE RANGE SELECT TABLE
DESIRED FULL-SCALE RANGE
SEL1
SEL2
INTERNAL V
REF
4Vp-p
GND
GND
2V
3Vp-p
GND
+V
SA
1.5V
2Vp-p
V
REF
GND
1V
NOTE: For external reference operation, tie V
REF
to +V
SA
. The full-scale range will be 2x the reference value. For example, selecting a 2V external reference
will set the full-scale values of 1.5V to 3.5V for both IN and IN inputs.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
CONV
Convert Clock Period
25
1
s
ns
t
L
Clock Pulse LOW
11.5
t
CONV
/2
ns
t
H
Clock Pulse HIGH
11.5
t
CONV
/2
ns
t
D
Aperture Delay
3
ns
t
1
Data Hold Time, C
L
= 0pF
3.9
7.2
ns
t
2
New Data Delay Time, C
L
= 15pF max
12.7
ns
t
DV
Data Valid Output, C
L
= 15pF
4.4
ns
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