ADS7822

DESCRIPTION

The ADS7822 is a 12-bit sampling analog-to-digital
converter (A/D) with guaranteed specifications over a
2.7V to 3.6V supply range. It requires very little power
even when operating at the full 75kHz rate. At lower
conversion rates, the high speed of the device enables
it to spend most of its time in the power down mode--
the power dissipation is less than 60

W at 7.5kHz.

The ADS7822 also features operation from 2.0V to
5V, a synchronous serial interface, and a differential
input. The reference voltage can be set to any level
within the range of 50mV to V

Ultra low power and small size make the ADS7822
ideal for battery operated systems. It is also a perfect
fit for remote data acquisition modules, simultaneous
multi-channel systems, and isolated data acquisition.
The ADS7822 is available in a plastic mini-DIP-8, an
SOIC-8, or an MSOP-8 package.

12-Bit High Speed 2.7V

microPower Sampling

ANALOG-TO-DIGITAL CONVERTER

1996 Burr-Brown Corporation

PDS-1358C

Printed in U.S.A., May, 2000

International Airport Industrial Park · Mailing Address: PO Box 11400, Tucson, AZ 85734 · Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 · Tel: (520) 746-1111

Twx: 910-952-1111 · Internet: http://www.burr-brown.com/ · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132

FEATURES

75kHz SAMPLING RATE

MICRO POWER:
0.54mW at 75kHz
0.06mW at 7.5kHz

POWER DOWN: 3

A max

MINI-DIP-8, SOIC-8, AND MSOP-8

DIFFERENTIAL INPUT

SERIAL INTERFACE

SAR

Control

Serial

Interface

OUT

Comparator

S/H Amp

CS/SHDN

DCLOCK

+In

REF

CDAC

APPLICATIONS

BATTERY OPERATED SYSTEMS

REMOTE DATA ACQUISITION

ISOLATED DATA ACQUISITION

SIMULTANEOUS SAMPLING,
MULTI-CHANNEL SYSTEMS

OPA658

ADS7822

For most current data sheet and other product

information, visit www.burr-brown.com

ADS7822

SPECIFICATIONS

At 40

C to +85

C, +V

= +2.7V, V

REF

= +2.5V, f

SAMPLE

= 75kHz, f

CLK

= 16 · f

SAMPLE

, unless otherwise specified.

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

ADS7822

ADS7822B

ADS7822C

PARAMETER

CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

ANALOG INPUT
Full-Scale Input Span

+In (In)

REF

Absolute Input Range

+In

0.2

+0.2

0.2

+1.0

Capacitance

Leakage Current

SYSTEM PERFORMANCE
Resolution

Bits

No Missing Codes

Bits

Integral Linearity Error

0.5

0.25

0.75

LSB

(1)

Differential Linearity Error

0.5

0.25

0.75

LSB

Offset Error

LSB

Gain Error

LSB

Noise

Vrms

Power Supply Rejection

SAMPLING DYNAMICS
Conversion Time

Clk Cycles

Acquisition Time

1.5

Clk Cycles

Throughput Rate

kHz

DYNAMIC CHARACTERISTICS
Total Harmonic Distortion

= 2.5Vp-p at 1kHz

SINAD

= 2.5Vp-p at 1kHz

Spurious Free Dynamic Range

= 2.5Vp-p at 1kHz

REFERENCE INPUT
Voltage Range

0.05

Resistance

CS = GND, f

SAMPLE

= 0Hz

CS = V

Current Drain

At Code 710h

SAMPLE

= 7.5kHz

0.8

CS = V

0.001

DIGITAL INPUT/OUTPUT
Logic Family

CMOS

Logic Levels:

= +5

2.0

5.5

= +5

0.3

0.8

= 250

2.1

= 250

0.4

Data Format

Straight Binary

POWER SUPPLY REQUIREMENTS
V

Specified Performance

2.7

3.6

See Notes 2 and 3

2.0

2.7

See Note 3

3.6

5.25

Quiescent Current

200

325

SAMPLE

= 7.5kHz

(4,5)

SAMPLE

= 7.5kHz

(5)

180

Power Down

CS = V

TEMPERATURE RANGE
Specified Performance

+85

Specifications same as ADS7822.

Notes: (1) LSB means Least Significant Bit. With V

REF

equal to +2.5V, one LSB is 0.61mV. (2) The maximum clock rate of the ADS7822 is less than 1.2MHz in this

power supply range. (3) See the Typical Performance Curves for more information. (4) f

CLK

= 1.2MHz, CS = V

for 145 clock cycles out of every 160. (5) See the

Power Dissipation section for more information regarding lower sample rates.

ADS7822

ELECTROSTATIC
DISCHARGE SENSITIVITY

Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits
be handled and stored using appropriate ESD protection
methods.

ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.

ABSOLUTE MAXIMUM RATINGS

(1)

....................................................................................................... +6V

Analog Input .............................................................. 0.3V to (V

+ 0.3V)

Logic Input ............................................................................... 0.3V to 6V
Case Temperature ......................................................................... +100

Junction Temperature .................................................................... +150

Storage Temperature ..................................................................... +125

External Reference Voltage .............................................................. +5.5V

NOTE: (1) Stresses above these ratings may permanently damage the device.

PIN

NAME

DESCRIPTION

REF

Reference Input.

+In

Non Inverting Input.

Inverting Input. Connect to ground or to remote ground sense point.

GND

Ground.

CS/SHDN

Chip Select when LOW, Shutdown Mode when HIGH.

OUT

The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The
second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 12 edges.

DCLOCK

Data Clock synchronizes the serial data transfer and determines conversion speed.

Power Supply.

PIN CONFIGURATION

PIN ASSIGNMENTS

DCLOCK

OUT

CS/SHDN

REF

+In

GND

ADS7822

PDIP-8,

SOIC-8,

MSOP-8

PACKAGE/ORDERING INFORMATION

MAXIMUM

INTEGRAL

DIFFERENTIAL

LINEARITY

PACKAGE

SPECIFICATION

ERROR

DRAWING

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

(LSB)

PACKAGE

NUMBER

(1)

RANGE

MARKING

(2)

NUMBER

(3)

MEDIA

ADS7822E

MSOP-8

337

C to +85

A22

ADS7822E/250

Tape and Reel

ADS7822E

ADS7822E/2K5

ADS7822EB

MSOP-8

337

C to +85

A22

ADS7822EB/250

Tape and Reel

ADS7822EB

ADS7822EB/2K5

ADS7822EC

0.75

MSOP-8

337

C to +85

A22

ADS7822EC/250

Tape and Reel

ADS7822EC

ADS7822EC/2K5

ADS7822P

Plastic DIP-8

006

C to +85

ADS7822P

Rails

ADS7822PB

Plastic DIP-8

006

C to +85

ADS7822PB

Rails

ADS7822PC

0.75

Plastic DIP-8

006

C to +85

ADS7822PC

Rails

ADS7822U

SOIC-8

182

C to +85

ADS7822U

Rails

ADS7822U

ADS7822U/2K5

Tape and Reel

ADS7822UB

SOIC-8

182

C to +85

ADS7822UB

Rails

ADS7822UB

ADS7822UB/2K5 Tape and Reel

ADS7822UC

0.75

SOIC-8

182

C to +85

ADS7822UC

Rails

ADS7822UC

ADS7822UC/2K5 Tape and Reel

NOTE: (1) For detail drawing and dimension table, please see end of data sheet or Package Drawing File on Web. (2) Performance Grade information is marked
on the reel. (3) Models with a slash(/) are available only in Tape and reel in quantities indicated (e.g. /250 indicates 250 units per reel, /2K5 indicates 2500 devices
per reel). Ordering 2500 pieces of "ADS7822E/2K5" will get a single 2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to the
www.burr-brown.com web site under Applications and Tape and Reel Orientation and Dimensions.

ADS7822

TYPICAL PERFORMANCE CURVES

At T

= +25

C, V

= +2.7V, V

REF

= +2.5V, f

SAMPLE

= 75kHz, f

CLK

= 16 · f

SAMPLE

, unless otherwise specified.

DIFFERENTIAL LINEARITY ERROR vs CODE

1.00

0.75

0.50

0.25

0.00

0.25

0.50

0.75

1.00

Differential Linearity Error (LSB)

2048

4095

Code

INTEGRAL LINEARITY ERROR vs CODE

1.00

0.75

0.50

0.25

0.00

0.25

0.50

0.75

1.00

Integral Linearity Error (LSB)

2048

4095

Code

QUIESCENT CURRENT vs V

400

350

300

250

200

150

100

Quiescent Current (

(V)

MAXIMUM SAMPLE RATE vs V

1000

100

Sample Rate (kHz)

(V)

SUPPLY CURRENT vs TEMPERATURE

350

300

250

200

150

100

Supply Current (

100

Temperature (

POWER DOWN SUPPLY CURRENT

vs TEMPERATURE

120

100

Supply Current (nA)

100

Temperature (

ADS7822

TYPICAL PERFORMANCE CURVES

(Cont.)

At T

= +25

C, V

= +2.7V, V

REF

= +2.5V, f

SAMPLE

= 75kHz, f

CLK

= 16 · f

SAMPLE

, unless otherwise specified.

CHANGE IN GAIN vs TEMPERATURE

0.15

0.1

0.05

0.1

0.15

Delta from 25

C (LSB)

100

Temperature (

CHANGE IN OFFSET vs REFERENCE VOLTAGE

1.2

1.0

0.8

0.6

0.4

0.2

0.0

0.2

0.4

0.6

0.8

Change in Offset (LSB)

Reference Voltage (V)

= 5V

CHANGE IN OFFSET vs TEMPERATURE

0.6

0.4

0.2

0.4

0.6

Delta from 25

C (LSB)

100

Temperature (

CHANGE IN GAIN vs REFERENCE VOLTAGE

2.5

2.0

1.5

1.0

0.5

0.0

0.5

1.0

1.5

Change in Gain (LSB)

Reference Voltage (V)

= 5V

EFFECTIVE NUMBER OF BITS

vs REFERENCE VOLTAGE

11.75

11.5

11.25

10.75

10.5

10.25

Effective Number of Bits (rms)

0.1

Reference Voltage (V)

= 5V

PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE

Peak-to-Peak Noise (LSB)

0.1

Reference Voltage (V)

= 5V

ADS7822

SPURIOUS FREE DYNAMIC RANGE and

SIGNAL-TO-NOISE RATIO vs FREQUENCY

100

Spurious Free Dynamic Range

and Signal-to-Noise Ratio (dB)

100

Frequency (kHz)

Spurious Free Dynamic Range

Signal-to-Noise Ratio

TOTAL HARMONIC DISTORTION vs FREQUENCY

100

Total Harmonic Distortion (dB)

100

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY

100

Signal-to-(Noise + Distortion) (dB)

100

Frequency (kHz)

SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL

Signal-to-(Noise Ratio Plus Distortion) (dB)

Input Level (dB)

REFERENCE CURRENT vs SAMPLE RATE

Reference Current (

Sample Rate (kHz)

REFERENCE CURRENT vs TEMPERATURE

(Code = 710h)

Reference Current (

100

Temperature (

TYPICAL PERFORMANCE CURVES

(Cont.)

At T

= +25

C, V

= +2.7V, V

REF

= +2.5V, f

SAMPLE

= 75kHz, f

CLK

= 16 · f

SAMPLE

, unless otherwise specified.

ADS7822

TYPICAL PERFORMANCE CURVES

(Cont.)

At T

= +25

C, V

= +2.7V, V

REF

= +2.5V, f

SAMPLE

= 75kHz, f

CLK

= 16 · f

SAMPLE

, unless otherwise specified.

CHANGE IN INTEGRAL LINEARITY AND DIFFERENTIAL

LINEARITY vs REFERENCE VOLTAGE

0.20

0.15

0.10

0.05

0.00

0.05

0.10

Delta from +2.5V Reference (LSB)

Reference Voltage (V)

= 5V

Change in Integral

Linearity (LSB)

Change in Differential

Linearity (LSB)

POWER SUPPLY REJECTION vs RIPPLE FREQUENCY

Power Supply Rejection (dB)

100

1000

10000

Ripple Frequency (kHz)

THEORY OF OPERATION

The ADS7822 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a 0.6

CMOS process. The architecture and process allow the
ADS7822 to acquire and convert an analog signal at up to
75,000 conversions per second while consuming very little
power.

The ADS7822 requires an external reference, an external
clock, and a single power source (V

). The external refer-

ence can be any voltage between 50mV and V

. The value

of the reference voltage directly sets the range of the analog
input. The reference input current depends on the conversion
rate of the ADS7822.

The external clock can vary between 10kHz (625Hz through-
put) and 1.2MHz (75kHz throughput). The duty cycle of the
clock is essentially unimportant as long as the minimum high
and low times are at least 400ns (V

= 2.7V or greater).

The minimum clock frequency is set by the leakage on the
capacitors internal to the ADS7822.

The analog input is provided to two input pins: +In and In.
When a conversion is initiated, the differential input on these
pins is sampled on the internal capacitor array. While a
conversion is in progress, both inputs are disconnected from
any internal function.

The digital result of the conversion is clocked out by the
DCLOCK input and is provided serially, most significant bit
first, on the D

OUT

pin. The digital data that is provided on the

OUT

pin is for the conversion currently in progress--there

is no pipeline delay. It is possible to continue to clock the
ADS7822 after the conversion is complete and to obtain the
serial data least significant bit first. See the digital timing
section for more information.

ANALOG INPUT

The +In and In input pins allow for a differential input
signal. Unlike some converters of this type, the In input is
not re-sampled later in the conversion cycle. When the
converter goes into the hold mode, the voltage difference
between +In and In is captured on the internal capacitor
array.

The range of the In input is limited to 0.2V to +1V.
Because of this, the differential input can be used to reject
only small signals that are common to both inputs. Thus, the
In input is best used to sense a remote signal ground that
may move slightly with respect to the local ground potential.

The input current on the analog inputs depends on a number
of factors: sample rate, input voltage, source impedance, and
power down mode. Essentially, the current into the ADS7822
charges the internal capacitor array during the sample period.
After this capacitance has been fully charged, there is no
further input current. The source of the analog input voltage
must be able to charge the input capacitance (25pF) to a
12-bit settling level within 1.5 clock cycles. When the
converter goes into the hold mode or while it is in the power
down mode, the input impedance is greater than 1G

Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the In
input should not drop below GND 200mV or exceed
GND + 1V. The +In input should always remain within the
range of GND 200mV to V

+ 200mV. Outside of these

ranges, the converter's linearity may not meet specifications.

ADS7822

REFERENCE INPUT

The external reference sets the analog input range. The
ADS7822 will operate with a reference in the range of 50mV
to V

. There are several important implications of this.

As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the LSB (least significant bit) size and is equal
to the reference voltage divided by 4096. This means that any
offset or gain error inherent in the A/D converter will appear
to increase, in terms of LSB size, as the reference voltage is
reduced.

The noise inherent in the converter will also appear to
increase with lower LSB size. With a 2.5V reference, the
internal noise of the converter typically contributes only 0.32
LSB peak-to-peak of potential error to the output code. When
the external reference is 50mV, the potential error contribu-
tion from the internal noise will be 50 times larger--16
LSBs. The errors due to the internal noise are gaussian in
nature and can be reduced by averaging consecutive conver-
sion results.

For more information regarding noise, consult the typical
performance curves "Effective Number of Bits vs Reference
Voltage" and "Peak-to-Peak Noise vs Reference Voltage."
Note that the effective number of bits (ENOB) figure is
calculated based on the converter's signal-to-(noise + distor-
tion) ratio with a 1kHz, 0dB input signal. SINAD is related
to ENOB as follows

SINAD = 6.02 · ENOB + 1.76

With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Because the LSB size is lower, the converter will also
be more sensitive to external sources of error such as nearby
digital signals and electromagnetic interference.

DIGITAL INTERFACE

SIGNAL LEVELS

The digital inputs of the ADS7822 can accommodate logic
levels up to 6V regardless of the value of V

. Thus, the

ADS7822 can be powered at 3V and still accept inputs from
logic powered at 5V.

The CMOS digital output (D

OUT

) will swing 0V to V

. If

is 3V and this output is connected to a 5V CMOS logic

input, then that IC may require more supply current than
normal and may have a slightly longer propagation delay.

SERIAL INTERFACE

The ADS7822 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface as
shown in Figure 1 and Table I. The DCLOCK signal syn-
chronizes the data transfer with each bit being transmitted on
the falling edge of DCLOCK. Most receiving systems will
capture the bitstream on the rising edge of DCLOCK. How-
ever, if the minimum hold time for D

OUT

is acceptable, the

system can use the falling edge of DCLOCK to capture each
bit.

FIGURE 1. ADS7822 Basic Timing Diagrams.

CS/SHDN

OUT

DCLOCK

DATA

SUCS

CYC

CONV

Power
Down

SMPL

Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output LSB-First data then followed with zeroes indefinitely.

B11

(MSB)

B10 B9

B1 B0

(1)

Null

Bit

Hi-Z

B11 B10

Null

Bit

CS/SHDN

OUT

DCLOCK

CONV

DATA

SUCS

CSD

CYC

Power Down

SMPL

Note: (1) After completing the data transfer, if further clocks are applied with CS
LOW, the A/D will output zeroes indefinitely.

DATA

: During this time, the bias current and the comparator power down and the reference input

becomes a high impedance node, leaving the CLK running to clock out LSB-First data or zeroes.

B11

(MSB)

B10 B9

Null

Bit

Hi-Z

B10 B11

(1)

CSD

ADS7822

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

SMPL

Analog Input Sample Time

1.5

2.0

Clk Cycles

CONV

Conversion Time

Clk Cycles

CYC

Throughput Rate

kHz

CSD

CS Falling to

DCLOCK LOW

SUCS

CS Falling to

DCLOCK Rising

hDO

DCLOCK Falling to

Current D

OUT

Not Valid

dDO

DCLOCK Falling to Next

130

200

OUT

Valid

dis

CS Rising to D

OUT

Tri-State

DCLOCK Falling to D

OUT

175

Enabled

OUT

Fall Time

200

OUT

Rise Time

110

200

periods, D

OUT

will output the conversion result, most signifi-

cant bit first. After the least significant bit (B0) has been
output, subsequent clocks will repeat the output data but in a
least significant bit first format.

After the most significant bit (B11) has been repeated, D

OUT

will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.

DATA FORMAT

The output data from the ADS7822 is in straight binary
format as shown in Table II. This table represents the ideal
output code for the given input voltage and does not include
the effects of offset, gain error, or noise.

FIGURE 2. Timing Diagrams and Test Circuits for the Parameters in Table I.

TABLE I. Timing Specifications (V

= 2.7V and above,

C to +85

A falling CS signal initiates the conversion and data transfer.
The first 1.5 to 2.0 clock periods of the conversion cycle are
used to sample the input signal. After the second falling
DCLOCK edge, D

OUT

is enabled and will output a LOW

value for one clock period. For the next 12 DCLOCK

DESCRIPTION

ANALOG VALUE

Full Scale Range

REF

Least Significant

REF

/4096

Bit (LSB)

BINARY CODE

HEX CODE

Full Scale

REF

1 LSB

1111 1111 1111

FFF

Midscale

REF

1000 0000 0000

800

Midscale 1 LSB

REF

/2 1 LSB

0111 1111 1111

7FF

Zero

0000 0000 0000

000

DIGITAL OUTPUT

STRAIGHT BINARY

TABLE II. Ideal Input Voltages and Output Codes.

OUT

1.4V

Test Point

100pF
C

LOAD

Load Circuit for t

dDO

, t

, and t

Voltage Waveforms for D

OUT

Rise and Fall Times, t

, t

Voltage Waveforms for D

OUT

Delay Times, t

dDO

Voltage Waveforms for t

dis

NOTES: (1) Waveform 1 is for an output with internal conditions such that the output
is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with
internal conditions such that the output is LOW unless disabled by the output control.

Voltage Waveforms for t

Load Circuit for t

dis

and t

OUT

Test Point

dis

Waveform 2, t

dis

Waveform 1

100pF
C

LOAD

dis

CS/SHDN

OUT

Waveform 1

(1)

OUT

Waveform 2

(2)

90%

10%

B11

CS/SHDN

DCLOCK

OUT

dDO

OUT

DCLOCK

hDO

ADS7822

POWER DISSIPATION

The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design allow the ADS7822 to
convert at up to a 75kHz rate while requiring very little
power. Still, for the absolute lowest power dissipation, there
are several things to keep in mind.

The power dissipation of the ADS7822 scales directly with
conversion rate. So, the first step to achieving the lowest
power dissipation is to find the lowest conversion rate that
will satisfy the requirements of the system.

In addition, the ADS7822 is in power down mode under two
conditions: when the conversion is complete and whenever
CS is HIGH (see Figure 1). Ideally, each conversion should
occur as quickly as possible, preferably, at a 1.2MHz clock
rate. This way, the converter spends the longest possible time
in the power down mode. This is very important as the
converter not only uses power on each DCLOCK transition
(as is typical for digital CMOS components) but also uses
some current for the analog circuitry, such as the comparator.
The analog section dissipates power continuously, until the
power down mode is entered.

Figure 3 shows the current consumption of the ADS7822
versus sample rate. For this graph, the converter is clocked at
1.2MHz regardless of the sample rate--CS is HIGH for the
remaining sample period. Figure 4 also show current con-
sumption versus sample rate. However, in this case, the
DCLOCK period is 1/16th of the sample period--CS is
HIGH for one DCLOCK cycle out of every 16.

There is an important distinction between the power down
mode that is entered after a conversion is complete and the
full power down mode which is enabled when CS is HIGH.
While both shutdown the analog section, the digital section
is completely shutdown only when CS is HIGH. Thus, if CS
is left LOW at the end of a conversion and the converter is
continually clocked, the power consumption will not be as
low as when CS is HIGH. See Figure 5 for more information.

Power dissipation can also be reduced by lowering the power
supply voltage and the reference voltage. The ADS7822 will
operate over a V

range of 2.0V to 5.25V. However, at

voltages below 2.7V, the converter will not run at a 75kHz
sample rate. See the typical performance curves for more
information regarding power supply voltage and maximum
sample rate.

SHORT CYCLING

Another way of saving power is to utilize the CS signal to
short cycle the conversion. Because the ADS7822 places the
latest data bit on the D

OUT

line as it is generated, the

converter can easily be short cycled. This term means that the
conversion can be terminated at any time. For example, if
only 8 bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after the
8th bit has been clocked out.

FIGURE 3. Maintaining f

CLK

at the Highest Possible Rate

Allows Supply Current to Drop Linearly with
Sample Rate.

FIGURE 4. Scaling f

CLK

Reduces Supply Current Only

Slightly with Sample Rate.

1000

100

Supply Current (

0.1

100

Sample Rate (kHz)

= 25

= 2.7V

REF

= 2.5V

CLK

= 16 · f

SAMPLE

FIGURE 5. Shutdown Current with CS HIGH is 50nA

Typically, Regardless of the Clock. Shutdown
Current with CS LOW Varies with Sample
Rate.

10.0

8.0

6.0

4.0

2.0

0.0

0.00

Supply Current (

0.1

100

Sample Rate (kHz)

0.050

= 25

= 2.7V

REF

= 2.5V

CLK

= 16 · f

SAMPLE

CS LOW (GND)

CS HIGH (V

)

1000

100

Supply Current (

0.1

100

Sample Rate (kHz)

= 5.0V

REF

= 5.0V

= 2.7V

REF

= 2.5V

= 25

CLK

= 1.2MHz

ADS7822

This technique can be used to lower the power dissipation (or
to increase the conversion rate) in those applications where
an analog signal is being monitored until some condition
becomes true. For example, if the signal is outside a prede-
termined range, the full 12-bit conversion result may not be
needed. If so, the conversion can be terminated after the first
n-bits, where n might be as low as 3 or 4. This results in lower
power dissipation in both the converter and the rest of the
system, as they spend more time in the power down mode.

LAYOUT

For optimum performance, care should be taken with the
physical layout of the ADS7822 circuitry. This will be
particularly true if the reference voltage is low and/or the
conversion rate is high. At a 75kHz conversion rate, the
ADS7822 makes a bit decision every 830ns. That is, for each
subsequent bit decision, the digital output must be updated
with the results of the last bit decision, the capacitor array
appropriately switched and charged, and the input to the
comparator settled to a 12-bit level all within one clock cycle.

The basic SAR architecture is sensitive to spikes on the
power supply, reference, and ground connections that occur
just prior to latching the comparator output. Thus, during any
single conversion for an n-bit SAR converter, there are n
"windows" in which large external transient voltages can
easily affect the conversion result. Such spikes might origi-
nate from switching power supplies, digital logic, and high
power devices, to name a few. This particular source of error
can be very difficult to track down if the glitch is almost
synchronous to the converter's DCLOCK signal--as the
phase difference between the two changes with time and
temperature, causing sporadic misoperation.

With this in mind, power to the ADS7822 should be clean
and well bypassed. A 0.1

F ceramic bypass capacitor should

be placed as close to the ADS7822 package as possible. In
addition, a 1 to 10

F capacitor and a 5

series

resistor may be used to lowpass filter a noisy supply.

The reference should be similarly bypassed with a 0.1

capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, be careful that the op amp

can drive the bypass capacitor without oscillation (the series
resistor can help in this case). Keep in mind that while the
ADS7822 draws very little current from the reference on
average, there are still instantaneous current demands placed
on the external reference circuitry.

Also, keep in mind that the ADS7822 offers no inherent
rejection of noise or voltage variation in regards to the
reference input. This is of particular concern when the
reference input is tied to the power supply. Any noise and
ripple from the supply will appear directly in the digital
results. While high frequency noise can be filtered out as
described in the previous paragraph, voltage variation due to
the line frequency (50Hz or 60Hz), can be difficult to
remove.

The GND pin on the ADS7822 should be placed on a clean
ground point. In many cases, this will be the "analog"
ground. Avoid connecting the GND pin too close to the
grounding point for a microprocessor, microcontroller, or
digital signal processor. If needed, run a ground trace directly
from the converter to the power supply connection point. The
ideal layout will include an analog ground plane for the
converter and associated analog circuitry.

APPLICATION CIRCUITS

Figures 6 and 7 show some typical application circuits for
the ADS7822. Figure 6 uses an ADS7822 and a multiplexer
to provide for a flexible data acquisition circuit. A resistor
string provides for various voltages at the multiplexer input.
The selected voltage is buffered and driven into V

REF

. As

shown in Figure 6, the input range of the ADS7822 is
programmable to 100mV, 200mV, 300mV, or 400mV. The
100mV range would be useful for sensors such as the
thermocouple shown.

Figure 7 shows a basic data acquisition system. The ADS7822
input range is 0V to V

, as the reference input is connected

directly to the power supply. The 5

resistor and 1

F to

F capacitor filter the microcontroller "noise" on the

supply, as well as any high-frequency noise from the supply
itself. The exact values should be picked such that the filter
provides adequate rejection of the noise.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADS7822C

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADS7822C