ADS7832
Autocalibrating, 4-Channel, 12-Bit
ANALOG-TO-DIGITAL CONVERTER
DESCRIPTION
The ADS7832 is a monolithic CMOS 12-bit analog-
to-digital converter with internal sample/hold and four-
channel multiplexer. It is designed and tested for full
dynamic performance with input signals to 50kHz.
The 5V single-supply requirements and standard CS,
RD, and WR control signals make the part easy to use
in microprocessor applications. Conversion results are
available in two bytes through an 8-bit three-state
output bus.
The ADS7832 is available in a 28-pin plastic DIP and
28-lead PLCC, fully specified for operation over the
industrial 40
C to +85
C temperature range.
FEATURES
q
PIN COMPATIBLE TO ADC7802 AND
ADS7803
q
SINGLE SUPPLY: +5V OR +3.3V
q
LOW POWER: 14mW plus Power Down
q
SIGNAL-TO-(NOISE + DISTORTION)
RATIO OVER TEMPERATURE:
69dB min with f
IN
= 1kHz
66dB min with f
IN
= 50kHz
q
FAST CONVERSION TIME: 8.5
s
Including Acquisition (117kHz Sampling
Rate)
q
FOUR-CHANNEL INPUT MULTIPLEXER
q
AUTOCAL: No offset or Gain Adjust
Required
ADS7832
ADS7832
1996 Burr-Brown Corporation
PDS-1332B
Printed in U.S.A. April, 1998
Three-State
Input/Output
CS
Control
Logic
RD
WR
SFR
BUSY
8-Bit
Data Bus
Capacitor Array
Sampling ADC
Analog
Multiplexer
AIN0
AIN1
AIN2
AIN3
Calibration
Microcontroller
and Memory
A0
A1
Clock
V
REF
+
V
REF
Address
Latch and
Decoder
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
ADS7832
2
ADS7832BP/ADS7832BN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
12
Bits
ANALOG INPUT
V
A
= V
D
= V
REF+
= 3.0V
Voltage Input Range
0
V
REF+
V
Input Capacitance
40
pF
On State Bias Current
100
nA
Off State Bias Current
T
A
= +25
C
10
nA
T
A
= 40
C to +85
C
100
nA
On Resistance Multiplexer
400
Off Resistance Multiplexer
10
M
Channel Separation
F
IN
= 1kHz, V
REF
+ = 3.0V
0.5
LSB
REFERENCE INPUT
For Specified Performance: V
REF
+
V
A
V
V
REF
0
V
For Derated Performance
(2)
: V
REF
+
(V
REF
+) (V
REF
)
2.5V
2.5
V
A
V
V
REF
0
0.5
V
Input Reference Current
100
200
A
THROUGHPUT SPEED
Conversion Time With External Clock (Including
Multiplexer Settling Time and Acquisition Time)
CLK = 1MHz
17
s
CLK = 500kHz
34
s
With Internal Clock Using Recommended
T
A
= +25
C
30
s
Clock Components
T
A
= 40
C to +85
C
30
s
Slew Rate
2
V/
s
Multiplexer Settling Time to 1/2 LSB
0.5
s
Multiplexer Access Time
20
ns
SAMPLING DYNAMICS
Full Power Bandwidth
3dB
2
MHz
Aperture Jitter
ps
Aperture Delay
SRF D2 LOW
(3)
5
s
SFR D2 HIGH
5
ns
DC ACCURACY
Integral Nonlinearity, All Channels
SFR D2 LOW
0.75
LSB
(4)
SFR D2 HIGH, Internal Clock or Sampling
0.5
LSB
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
0.6
LSB
Command Asynchronous to External Clock
Differential Nonlinearity
0.75
LSB
No Missing Codes
Guaranteed
Gain Error
All Channels
0.5
LSB
Gain Error Drift
Between Calibration Cycles
0.2
ppm/
C
Offset Error
All Channels
SFR D2 LOW
0.75
LSB
SFR D2 HIGH, Internal Clock or Sampling
1
LSB
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
4
LSB
Command Asynchronous to External Clock
Offset Error Drift
Between Calibration Cycles
SFR D2 LOW
0.2
ppm/
C
SFR D2 HIGH, Internal Clock or Sampling
0.5
ppm/
C
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
1
ppm/
C
Command Asynchronous to External Clock
Channel-to-Channel Mismatch
SFR D2 LOW
0.25
LSB
SFR D2 HIGH, Internal Clock or Sampling
0.5
LSB
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
1
LSB
Command Asynchronous to External Clock
Power Supply Sensitivity
V
D
= V
A
= +3.3V
10% (without recalibration)
0.125
LSB
AC ACCURACY
Signal-to-(Noise + Distortion) Ratio
f
IN
= 1kHz
69
71
dB
(1)
f
IN
= 50kHz
66
69
dB
Total Harmonic Distortion
f
IN
= 50kHz
75
dB
Signal-to-Noise Ratio
f
IN
= 50kHz
70
dB
Spurious Free Dynamic Range
f
IN
= 1kHz
85
dB
f
IN
= 50kHz
82
dB
SPECIFICATIONS
ADS7832 Electrical Specifications with 3.3V Supply
V
A
= V
D
= V
REF
+ = 3.3V
10%; V
REF
= AGND = DGND = 0V; CLK = 1MHz external, T
A
= 40
C to +85
C, after calibration at any temperature, unless otherwise specified.
3
ADS7832
SPECIFICATIONS
(CONT)
ADS7832 Electrical Specifications with 3.3V Supply
V
A
= V
D
= V
REF
+ = 3.3V
10%; V
REF
= AGND = DGND = 0V; CLK = 1MHz external, T
A
= 40
C to +85
C, after calibration at any temperature, unless otherwise specified.
ADS7832BP/ADS7832BN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
T
These specifications need to be added based on performance of final silicon.
NOTES: (1) All specifications in dB are referred to a full-scale input range. (2) Over this range, total error will typically not exceed
1LSB. (3) In this mode, the ADS7832
acquires the input signal for five clock cycles after a start command, before the input is held and conversion begins. (4) LSB means Least Significant Bit. For a 0V to
5V input range, one LSB is 1.22mV. For a 0V to 2.5V input range, one LSB is 610
V.
DIGITAL INPUTS
Voltage Levels: V
IL
0.3
+0.8
V
V
IH
0.7 V
D
V
D
+0.3V
V
Current Levels: I
IL
CAL (Internal Pull-Up)
10
A
I
IL
All Other Inputs
10
A
I
IH
SFR (Internal Pull-Down)
90
A
I
IH
CLK
1.5
mA
I
IH
All Other Inputs
10
A
I
IH
Power Down Mode (SFR D3 HIGH)
100
nA
DIGITAL OUTPUTS
Data Format
Parallel 12 Bits in Two Bytes
Data Coding
Straight Binary
V
OL
I
SINK
= 1.6mA
0.2 V
D
V
V
OH
I
SOURCE
= 200
A
0.8 V
D
V
Leakage Current
High-Z State, V
OUT
= 0V to V
D
1
A
Output Capacitance
High-Z State
4
pF
CALIBRATION TIMING
Calibration Cycle
Power On or Power Failure
37393
Clock Cycles
Calibration Cycle
During Normal Operation
4625
Clock Cycles
DIGITAL TIMING
Bus Access Time
83
ns
Bus Relinquish Time
83
ns
POWER SUPPLIES
Supply Voltage for Specified Performance: V
A
Tested at 3.0V
3
3.3
V
V
D
Tested at 3.0V
3
3.3
V
Supply Current: I
A
2.5
3
mA
I
D
300
500
A
Power Dissipation
Power Up Mode or During Conversion
7.5
mW
Power Down Mode, No Clock Running
50
W
TEMPERATURE RANGE
Specification
40
+85
C
Storage
65
+150
C
ADS7832
4
SPECIFICATIONS
ADS7832 Electrical Specifications with 5V Supply
V
A
= V
D
= 5V
10%; V
REF
+ = 5.0V; V
REF
= AGND = DGND = 0V; CLK = 1MHz external 50%
2% Duty Cycle, T
A
= 40
C to +85
C, after calibration at any temperature,
unless otherwise specified.
ADS7832BP/ADS7832BN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
12
Bits
ANALOG INPUT
Voltage Input Range
V
D
= V
A
= V
REF
+ = 5V
0
5
V
Input Capacitance
40
pF
On State Bias Current
100
nA
Off State Bias Current
T
A
= +25
C
10
nA
T
A
= 40
C to +85
C
100
nA
On Resistance Multiplexer
400
Off Resistance Multiplexer
10
M
Channel Separation
F
IN
= 1kHz, V
D
= V
A
= V
REF
+ = 5V
0.5
LSB
REFERENCE INPUT
For Specified Performance:
V
REF
= V
A
= 5V
V
REF
+
V
A
V
V
REF
0
V
For Derated Performance
(2)
:
(V
REF
+) (V
REF
)
2.5V
V
REF
+
2.5
V
A
V
V
REF
0
1
V
Input Reference Current
100
200
A
THROUGHPUT SPEED
Conversion Time With External Clock (Including
CLK = 2MHz
8.5
s
Multiplexer Settling Time and Acquisition Time)
CLK = 1MHz
17
s
CLK = 500kHz
34
s
With Internal Clock Using Recommended
T
A
= +25
C
30
s
Clock Components
T
A
= 40
C to +85
C
30
s
Slew Rate
2
mV/
s
Multiplexer Settling Time to 1/2 LSB
0.5
s
Multiplexer Access Time
20
ns
SAMPLING DYNAMICS
Full Power Bandwidth
3dB
4
MHz
Aperture Jitter
10
ps
Aperture Delay
SRF D2 LOW
(3)
2.5
s
SFR D2 HIGH
5
ns
DC ACCURACY
Integral Nonlinearity, All Channels
SFR D2 LOW
0.75
LSB
(4)
SFR D2 HIGH, Internal Clock or Sampling
0.5
LSB
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
0.6
LSB
Command Asynchronous to External Clock
Differential Nonlinearity
0.75
LSB
No Missing Codes
Guaranteed
Gain Error
All Channels
0.50
LSB
Gain Error Drift
Between Calibration Cycles
0.2
ppm/
C
Offset Error
All Channels
SFR D2 LOW
0.75
LSB
SFR D2 HIGH, Internal Clock or Sampling
1
LSB
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
4
LSB
Command Asynchronous to External Clock
Offset Error Drift
Between Calibration Cycles
SFR D2 LOW
0.2
ppm/
C
SFR D2 HIGH, Internal Clock or Sampling
0.5
ppm/
C
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
1
ppm/
C
Command Asynchronous to External Clock
Channel-to-Channel Mismatch
SFR D2 LOW
0.25
LSB
SFR D2 HIGH, Internal Clock or Sampling
0.5
LSB
Command Synchronous to External Clock
SFR D2 HIGH, Sampling
1.0
LSB
Command Asynchronous to External Clock
Power Supply Sensitivity
V
D
= V
A
= +5V
10% (without recalibration)
0.125
LSB
5
ADS7832
AC ACCURACY
Signal-to-(Noise + Distortion) Ratio
f
IN
= 1kHz
69
71
dB
(1)
f
IN
= 50kHz
66
69
dB
Total Harmonic Distortion
f
IN
= 50kHz
75
dB
Signal-to-Noise Ratio
f
IN
= 50kHz
70
dB
Spurious Free Dynamic Range
f
IN
= 1kHz
85
dB
f
IN
= 50kHz
82
dB
DIGITAL INPUTS
Voltage Levels: V
IL
CLK
0.3
0.8
V
V
IH
CLK
3.5
V
D
+0.3V
V
V
IL
All Others
0.3
0.8
V
V
IH
All Others
2.4
V
D
+0.3V
V
Current Levels: I
IL
CAL (Internal Pull-Up)
10
A
I
IL
All Other Inputs
10
A
I
IH
SFR (Internal Pull-Down)
90
A
I
IH
CLK
1.5
mA
I
IH
All Other Inputs
10
A
I
IH
Power Down Mode (SFR D3 HIGH)
100
nA
DIGITAL OUTPUTS
Data Format
Parallel 12 Bits in Two Bytes
Data Coding
Straight Binary
V
OL
I
SINK
= 1.6mA
0.4
V
V
OH
I
SOURCE
= 200
A
4
V
Leakage Current
High-Z State
1
A
Output Capacitance
High-Z State
4
pF
CALIBRATION TIMING
Calibration Cycle
Power On or Power Failure
37393
Clock Cycles
Calibration Cycle
During Normal Operation
4625
Clock Cycles
DIGITAL TIMING
Bus Access Time
83
ns
Bus Relinquish Time
83
ns
POWER SUPPLIES
Supply Voltage for Specified Performance: V
A
Tested at 5.5V
5
5.5
V
V
D
Tested at 5.5V
5
5.5
V
Supply Current: I
A
Tested at 5.5V
2.5
5.5
mA
I
D
Tested at 5.5V
300
500
A
Power Dissipation
Power Up Mode or During Conversion
14
mW
Power Down Mode, No Clock Running
50
W
TEMPERATURE RANGE
Specification
40
85
C
Storage
65
150
C
SPECIFICATIONS
(CONT)
ADS7832 Electrical Specifications with 5V Supply
V
A
= V
D
= 5V
10%; V
REF
+ = 5V; V
REF
= AGND = DGND = 0V; CLK = 1MHz external 50%
2% Duty Cycle, T
A
= 40
C to +85
C, after calibration at any temperature, unless
otherwise specified.
ADS7832BP/ADS7832BN
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
T
These specifications need to be added based on performance of final silicon.
NOTES: (1) All specifications in dB are referred to a full-scale input range. (2) Over this range, total error will typically not exceed
1LSB. (3) In this mode, the ADS7832
acquires the input signal for five clock cycles after a start command, before the input is held and conversion begins. (4) LSB means Least Significant Bit. For a 0V to
5V input range, one LSB is 1.22mV. For a 0V to 2.5V input range, one LSB is 610
V.
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