ADS7844
12-Bit, 8-Channel Serial Output Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
SINGLE SUPPLY: 2.7V to 5V
q
8-CHANNEL SINGLE-ENDED OR
4-CHANNEL DIFFERENTIAL INPUT
q
UP TO 200kHz CONVERSION RATE
q
1 LSB MAX INL AND DNL
q
GUARANTEED NO MISSING CODES
q
72dB SINAD
q
SERIAL INTERFACE
q
20-LEAD QSOP AND
20-LEAD SSOP PACKAGES
q
ALTERNATE SOURCE FOR MAX147
DESCRIPTION
The ADS7844 is an 8-channel, 12-bit sampling ana-
log-to-digital converter (ADC) with a synchronous
serial interface. Typical power dissipation is 3mW at
a 200kHz throughput rate and a +5V supply. The
reference voltage (V
REF
) can be varied between 100mV
and V
CC
, providing a corresponding input voltage
range of 0V to V
REF
. The device includes a shutdown
mode which reduces power dissipation to under 1
W.
The ADS7844 is guaranteed down to 2.7V operation.
Low power, high speed, and on-board multiplexer
make the ADS7844 ideal for battery operated systems
such as personal digital assistants, portable multi-
channel data loggers, and measurement equipment.
The serial interface also provides low-cost isolation
for remote data acquisition. The ADS7844 is available
in a 20-lead QSOP package and the MAX147 equiva-
lent 20-lead SSOP package and is guaranteed over the
40
C to +85
C temperature range.
1998 Burr-Brown Corporation
PDS-1463D
Printed in U.S.A. July, 1999
APPLICATIONS
q
DATA ACQUISITION
q
TEST AND MEASUREMENT
q
INDUSTRIAL PROCESS CONTROL
q
PERSONAL DIGITAL ASSISTANTS
q
BATTERY-POWERED SYSTEMS
CDAC
SAR
Comparator
Eight
Channel
Multiplexer
Serial
Interface
and
Control
CH4
CH5
CH6
CH7
COM
V
REF
CH0
CH1
CH2
CH3
CS
SHDN
DIN
DOUT
BUSY
DCLK
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
ADS7844
ADS
7844
2
ADS7844
SPECIFICATION: +5V
At T
A
= 40
C to +85
C, +V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 200kHz, and f
CLK
= 16 f
SAMPLE
= 3.2MHz, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
ADS7844E, N
ADS7844EB, NB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
Positive Input - Negative Input
0
V
REF
T
T
V
Absolute Input Range
Positive Input
0.2
+V
CC
+0.2
T
T
V
Negative Input
0.2
+1.25
T
T
V
Capacitance
25
T
pF
Leakage Current
1
T
A
SYSTEM PERFORMANCE
Resolution
12
T
Bits
No Missing Codes
12
T
Bits
Integral Linearity Error
2
1
LSB
(1)
Differential Linearity Error
0.8
0.5
1
LSB
Offset Error
3
T
LSB
Offset Error Match
0.15
1.0
T
T
LSB
Gain Error
4
3
LSB
Gain Error Match
0.1
1.0
T
T
LSB
Noise
30
T
Vrms
Power Supply Rejection
70
T
dB
SAMPLING DYNAMICS
Conversion Time
12
T
Clk Cycles
Acquisition Time
3
T
Clk Cycles
Throughput Rate
200
T
kHz
Multiplexer Settling Time
500
T
ns
Aperture Delay
30
T
ns
Aperture Jitter
100
T
ps
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
(2)
V
IN
= 5Vp-p at 10kHz
76
78
dB
Signal-to-(Noise + Distortion)
V
IN
= 5Vp-p at 10kHz
71
72
dB
Spurious Free Dynamic Range
V
IN
= 5Vp-p at 10kHz
76
78
dB
Channel-to-Channel Isolation
V
IN
= 5Vp-p at 50kHz
120
T
dB
REFERENCE INPUT
Range
0.1
+V
CC
T
T
V
Resistance
DCLK Static
5
T
G
Input Current
45
100
T
T
A
f
SAMPLE
= 12.5kHz
2.5
T
A
DCLK Static
0.001
3
T
T
A
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
T
Logic Levels
V
IH
| I
IH
|
+5
A
3.0
5.5
T
T
V
V
IL
| I
IL
|
+5
A
0.3
+0.8
T
T
V
V
OH
I
OH
= 250
A
3.5
T
V
V
OL
I
OL
= 250
A
0.4
T
V
Data Format
Straight Binary
T
POWER SUPPLY REQUIREMENTS
+V
CC
Specified Performance
4.75
5.25
T
T
V
Quiescent Current
550
900
T
A
f
SAMPLE
= 12.5kHz
300
T
A
Power-Down Mode
(3)
, CS = +V
CC
3
T
A
Power Dissipation
4.5
T
mW
TEMPERATURE RANGE
Specified Performance
40
+85
T
T
C
T
Same specifications as ADS7844E, ADS7844N.
NOTE: (1) LSB means Least Significant Bit. With V
REF
equal to +5.0V, one LSB is 1.22mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
3
ADS7844
SPECIFICATION: +2.7V
At T
A
= 40
C to +85
C, +V
CC
= +2.7V, V
REF
= +2.5V, f
SAMPLE
= 125kHz, and f
CLK
= 16 f
SAMPLE
= 2MHz, unless otherwise noted.
ADS7844E, N
ADS7844EB, NB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Input Span
Positive Input - Negative Input
0
V
REF
T
T
V
Absolute Input Range
Positive Input
0.2
+V
CC
+0.2
T
T
V
Negative Input
0.2
+0.2
T
T
V
Capacitance
25
T
pF
Leakage Current
1
T
A
SYSTEM PERFORMANCE
Resolution
12
T
Bits
No Missing Codes
12
T
Bits
Integral Linearity Error
2
1
LSB
(1)
Differential Linearity Error
0.8
0.5
1
LSB
Offset Error
3
T
LSB
Offset Error Match
0.15
1.0
T
T
LSB
Gain Error
4
3
LSB
Gain Error Match
0.1
1.0
T
T
LSB
Noise
30
T
Vrms
Power Supply Rejection
70
T
dB
SAMPLING DYNAMICS
Conversion Time
12
T
Clk Cycles
Acquisition Time
3
T
Clk Cycles
Throughput Rate
125
T
kHz
Multiplexer Settling Time
500
T
ns
Aperture Delay
30
T
ns
Aperture Jitter
100
T
ps
DYNAMIC CHARACTERISTICS
Total Harmonic Distortion
(2)
V
IN
= 2.5Vp-p at 10kHz
75
77
dB
Signal-to-(Noise + Distortion)
V
IN
= 2.5Vp-p at 10kHz
71
72
dB
Spurious Free Dynamic Range
V
IN
= 2.5Vp-p at 10kHz
78
80
dB
Channel-to-Channel Isolation
V
IN
= 2.5Vp-p at 50kHz
100
T
dB
REFERENCE INPUT
Range
0.1
+V
CC
T
T
V
Resistance
DCLK Static
5
T
G
Input Current
13
40
T
T
A
f
SAMPLE
= 12.5kHz
2.5
T
A
DCLK Static
0.001
3
T
T
A
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
T
Logic Levels
V
IH
| I
IH
|
+5
A
+V
CC
0.7
5.5
T
T
V
V
IL
| I
IL
|
+5
A
0.3
+0.8
T
T
V
V
OH
I
OH
= 250
A
+V
CC
0.8
T
V
V
OL
I
OL
= 250
A
0.4
T
V
Data Format
Straight Binary
T
POWER SUPPLY REQUIREMENTS
+V
CC
Specified Performance
2.7
3.6
T
T
V
Quiescent Current
280
650
T
T
A
f
SAMPLE
= 12.5kHz
220
T
A
Power-Down Mode
(3)
, CS = +V
CC
3
T
A
Power Dissipation
1.8
T
mW
TEMPERATURE RANGE
Specified Performance
40
+85
T
T
C
T
Same specifications as ADS7844E, ADS7844N.
NOTE: (1) LSB means Least Significant Bit. With V
REF
equal to +2.5V, one LSB is 610mV. (2) First five harmonics of the test frequency. (3) Auto power-down mode
(PD1 = PD0 = 0) active or SHDN = GND.
4
ADS7844
PIN CONFIGURATION
Top View
PIN DESCRIPTIONS
PIN
NAME
DESCRIPTION
1
CH0
Analog Input Channel 0.
2
CH1
Analog Input Channel 1.
3
CH2
Analog Input Channel 2.
4
CH3
Analog Input Channel 3.
5
CH4
Analog Input Channel 4.
6
CH5
Analog Input Channel 5.
7
CH6
Analog Input Channel 6.
8
CH7
Analog Input Channel 7.
9
COM
Ground reference for analog inputs. Sets zero code
voltage in single ended mode. Connect this pin to ground
or ground reference point.
10
SHDN
Shutdown. When LOW, the device enters a very low
power shutdown mode.
11
V
REF
Voltage Reference Input. See Specification Table for
ranges.
12
+V
CC
Power Supply, 2.7V to 5V.
13
GND
Ground
14
GND
Ground
15
D
OUT
Serial Data Output. Data is shifted on the falling edge of
D
CLK
. This output is high impedance when
CS is high.
16
BUSY
Busy Output. Busy goes low when the DIN control bits
are being read and also when the device is converting.
The Output is high impedance when CS is High.
17
D
IN
Serial Data Input. If CS is LOW, data is latched on rising
edge of D
CLK
.
18
CS
Chip Select Input. Active LOW. Data will not be clocked
into D
IN
unless CS is low. When CS is high D
OUT
is high
impedance.
19
CLK
External Clock Input. The clock speed determines the
conversion rate by the equation f
CLK
= 16 f
SAMPLE
.
20
+V
CC
Power Supply
1
2
3
4
5
6
7
8
9
10
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
+V
CC
D
CLK
CS
D
IN
BUSY
D
OUT
GND
GND
+V
CC
V
REF
20
19
18
17
16
15
14
13
12
11
ADS7844
MINIMUM
RELATIVE
MAXIMUM
SPECIFICATION
PACKAGE
ACCURACY
GAIN ERROR
TEMPERATURE
DRAWING
ORDERING
TRANSPORT
PRODUCT
(LSB)
(LSB)
RANGE
PACKAGE
NUMBER
(1)
NUMBER
(2)
MEDIA
ADS7844E
2
4
40
C to +85
C
20-Lead QSOP
349
ADS7844E
Rails
"
"
"
"
"
"
ADS7844E/2K5
Tape and Reel
ADS7844N
"
"
"
20-Lead SSOP
334
ADS7844N
Rails
"
"
"
"
"
"
ADS7844N/1K
Tape and Reel
ADS7844EB
1
3
40
C to +85
C
20-Lead QSOP
349
ADS7844EB
Rails
"
"
"
"
"
"
ADS7844EB/2K5
Tape and Reel
ADS7844NB
"
"
"
20-Lead SSOP
334
ADS7844NB
Rails
"
"
"
"
"
"
ADS7844NB/1K
Tape and Reel
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of "ADS7844/2K5" will get a single
2500-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
PACKAGE/ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
(1)
+V
CC
to GND ........................................................................ 0.3V to +6V
Analog Inputs to GND ............................................ 0.3V to +V
CC
+ 0.3V
Digital Inputs to GND ........................................................... 0.3V to +6V
Power Dissipation .......................................................................... 250mW
Maximum Junction Temperature ................................................... +150
C
Operating Temperature Range ........................................ 40
C to +85
C
Storage Temperature Range ......................................... 65
C to +150
C
Lead Temperature (soldering, 10s) ............................................... +300
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and
installation procedures can cause damage.
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be
more susceptible to damage because very small parametric
changes could cause the device not to meet its published specifi-
cations.
5
ADS7844
TYPICAL PERFORMANCE CURVES:+5V
At T
A
= +25
C, +V
CC
= +5V, V
REF
= +5V, f
SAMPLE
= 200kHz, and f
CLK
= 16 f
SAMPLE
= 3.2MHz, unless otherwise noted.
0
20
40
60
80
100
120
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1,123Hz, 0.2dB)
0
100
25
75
50
Frequency (kHz)
Amplitude (dB)
0
20
40
60
80
100
120
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10.3kHz, 0.2dB)
0
100
25
75
50
Frequency (kHz)
Amplitude (dB)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
10
1
100
Input Frequency (kHz)
SNR and SINAD (dB)
74
73
72
71
70
69
68
SINAD
SNR
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
10
1
100
Input Frequency (kHz)
SFDR (dB)
THD (dB)
85
80
75
70
65
85
80
75
70
65
THD
SFDR
12.0
11.8
11.6
11.4
11.2
11.0
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
10
1
100
Input Frequency (kHz)
Effective Number of Bits
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
20
40
100
Temperature (C)
Delta from +25C (dB)
0.4
0.2
0.0
0.2
0.4
0.6
0.6
0
20
40
60
80
f
IN
= 10kHz, 0.2dB
6
ADS7844
0
20
40
60
80
100
120
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 1,129Hz, 0.2dB)
0
62.5
15.6
46.9
31.3
Frequency (kHz)
Amplitude (dB)
0
20
40
60
80
100
120
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 10.6kHz, 0.2dB)
0
62.5
15.6
46.9
31.3
Frequency (kHz)
Amplitude (dB)
SIGNAL-TO-NOISE RATIO AND SIGNAL-TO-
(NOISE+DISTORTION) vs INPUT FREQUENCY
10
1
100
Input Frequency (kHz)
SNR and SINAD (dB)
78
74
70
66
62
58
54
SINAD
SNR
THD
SFDR
SPURIOUS FREE DYNAMIC RANGE AND TOTAL
HARMONIC DISTORTION vs INPUT FREQUENCY
10
1
100
Input Frequency (kHz)
SFDR (dB)
THD (dB)
90
85
80
75
70
65
60
55
50
90
85
80
75
70
65
60
55
50
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
10
1
100
Input Frequency (kHz)
Effective Number of Bits
12.0
11.5
11.0
10.5
10.0
9.5
9.0
TYPICAL PERFORMANCE CURVES:+2.7V
At T
A
= +25
C, +V
CC
= +2.7V, V
REF
= +2.5V, f
SAMPLE
= 125kHz, and f
CLK
= 16 f
SAMPLE
= 2MHz, unless otherwise noted.
CHANGE IN SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
20
40
100
Temperature (C)
Delta from +25C (dB)
0.2
0.0
0.2
0.4
0.6
0.8
0.4
0
20
40
60
80
f
IN
= 10kHz, 0.2dB
7
ADS7844
SUPPLY CURRENT vs TEMPERATURE
20
40
100
20
0
40
Temperature (C)
Supply Current (
A)
400
350
300
250
200
150
100
60
80
POWER DOWN SUPPLY CURRENT
vs TEMPERATURE
20
40
100
20
0
40
Temperature (C)
Supply Current (nA)
140
120
100
80
60
40
20
60
80
Output Code
1.00
0.75
0.50
0.25
0.00
0.25
0.50
0.75
1.00
INTEGRAL LINEARITY ERROR vs CODE
800
H
FFF
H
000
H
ILE (LSB)
Output Code
1.00
0.75
0.50
0.25
0.00
0.25
0.50
0.75
1.00
DIFFERENTIAL LINEARITY ERROR vs CODE
800
H
FFF
H
000
H
DLE (LSB)
CHANGE IN GAIN vs TEMPERATURE
20
40
100
20
0
40
Temperature (C)
Delta from +25C (LSB)
0.15
0.10
0.05
0.00
0.05
0.10
0.15
60
80
CHANGE IN OFFSET vs TEMPERATURE
20
40
100
20
0
40
Temperature (C)
Delta from +25C (LSB)
0.6
0.4
0.2
0.0
0.2
0.4
0.6
60
80
TYPICAL PERFORMANCE CURVES:+2.7V
(CONT)
At T
A
= +25
C, +V
CC
= +2.7V, V
REF
= +2.5V, f
SAMPLE
= 125kHz, and f
CLK
= 16 f
SAMPLE
= 2MHz, unless otherwise noted.
8
ADS7844
REFERENCE CURRENT vs SAMPLE RATE
75
0
125
25
50
100
Sample Rate (kHz)
Reference Current (
A)
14
12
10
8
6
4
2
0
REFERENCE CURRENT vs TEMPERATURE
20
40
100
20
0
40
Temperature (C)
Reference Current (
A)
18
16
14
12
10
8
6
60
80
SUPPLY CURRENT vs +V
CC
3.5
2
5
2.5
4
+V
CC
(V)
Supply Current (
A)
320
300
280
260
240
220
200
180
4.5
3
f
SAMPLE
= 12.5kHz
V
REF
= +V
CC
MAXIMUM SAMPLE RATE vs +V
CC
3.5
2
5
2.5
4
+V
CC
(V)
Sample Rate (Hz)
1M
100k
10k
1k
4.5
3
V
REF
= +V
CC
TYPICAL PERFORMANCE CURVES
(CONT)
At T
A
= +25
C, +V
CC
= +2.7V, V
REF
= +2.5V, f
SAMPLE
= 125kHz, and f
CLK
= 16 f
SAMPLE
= 2MHz, unless otherwise noted.
9
ADS7844
THEORY OF OPERATION
The ADS7844 is a classic successive approximation register
(SAR) analog-to-digital (A/D) converter. The architecture is
based on capacitive redistribution which inherently includes
a sample/hold function. The converter is fabricated on a
0.6
s CMOS process.
The basic operation of the ADS7844 is shown in Figure 1.
The device requires an external reference and an external
clock. It operates from a single supply of 2.7V to 5.25V. The
external reference can be any voltage between 100mV and
+V
CC
. The value of the reference voltage directly sets the
input range of the converter. The average reference input
current depends on the conversion rate of the ADS7844.
The analog input to the converter is differential and is
provided via an eight-channel multiplexer. The input can be
provided in reference to a voltage on the COM pin (which
is generally ground) or differentially by using four of the
eight input channels (CH0 - CH7). The particular configura-
tion is selectable via the digital interface.
A2
A1
A0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
0
0
0
+IN
IN
0
0
1
+IN
IN
0
1
0
+IN
IN
0
1
1
+IN
IN
1
0
0
IN
+IN
1
0
1
IN
+IN
1
1
0
IN
+IN
1
1
1
IN
+IN
TABLE II. Differential Channel Control (SGL/DIF LOW).
TABLE I. Single-Ended Channel Selection (SGL/DIF HIGH).
FIGURE 1. Basic Operation of the ADS7844.
A2
A1
A0
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
0
0
0
+IN
IN
1
0
0
+IN
IN
0
0
1
+IN
IN
1
0
1
+IN
IN
0
1
0
+IN
IN
1
1
0
+IN
IN
0
1
1
+IN
IN
1
1
1
+IN
IN
ANALOG INPUT
Figure 2 shows a block diagram of the input multiplexer on
the ADS7844. The differential input of the converter is
derived from one of the eight inputs in reference to the COM
pin or four of the eight inputs. Table I and Table II show the
relationship between the A2, A1, A0, and SGL/DIF control
bits and the configuration of the analog multiplexer. The
control bits are provided serially via the DIN pin, see the
Digital Interface section of this data sheet for more details.
When the converter enters the hold mode, the voltage
difference between the +IN and IN inputs (see Figure 2) is
captured on the internal capacitor array. The voltage on the
IN input is limited between 0.2V and 1.25V, allowing the
input to reject small signals which are common to both the
+IN and IN input. The +IN input has a range of 0.2V to
+V
CC
+ 0.2V.
The input current on the analog inputs depends on the
conversion rate of the device. During the sample period, the
source must charge the internal sampling capacitor (typi-
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
SHDN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
+V
CC
D
CLK
CS
D
IN
BUSY
D
OUT
GND
GND
+V
CC
V
REF
Serial/Conversion Clock
Chip Select
Serial Data In
Serial Data Out
+2.7V to +5V
1
F to 10
F
ADS7844
Single-ended
or differential
analog inputs
1
F to 10
F
0.1
F
10
ADS7844
cally 25pF). After the capacitor has been fully charged, there
is no further input current. The rate of charge transfer from
the analog source to the converter is a function of conversion
rate.
REFERENCE INPUT
The external reference sets the analog input range. The
ADS7844 will operate with a reference in the range of
100mV to +V
CC
. Keep in mind that the analog input is the
difference between the +IN input and the IN input as shown
in Figure 2. For example, in the single-ended mode, a 1.25V
reference, and with the COM pin grounded, the selected input
channel (CH0 - CH7) will properly digitize a signal in the
range of 0V to 1.25V. If the COM pin is connected to 0.5V,
the input range on the selected channel is 0.5V to 1.75V.
There are several critical items concerning the reference input
and its wide voltage range. As the reference voltage is re-
duced, the analog voltage weight of each digital output code
is also reduced. This is often referred to as the LSB (least
significant bit) size and is equal to the reference voltage
divided by 4096. Any offset or gain error inherent in the A/D
converter will appear to increase, in terms of LSB size, as the
reference voltage is reduced. For example, if the offset of a
given converter is 2 LSBs with a 2.5V reference, then it will
typically be 10 LSBs with a 0.5V reference. In each case, the
actual offset of the device is the same, 1.22mV.
Likewise, the noise or uncertainty of the digitized output will
increase with lower LSB size. With a reference voltage of
100mV, the LSB size is 24
V. This level is below the
internal noise of the device. As a result, the digital output
code will not be stable and vary around a mean value by a
number of LSBs. The distribution of output codes will be
gaussian and the noise can be reduced by simply averaging
consecutive conversion results or applying a digital filter.
With a lower reference voltage, care should be taken to
provide a clean layout including adequate bypassing, a clean
(low noise, low ripple) power supply, a low-noise reference,
and a low-noise input signal. Because the LSB size is lower,
the converter will also be more sensitive to nearby digital
signals and electromagnetic interference.
The voltage into the V
REF
input is not buffered and directly
drives the capacitor digital-to-analog converter (CDAC)
portion of the ADS7844. Typically, the input current is
13
A with a 2.5V reference. This value will vary by
microamps depending on the result of the conversion. The
reference current diminishes directly with both conversion
rate and reference voltage. As the current from the reference
is drawn on each bit decision, clocking the converter more
quickly during a given conversion period will not reduce
overall current drain from the reference.
DIGITAL INTERFACE
Figure 3 shows the typical operation of the ADS7844's
digital interface. This diagram assumes that the source of the
digital signals is a microcontroller or digital signal processor
with a basic serial interface (note that the digital inputs are
over-voltage tolerant up to 5.5V, regardless of +V
CC
). Each
communication between the processor and the converter
consists of eight clock cycles. One complete conversion can
be accomplished with three serial communications, for a
total of 24 clock cycles on the DCLK input.
The first eight clock cycles are used to provide the control
byte via the DIN pin. When the converter has enough
information about the following conversion to set the input
multiplexer appropriately, it enters the acquisition (sample)
mode. After three more clock cycles, the control byte is
complete and the converter enters the conversion mode. At
this point, the input sample/hold goes into the hold mode.
The next twelve clock cycles accomplish the actual analog-
to-digital conversion. A thirteenth clock cycle is needed for
the last bit of the conversion result. Three more clock cycles
are needed to complete the last byte (DOUT will be LOW).
These will be ignored by the converter.
Control Byte
Also shown in Figure 3 is the placement and order of the
control bits within the control byte. Tables III and IV give
detailed information about these bits. The first bit, the `S' bit,
must always be HIGH and indicates the start of the control
byte. The ADS7844 will ignore inputs on the DIN pin until
the start bit is detected. The next three bits (A2 - A0) select
the active input channel or channels of the input multiplexer
(see Tables I and II and Figure 2).
FIGURE 2. Simplified Diagram of the Analog Input.
Converter
+IN
IN
CH0
CH1
CH2
CH3
A2-A0
(shown 00o
B
)
(1)
SGL/DIF
(shown HIGH)
CH4
CH5
CH6
CH7
COM
NOTE: (1) See Truth Tables,
Table 1 & Table 2 for address coding.
11
ADS7844
FIGURE 3. Conversion Timing, 24-Clocks per Conversion, 8-Bit Bus Interface. No DCLK delay required with dedicated
serial port.
1
DCLK
CS
8
1
11
DOUT
BUSY
S
DIN
CONTROL BITS
S
CONTROL BITS
10
9
8
7
6
5
4
3
2
1
0
11 10
9
8
1
1
8
FIGURE 4. Conversion Timing, 16-Clocks per Conversion, 8-bit Bus Interface. No DCLK delay required with dedicated
serial port.
Bit 7
Bit 0
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
S
A2
A1
A0
--
SGL/DIF
PD1
PD0
TABLE III. Order of the Control Bits in the Control Byte.
TABLE IV. Descriptions of the Control Bits within the
Control Byte.
BIT
NAME
DESCRIPTION
7
S
Start Bit. Control byte starts with first HIGH bit on
DIN. A new control byte starts with every 15th clock
cycle.
6 - 4
A2 - A0
Channel Select Bits. Along with the SGL/DIF bit,
these bits control the setting of the multiplexer input
as detailed in Tables I and II.
3
--
Not Used.
2
SGL/DIF
Single-Ended/Differential Select Bit. Along with bits
A2 - A0, this bit controls the setting of the multiplexer
input as detailed in Tables I and II.
1 - 0
PD1 - PD0
Power-Down Mode Select Bits. See Table V for
details.
The SGL/DIF bit controls the multiplexer input mode: either
single-ended (HIGH) or differential (LOW). In single-ended
mode, the selected input channel is referenced to the COM
pin. In differential mode, the two selected inputs provide a
differential input. See Tables I and II and Figure 2 for more
information. The last two bits (PD1 - PD0) select the power-
down mode as shown in Table V. If both inputs are HIGH,
the device is always powered up. If both inputs are LOW, the
device enters a power-down mode between conversions.
When a new conversion is initiated, the device will resume
normal operation instantly--no delay is needed to allow the
device to power up and the very first conversion will be
valid.
16-Clocks per Conversion
The control bits for conversion n+1 can be overlapped with
conversion `n' to allow for a conversion every 16 clock
cycles, as shown in Figure 4. This figure also shows possible
serial communication occurring with other serial peripherals
between each byte transfer between the processor and the
converter. This is possible provided that each conversion
completes within 1.6ms of starting. Otherwise, the signal
that has been captured on the input sample/hold may droop
enough to affect the conversion result. In addition, the
ADS7844 is fully powered while other serial communica-
tions are taking place.
t
ACQ
Acquire
Idle
Conversion
Idle
1
DCLK
CS
8
1
11
DOUT
BUSY
(MSB)
(START)
(LSB)
A2
S
DIN
A1
A0
SGL/
DIF
PD1 PD0
10
9
8
7
6
5
4
3
2
1
0
Zero Filled...
8
1
8
12
ADS7844
Digital Timing
Figure 5 and Tables VI and VII provide detailed timing for
the digital interface of the ADS7844.
15-Clocks per Conversion
Figure 6 provides the fastest way to clock the ADS7844.
This method will not work with the serial interface of most
microcontrollers and digital signal processors as they are
generally not capable of providing 15 clock cycles per serial
transfer. However, this method could be used with field
programmable gate arrays (FPGAs) or application specific
integrated circuits (ASICs). Note that this effectively in-
creases the maximum conversion rate of the converter be-
yond the values given in the specification tables, which
assume 16 clock cycles per conversion.
PD1
PD0
Description
0
0
Power-down between conversions. When each
conversion is finished, the converter enters a low
power mode. At the start of the next conversion,
the device instantly powers up to full power. There
is no need for additional delays to assure full
operation and the very first conversion is valid.
0
1
Reserved for future use.
1
0
Reserved for future use.
1
1
No power-down between conversions, device al-
ways powered.
TABLE V. Power-Down Selection.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ACQ
Acquisition Time
1.5
s
t
DS
DIN Valid Prior to DCLK Rising
100
ns
t
DH
DIN Hold After DCLK HIGH
10
ns
t
DO
DCLK Falling to DOUT Valid
200
ns
t
DV
CS Falling to DOUT Enabled
200
ns
t
TR
CS Rising to DOUT Disabled
200
ns
t
CSS
CS Falling to First DCLK Rising
100
ns
t
CSH
CS Rising to DCLK Ignored
0
ns
t
CH
DCLK HIGH
200
ns
t
CL
DCLK LOW
200
ns
t
BD
DCLK Falling to BUSY Rising
200
ns
t
BDV
CS Falling to BUSY Enabled
200
ns
t
BTR
CS Rising to BUSY Disabled
200
ns
TABLE VI. Timing Specifications (+V
CC
= +2.7V to 3.6V,
T
A
= 40
C to +85
C, C
LOAD
= 50pF).
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
ACQ
Acquisition Time
900
ns
t
DS
DIN Valid Prior to DCLK Rising
50
ns
t
DH
DIN Hold After DCLK HIGH
10
ns
t
DO
DCLK Falling to DOUT Valid
100
ns
t
DV
CS Falling to DOUT Enabled
70
ns
t
TR
CS Rising to DOUT Disabled
70
ns
t
CSS
CS Falling to First DCLK Rising
50
ns
t
CSH
CS Rising to DCLK Ignored
0
ns
t
CH
DCLK HIGH
150
ns
t
CL
DCLK LOW
150
ns
t
BD
DCLK Falling to BUSY Rising
100
ns
t
BDV
CS Falling to BUSY Enabled
70
ns
t
BTR
CS Rising to BUSY Disabled
70
ns
TABLE VII. Timing Specifications (+V
CC
= +4.75V to
+5.25V, T
A
= 40
C to +85
C, C
LOAD
= 50pF).
FIGURE 6. Maximum Conversion Rate, 15-Clocks per Conversion.
FIGURE 5. Detailed Timing Diagram.
PD0
t
BDV
t
DH
t
CH
t
CL
t
DS
t
CSS
t
DV
t
BD
t
BD
t
TR
t
BTR
t
D0
t
CSH
DCLK
CS
11
DOUT
BUSY
DIN
10
1
DCLK
CS
11
DOUT
BUSY
A2
S
DIN
A1 A0
SGL/
DIF PD1 PD0
10
9
8
7
6
5
4
3
2
1
0
11
10
9
8
7
6
5
4
3
2
A1 A0
15
1
15
1
A2
S
A1 A0
SGL/
DIF PD1 PD0
A2
S
13
ADS7844
Data Format
The ADS7844 output data is in straight binary format as
shown in Figure 7. This figure shows the ideal output code
for the given input voltage and does not include the effects
of offset, gain, or noise.
Output Code
0V
FS = Full-Scale Voltage = V
REF
1 LSB = V
REF
/4096
FS 1 LSB
11...111
11...110
11...101
00...010
00...001
00...000
1 LSB
Note 1: Voltage at converter input, after
multiplexer: +IN(IN). See Figure 2.
Input Voltage
(1)
(V)
FIGURE 7. Ideal Input Voltages and Output Codes.
POWER DISSIPATION
There are three power modes for the ADS7844: full power
(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),
and shutdown (SHDN LOW). The affects of these modes
varies depending on how the ADS7844 is being operated. For
example, at full conversion rate and 16 clocks per conver-
sion, there is very little difference between full power mode
and auto power-down. Likewise, if the device has entered
auto power-down, a shutdown (SHDN LOW) will not lower
power dissipation.
When operating at full-speed and 16-clocks per conversion
(as shown in Figure 4), the ADS7844 spends most of its time
acquiring or converting. There is little time for auto power-
down, assuming that this mode is active. Thus, the differ-
ence between full power mode and auto power-down is
negligible. If the conversion rate is decreased by simply
slowing the frequency of the DCLK input, the two modes
remain approximately equal. However, if the DCLK fre-
quency is kept at the maximum rate during a conversion, but
conversion are simply done less often, then the difference
between the two modes is dramatic. Figure 8 shows the
difference between reducing the DCLK frequency ("scal-
ing" DCLK to match the conversion rate) or maintaining
DCLK at the highest frequency and reducing the number of
conversion per second. In the later case, the converter
spends an increasing percentage of its time in power-down
mode (assuming the auto power-down mode is active).
If DCLK is active and CS is LOW while the ADS7844 is in
auto power-down mode, the device will continue to dissipate
some power in the digital logic. The power can be reduced
to a minimum by keeping CS HIGH. The differences in
supply current for these two cases are shown in Figure 9.
FIGURE 8. Supply Current vs Directly Scaling the Fre-
quency of DCLK with Sample Rate or Keeping
DCLK at the Maximum Possible Frequency.
10k
100k
1k
1M
f
SAMPLE
(Hz)
Supply Current (A)
100
10
1
1000
f
CLK
= 2MHz
f
CLK
= 16 f
SAMPLE
T
A
= 25C
+V
CC
= +2.7V
V
REF
= +2.5V
PD1 = PD0 = 0
FIGURE 9. Supply Current vs State of CS.
10k
100k
1k
1M
f
SAMPLE
(Hz)
Supply Current (A)
0.00
0.09
14
0
2
4
6
8
10
12
CS LOW
(GND)
CS HIGH (+V
CC
)
T
A
= 25C
+V
CC
= +2.7V
V
REF
= +2.5V
f
CLK
= 16 f
SAMPLE
PD1 = PD0 = 0
Operating the ADS7844 in auto power-down mode will
result in the lowest power dissipation, and there is no
conversion time "penalty" on power-up. The very first
conversion will be valid. SHDN can be used to force an
immediate power-down.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7844 circuitry. This is particu-
larly true if the reference voltage is low and/or the conver-
sion rate is high.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n "win-
dows" in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
14
ADS7844
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the DCLK
input.
With this in mind, power to the ADS7844 should be clean
and well bypassed. A 0.1
F ceramic bypass capacitor should
be placed as close to the device as possible. In addition, a
1
F to 10
F capacitor and a 5
or 10
series resistor may
be used to lowpass filter a noisy supply.
The reference should be similarly bypassed with a 0.1
F
capacitor. Again, a series resistor and large capacitor can be
used to lowpass filter the reference voltage. If the reference
voltage originates from an op amp, make sure that it can
drive the bypass capacitor without oscillation (the series
resistor can help in this case). The ADS7844 draws very
little current from the reference on average, but it does place
larger demands on the reference circuitry over short periods
of time (on each rising edge of DCLK during a conversion).
The ADS7844 architecture offers no inherent rejection of
noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied
to the power supply. Any noise and ripple from the supply
will appear directly in the digital results. While high fre-
quency noise can be filtered out as discussed in the previous
paragraph, voltage variation due to line frequency (50Hz or
60Hz) can be difficult to remove.
The GND pin should be connected to a clean ground point.
In many cases, this will be the "analog" ground. Avoid
connections which are too near the grounding point of a
microcontroller or digital signal processor. If needed, run a
ground trace directly from the converter to the power supply
entry point. The ideal layout will include an analog ground
plane dedicated to the converter and associated analog
circuitry.
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