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Электронный компонент: ADS7891

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ADS7891
SLAS410 - DECEMBER 2003
14 BIT, 3 MSPS
LOW POWER SAR ANALOG TO DIGITAL CONVERTER
FEATURES
D
3 MHz Sample Rate, 14-Bit Resolution
D
Zero Latency
D
Unipolar, Pseudo Differential Input, Range:
- 0 V to 2.5 V
D
High Speed Parallel Interface
D
78 dB SNR and 88.5 dB THD at 3 MSPS
D
Power Dissipation 85 mW at 3 MSPS
D
Nap Mode (10 mW Power Dissipation)
D
Power Down (10
m
W)
D
Internal Reference
D
Internal Reference Buffer
D
8-/14-Bit Bus Transfer
D
48-Pin TQFP Package
APPLICATIONS
D
Optical Networking (DWDM, MEMS Based
Switching)
D
Spectrum Analyzers
D
High Speed Data Acquisition Systems
D
High Speed Close-Loop Systems
D
Telecommunication
D
Ultra-Sound Detection
DESCRIPTION
The ADS7891 is a 14-bit 3-MSPS A-to-D converter with 2.5-V internal reference. The device includes a
capacitor based SAR A/D converter with inherent sample and hold. The device offers a 14-bit parallel interface
with an additional byte mode that provides easy interface with 8-bit processors. The device has a
pseudo-differential input stage.
The -IN swing of
200 mV is useful to compensate for ground voltage mismatch between the ADC and sensor
and also to cancel common-mode noise. With nap mode enabled, the device operates at lower power when
used at lower conversion rates. The device is available in a 48-pin TQFP package.
_
+
SAR
Output
Latches
and
3-State
Drivers
BYTE
14/8-Bit Parallel
Data Output Bus
Conversion
and
Control Logic
CONVST
BUSY
CS
RD
A_PWD
PWD/RST
CDAC
Comparator
CLOCK
2.5 V
Internal
Reference
+IN
-IN
REFIN
REFOUT
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
2003, Texas Instruments Incorporated
ADS7891
SLAS410 - DECEMBER 2003
www.ti.com
2
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate
precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to
damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
MODEL
MAXIMUM
INTEGRAL
LINEARITY
(LSB)
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
NO MISSING
CODES AT
RESOLUTION
(BIT)
PACKAGE
TYPE
PACKAGE
DESIGNATOR
TEMPERATURE
RANGE
ORDERING
INFORMATION
TRANSPORT
MEDIA QUANTITY
ADS7891
1.5
+1.5/-1
14
48-Pin
PFB
-40
C to 85
C
ADS7891IPFBT
Tape and reel
250
ADS7891
1.5
+1.5/-1
14
48-Pin
TQFP
PFB
-40
C to 85
C
ADS7891IPFBR
Tape and reel
1000
NOTE: For most current specifications and package information, refer to the TI website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range(1)
UNIT
+IN to AGND
-0.3 V to +VA + 0.1 V
-IN to AGND
-0.3 V to 0.5 V
+VA to AGND
-0.3 V to 7 V
+VBD to BDGND
-0.3 V to 7 V
Digital input voltage to GND
-0.3 V to (+VBD + 0.3 V)
Digital output to GND
-0.3 V to (+VBD + 0.3 V)
Operating temperature range
-40
C to 85
C
Storage temperature range
-65
C to 150
C
Junction temperature (TJmax)
150
C
TQFP package
Power dissipation
(TJ MaxTA)/
JA
TQFP package
JA Thermal impedance
86
C/W
Lead temperature, soldering
Vapor phase (60 sec)
215
C
Lead temperature, soldering
Infrared (15 sec)
220
C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
ADS7891
SLAS410 - DECEMBER 2003
www.ti.com
3
SPECIFICATIONS
TA = -40
C to 85
C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 3 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUT
Full-scale input span(1)
+IN (-IN)
0
Vref
V
Absolute input range
+IN
-0.2
Vref + 0.2
V
Absolute input range
-IN
-0.2
+0.2
V
Input capacitance
27
pF
Input leakage current
500
pA
SYSTEM PERFORMANCE
Resolution
14
Bits
No missing codes
14
Bits
Integral linearity(2)
-1.5
0.75
1.5
LSB(3)
Differential linearity
-1
0.75
1.5
LSB(3)
Offset error(4)
External reference
-1.5
0.2
1.5
mV
Gain error(4)
External reference
-1
0.2
1
mV
Common-mode rejection ratio
With common mode input signal = 200
mVp-p at 1 MHz
60
dB
Power supply rejection
At 3FF0H output code,
+VA = 4.75 V to 5.25 V , Vref = 2.50 V
80
dB
SAMPLING DYNAMICS
Conversion time
+VDB = 5 V
255
273
nsec
Conversion time
+VDB = 3 V
273
nsec
Acquisition time
+VDB = 5 V
60
78
nsec
Acquisition time
+VDB = 3 V
60
nsec
Maximum throughput rate
3
MHz
Aperture delay
2
nsec
Aperture jitter
20
psec
Step response
50
nsec
Over voltage recovery
50
nsec
DYNAMIC CHARACTERISTICS
(5)
VIN = 2.496 Vp-p at 100 kHz/2.5 Vref
-93
Total harmonic distortion(5)
VIN = 2.496 Vp-p at 1 MHz/2.5 Vref
-88.5
-87
dB
Total harmonic distortion(5)
VIN = 2.496 Vp-p at 1.4 MHz/2.5 Vref
-79.5
dB
VIN = 2.496 Vp-p at 100 kHz/2.5 Vref
78.5
SNR
VIN = 2.496 Vp-p at 1 MHz/2.5 Vref
78
dB
SNR
VIN = 2.496 Vp-p at 1.4 MHz/2.5 Vref
75
dB
VIN = 2.496 Vp-p at 100 kHz/2.5 Vref
78
SINAD
VIN = 2.496 Vp-p at 1 MHz/2.5 Vref
77
dB
SINAD
VIN = 2.496 Vp-p at 1.4 MHz/2.5 Vref
73.8
dB
SFDR
VIN = 2.496 Vp-p at 1 MHz/2.5 Vref
88
90
dB
-3 dB Small signal bandwidth
50
MHz
EXTERNAL REFERENCE INPUT
Input VREF range
2.4
2.5
2.6
V
Resistance(6)
500
k
(1) Ideal input span; does not include gain or offset error.
(2) This is endpoint INL, not best fit.
(3) LSB means least significant bit.
(4) Measured relative to actual measured reference.
(5) Calculated on the first nine harmonics of the input frequency.
(6) Can vary
20%.
ADS7891
SLAS410 - DECEMBER 2003
www.ti.com
4
SPECIFICATIONS Continued
TA = -40
C to 85
C, +VA = 5 V, +VBD = 5 V or 3.3 V, Vref = 2.5 V, fsample = 3 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL REFERENCE OUTPUT
Start-up time
From 95% (+VA), with 1-
F storage
capacitor on REFOUT to AGND
120
msec
VREF Range
IOUT=0
2.48
2.5
2.52
V
Source current
Static load
10
A
Line regulation
+VA = 4.75 V to 5.25 V
1
mV
Drift
IOUT = 0
25
PPM/C
DIGITAL INPUT/OUTPUT
Logic family
CMOS
VIH
IIH = 5
A
+VBD -1
+VBD + 0.3
V
Logic level
VIL
IIL = 5
A
-0.3
0.8
V
Logic level
VOH
IOH = 2 TTL loads
+VBD - 0.6
+VBD
V
VOL
IOL = 2 TTL loads
0
0.4
V
Data format
Straight
Binary
POWER SUPPLY REQUIREMENTS
Power supply voltage
+VBD
2.7
3.3
5.25
V
Power supply voltage
+VA
4.75
5
5.25
V
Supply current, +VA, 3 MHz sample rate
17
18
mA
Power dissipation, 3 MHz sample rate
+VA = 5 V
85
90
mW
NAP MODE
Supply current, +VA
2
3
mA
Power-up time(1)
60
nsec
POWER DOWN
Supply current, +VA
2
2.5
A
Power down time(2)
From simulation results
10
sec
Power up time
1-
F Storage capacitor on REFOUT to
AGND
25
msec
Invalid conversions after power up or reset
4
Numbers
TEMPERATURE RANGE
Operating free-air
-40
85
C
(1) Minimum acquisition time for first sampling after the end of nap state must be 60 nsec more than normal.
(2) Time required to reach level of 2.5
A.
ADS7891
SLAS410 - DECEMBER 2003
www.ti.com
5
TIMING REQUIREMENTS
All specifications typical at -40
C to 85
C, +VA = +5 V, +VBD = +5 V (see Notes 1, 2, 3, and 4)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
REF FIG.
Conversion time
t(conv)
255
273
ns
5
Acquisition time
t(acq)
60
78
ns
5
SAMPLING AND CONVERSION START
Hold time CS low to CONVST high (with BUSY high)
th1
10
ns
3
Delay CONVST high to acquisition start
td1
2
4
5
ns
1
Hold time, CONVST high to CS high with BUSY low
th2
10
ns
1
Hold time, CONVST low to CS high
th3
10
ns
1
Delay CONVST low to BUSY high
td2
40
ns
1
CS width for acquisition or conversion to start
tw3
20
ns
2
Delay CS low to acquisition start with CONVST high
td3
2
4
5
ns
2
Pulse width, from CS low to CONVST low for acquisition to start
tw1
20
ns
2
Delay CS low to BUSY high with CONVST low
td4
40
ns
2
Quiet sampling time(3)
25
ns
CONVERSION ABORT
Setup time CONVST high to CS low with BUSY high
tsu1
15
ns
4
Delay time CS low to BUSY low with CONVST high
td5
20
ns
4
DATA READ
Delay RD low to data valid with CS low
td6
25
ns
5
Delay BYTE high to LSB word valid with CS and RD low
td7
25
ns
5
Delay time RD high to data 3-state with CS low
td9
25
ns
5
Delay time end of conversion to BUSY low
td11
20
ns
5
Quiet sampling time RD high to CONVST low
t1
25
ns
5
Delay CS low to data valid with RD low
td8
25
ns
6
Delay CS high to data 3-state with RD low
td10
25
ns
6
Quiet sampling time CS low to CONVST low
t2
25
ns
6
BACK-TO-BACK CONVERSION
Delay BUSY low to data valid
td12
10
ns
7, 8
Pulse width, CONVST high
tw4
70
ns
7, 8
Pulse width, CONVST low
tw5
20
ns
7
POWER DOWN/RESET
Pulse width, low for PWD/RST to reset the device
tw6
45
6140
ns
12
Pulse width, low for PWD/RST to power down the device
tw7
7200
ns
11
Delay time, power up after PWD/RST is high
td13
25
ms
11
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagram.
(3) Quiet period before conversion start, no data bus activity including data bus 3-state is allowed in this period.
(4) All timings are measured with 20 pF equivalent loads with 5 V +VBD and 10-pF equivalent loads with 3 V +VBD on all data bits and BUSY pin.