1995 Burr-Brown Corporation

PDS-1290E

Printed in U.S.A. October, 1996

ADS802

FEATURES

NO MISSING CODES

LOW POWER: 250mW

INTERNAL REFERENCE

WIDEBAND TRACK/HOLD: 65MHz

SINGLE +5V SUPPLY

DESCRIPTION

The ADS802 is a low power, monolithic 12-bit, 10MHz
analog-to-digital converter utilizing a small geometry
CMOS process. This COMPLETE converter includes
a 12-bit quantizer, wideband track/hold, reference and
three-state outputs. It operates from a single +5V
power supply and can be configured to accept either
differential or single-ended input signals.

The ADS802 employs digital error correction in order
to provide excellent Nyquist differential linearity per-
formance for demanding imaging applications. Its low
distortion, high SNR, and high oversampling capability
give it the extra margin needed for telecommunications,
test instrumentation and video applications.

This high performance A/D converter is specified for
AC and DC performance at a 10MHz sampling rate.
The ADS802 is available in 28-lead SOIC and SSOP
packages.

12-Bit, 10MHz Sampling

ANALOG-TO-DIGITAL CONVERTER

APPLICATIONS

IF AND BASEBAND DIGITIZATION

DATA ACQUISITION CARDS

TEST INSTRUMENTATION

CCD IMAGING
Copiers
Scanners
Cameras

VIDEO DIGITIZING

GAMMA CAMERAS

Pipeline

A/D

Timing

Circuitry

Error

Correction

Logic

3-State

Outputs

T/H

12-Bit

Digital

Data

CLK

+1.25V

+3.25V

MSBI

REFT

REFB

ADS802U

ADS802E

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Internet: http://www.burr-brown.com/ · FAXLine: (800) 548-6133 (US/Canada Only) · Cable: BBRCORP · Telex: 066-6491 · FAX: (520) 889-1510 · Immediate Product Info: (800) 548-6132

ADS802

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.

ADS802U, E

PARAMETER

CONDITIONS

TEMP

MIN

TYP

MAX

UNITS

SPECIFICATIONS

At T

= +25

C, V

= +5V, and Sampling Rate = 10MHz, with a 50% duty cycle clock having 2ns rise/fall time, unless otherwise noted.

Resolution

Bits

Specified Temperature Range

AMBIENT

+85

ANALOG INPUT
Differential Full Scale Input Range

Both Inputs

+1.25

+3.25

Common-Mode Voltage

+2.25

Analog Input Bandwidth (3dB)

Small Signal

20dBFS

(1)

Input

+25

400

MHz

Full Power

0dBFS Input

+25

MHz

Input Impedance

1.25 || 4

|| pF

DIGITAL INPUT
Logic Family

TTL/HCT Compatible CMOS

Convert Command

Start Conversion

Falling Edge

ACCURACY

(2)

Gain Error

+25

0.6

1.5

Full

1.0

2.5

Gain Tempco

ppm/

Power Supply Rejection of Gain

Delta +V

+25

0.03

0.1

%FSR/%

Input Offset Error

Full

2.1

3.0

Power Supply Rejection of Offset

Delta +V

+25

0.05

0.1

%FSR/%

CONVERSION CHARACTERISTICS
Sample Rate

10k

10M

Sample/s

Data Latency

6.5

Convert Cycle

DYNAMIC CHARACTERISTICS
Differential Linearity Error

f = 500kHz

+25

0.3

1.0

LSB

C to +85

0.4

1.0

LSB

f = 5MHz

+25

0.4

1.0

LSB

C to +85

0.4

1.0

LSB

No Missing Codes

C to +85

Guaranteed

LSB

Integral Linearity Error at f = 500kHz

Best Fit

C to +85

1.7

2.75

LSB

Spurious-Free Dynamic Range (SFDR)

f = 500kHz (1dBFS input)

+25

dBFS

Full

dBFS

f = 5MHz (1dBFS input)

+25

dBFS

Full

dBFS

Two-Tone Intermodulation Distortion (IMD)

(3)

f = 4.4MHz and 4.5MHz (7dBFS each tone)

+25

dBc

Full

dBc

Signal-to-Noise Ratio (SNR)

f = 500kHz (1dBFS input)

+25

Full

f = 5MHz (1dBFS input)

+25

Full

Signal-to-(Noise + Distortion) (SINAD)

f = 500kHz (1dBFS input)

+25

Full

f = 5MHz (1dBFS input)

+25

Full

Differential Gain Error

NTSC or PAL

+25

0.5

Differential Phase Error

NTSC or PAL

+25

0.1

degrees

Aperture Delay Time

+25

Aperture Jitter

+25

ps rms

Overvoltage Recovery Time

(4)

1.5x Full Scale Input

+25

NOTE: (1) dBFS refers to dB below Full Scale. (2). Percentage accuracies are referred to the internal A/D Full Scale Range of 4Vp-p. (3) IMD is referred to the
larger of the two input signals. If referred to the peak envelope signal (

0dB), the intermodulation products will be 7dB lower. (4) No "rollover" of bits.

ADS802

ELECTROSTATIC
DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with ap-
propriate precautions. Failure to observe proper handling and
installation procedures can cause damage.

Electrostatic discharge can cause damage ranging from
performance degradation to complete device failure. Burr-
Brown Corporation recommends that all integrated circuits be
handled and stored using appropriate ESD protection
methods.

ABSOLUTE MAXIMUM RATINGS

....................................................................................................... +6V

Analog Input .............................................................. 0V to (+V

+ 300mV)

Logic Input ................................................................ 0V to (+V

+ 300mV)

Case Temperature ......................................................................... +100

Junction Temperature .................................................................... +150

Storage Temperature ..................................................................... +125

External Top Reference Voltage (REFT) .................................. +3.4V Max
External Bottom Reference Voltage (REFB) .............................. +1.1V Min

NOTE: Stresses above these ratings may permanently damage the device.

PACKAGE

DRAWING

TEMPERATURE

PRODUCT

PACKAGE

NUMBER

(1)

RANGE

ADS802U

28-Lead SOIC

217

C to +85

ADS802E

28-Lead SSOP

324

C to +85

NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

ADS802U, E

PARAMETER

CONDITIONS

TEMP

MIN

TYP

MAX

UNITS

SPECIFICATIONS

(CONT)

At T

= +25

C, V

= +5V, and Sampling Rate = 10MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.

OUTPUTS
Logic Family

TTL/HCT Compatible CMOS

Logic Coding

Logic Selectable

SOB or BTC

Logic Levels

Logic "LO"

Full

0.4

Logic "HI"

Full

2.0

3-State Enable Time

Full

3-State Disable Time

Full

POWER SUPPLY REQUIREMENTS
Supply Voltage: +V

Operating

Full

+4.75

+5.0

+5.25

Supply Current: +I

Operating

+25

Operating

Full

Power Consumption

Operating

+25

250

310

Operating

Full

260

310

Thermal Resistance,

28-Lead SOIC

C/W

28-Lead SSOP

C/W

ADS802

GND

B10

B11

B12

GND

REFT

REFB

MSBI

CLK

ADS802

PIN

DESIGNATOR

DESCRIPTION

GND

Ground

Bit 1, Most Significant Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

Bit 9

B10

Bit 10

B11

Bit 11

B12

Bit 12, Least Significant Bit

GND

Ground

+5V Power Supply

CLK

Convert Clock Input, 50% Duty Cycle

+5V Power Supply

HI: High Impedance State. LO or Floating: Nor-
mal Operation. Internal pull-down resistors.

MSBI

Most Significant Bit Inversion, HI: MSB inverted
for complementary output. LO or Floating: Straight
output. Internal pull-down resistors.

+5V Power Supply

REFB

Bottom Reference Bypass. For external bypass-
ing of internal +1.25V reference.

Common-Mode Voltage. It is derived by
(REFT + REFB)/2.

REFT

Top Reference Bypass. For external bypassing
of internal +3.25V reference.

+5V Power Supply

GND

Ground

Input

Complementary Input

GND

Ground

PIN DESCRIPTIONS

PIN CONFIGURATION

TOP VIEW

SOIC/SSOP

TIMING DIAGRAM

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

CONV

Convert Clock Period

100

Clock Pulse Low

Clock Pulse High

Aperture Delay

Data Hold Time, C

= 0pF

3.9

New Data Delay Time, C

= 15pF max

12.5

NOTE: (1) " " indicates the portion of the waveform that will stretch out at slower sample rates.

Track

Hold

"N"

Hold

"N + 1"

Hold

"N + 2"

Hold

"N + 3"

Hold

"N + 4"

Hold

"N + 5"

Hold

"N + 6"

Track

Data Valid

N-7

Data Valid

N-6

INTERNAL

TRACK/HOLD

CONVERT

CLOCK

OUTPUT

DATA

DATA LATENCY

(6.5 Clock Cycles)

CONV

Track

N-3

N-5

N-4

N-2

N-1

Track

Data Valid

N-8

(1)

Data Invalid

ADS802

100

Input Amplitude (dBm)

SFDR (dBFS)

SWEPT POWER SFDR

= 10MHz

DYNAMIC PERFORMANCE

vs SINGLE-ENDED FULL-SCALE INPUT RANGE

Single-Ended Full-Scale Range (Vp-p)

Dynamic Range (dB)

SNR (f

= 5MHz)

SFDR (f

= 5MHz)

TYPICAL PERFORMANCE CURVES

(CONT)

At T

= +25

C, V

= +5V, Sampling Rate = 10MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.

Input Amplitude (dBm)

SWEPT POWER SNR

SNR (dB)

= 5MHz

4.0

2.0

4.0

INTEGRAL LINEARITY ERROR

ILE (LSB)

1.0

2.0

3.0

4096

Code

= 500kHz

DYNAMIC PERFORMANCE

vs DIFFERENTIAL FULL-SCALE INPUT RANGE

Differential Full-Scale Input Range (Vp-p)

Dynamic Range (dB)

SFDR (f

= 5MHz)

SNR (f

= 5MHz)

DYNAMIC PERFORMANCE vs INPUT FREQUENCY

Frequency (Hz)

SFDR, SNR (dB)

100k

10M

SNR

SFDR

ADS802

SPURIOUS FREE DYNAMIC RANGE (SFDR)

vs TEMPERATURE

Ambient Temperature (°C)

SFDR (dBFS)

100

= 5MHz

= 500kHz

DIFFERENTIAL LINEARITY ERROR

vs TEMPERATURE

100

Ambient Temperature (°C)

DLE (LSBs)

1.0

0.8

0.6

0.4

0.2

0.1

= 5MHz

= 500kHz

TYPICAL PERFORMANCE CURVES

(CONT)

At T

= +25

C, V

= +5V, Sampling Rate = 10MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.

SIGNAL-TO-NOISE RATIO vs TEMPERATURE

Ambient Temperature (°C)

SNR (dB)

100

= 500kHz

= 5MHz

SIGNAL-TO-(NOISE + DISTORTION)

vs TEMPERATURE

Ambient Temperature (°C)

SINAD (dB)

100

= 500kHz

= 5MHz

SUPPLY CURRENT vs TEMPERATURE

Ambient Temperature (°C)

(mA)

100

POWER DISSIPATION vs TEMPERATURE

Ambient Temperature (°C)

(mW)

265

260

255

250

100

ADS802

FIGURE 2. Pipeline A/D Architecture.

FIGURE 1. Input Track/Hold Configuration with Timing

Signals.

OUT

Op Amp

Bias

Op Amp

Bias

Input Clock (50%)

Internal Non-overlapping Clock

THEORY OF OPERATION

The ADS802 is a high speed sampling analog-to-digital
converter with pipelining. It uses a fully differential archi-
tecture and digital error correction to guarantee 12-bit reso-
lution. The differential track/hold circuit is shown in Figure
1. The switches are controlled by an internal clock which
has a non-overlapping two phase signal,

1 and

2. At the

sampling time the input signal is sampled on the bottom
plates of the input capacitors. In the next clock phase,

2, the

bottom plates of the input capacitors are connected together
and the feedback capacitors are switched to the op amp
output. At this time the charge redistributes between C

and

, completing one track/hold cycle. The differential output

is a held DC representation of the analog input at the sample
time. The track/hold circuit can also convert a single-ended
input signal into a fully differential signal for the quantizer.

The pipelined quantizer architecture has 11 stages with each
stage containing a two-bit quantizer and a two bit digital-to-
analog converter, as shown in Figure 2. Each two-bit quan-
tizer stage converts on the edge of the sub-clock, which is
twice the frequency of the externally applied clock. The
output of each quantizer is fed into its own delay line to

B1 (MSB)

B10

B11

B12 (LSB)

2-Bit
DAC

2-Bit

Flash

Input

T/H

Digital Delay

2-Bit
DAC

2-Bit

Flash

Digital Delay

2-Bit

Flash

Digital Delay

2-Bit
DAC

2-Bit

Flash

Digital Delay

Digital Error Correction

STAGE 1

STAGE 2

STAGE 10

STAGE 11

ADS802

OUTPUT CODE

SOB

BTC

PIN 19

DIFFERENTIAL INPUT

(1)

FLOATING or LOW

HIGH

+FS (IN = +3.25V, IN = +1.25V)

111111111111

011111111111

+FS 1LSB

111111111111

011111111111

+FS 2LSB

111111111110

011111111110

+3/4 Full Scale

111000000000

011000000000

+1/2 Full Scale

110000000000

010000000000

+1/4 Full Scale

101000000000

001000000000

+1LSB

100000000001

000000000001

Bipolar Zero (IN = IN = +2.25V)

100000000000

000000000000

1LSB

011111111111

111111111111

1/4 Full Scale

011000000000

111000000000

1/2 Full Scale

010000000000

110000000000

3/4 Full Scale

001000000000

101000000000

FS +1LSB

000000000001

100000000001

FS (IN = +1.25V, IN = +3.25V)

000000000000

100000000000

Note: In the single-ended input mode, +FS = +4.25V and FS = +0.25V.

TABLE I. Coding Table for the ADS802.

time-align it with the data created from the following quan-
tizer stages. This aligned data is fed into a digital error
correction circuit which can adjust the output data based on
the information found on the redundant bits. This technique
gives the ADS802 excellent differential linearity and guar-
antees no missing codes at the 12-bit level.

Since there are two pipeline stages per external clock cycle,
there is a 6.5 clock cycle data latency from the start convert
signal to the valid output data. The output data is available in
Straight Offset Binary (SOB) or Binary Two's Complement
(BTC) format.

THE ANALOG INPUT AND INTERNAL REFERENCE

The analog input of the ADS802 can be configured in
various ways and driven with different circuits, depending
on the nature of the signal and the level of performance
desired. The ADS802 has an internal reference that sets the
full scale input range of the A/D. The differential input range
has each input centered around the common-mode of +2.25V,
with each of the two inputs having a full scale range of
+1.25V to +3.25V. Since each input is 2V peak-to-peak and
180

out of phase with the other, a 4V differential input

signal to the quantizer results. As shown in Figure 3, the
positive full scale reference (REFT) and the negative full
scale (REFB) are brought out for external bypassing. In
addition, the common-mode voltage (CM) may be used as a
reference to provide the appropriate offset for the driving
circuitry. However, care must be taken not to appreciably
load this reference node. For more information regarding
external references, single-ended input, and ADS802 drive
circuits, refer to the applications section.

FIGURE 3. Internal Reference Structure.

+1.25V

+3.25V

0.1µF

+2.25V

REFT

REFB

ADS802

Internal

Comparators

CLOCK REQUIREMENTS

The CLK pin accepts a CMOS level clock input. The rising
and falling edges of the externally applied convert command
clock control the various interstage conversions in the pipe-
line. Therefore, the duty cycle of the clock should be held at
50% with low jitter and fast rise/fall times of 2ns or less.
This is particularly important when digitizing a high fre-
quency input and operating at the maximum sample rate.
Deviation from a 50% duty cycle will effectively shorten
some of the interstage settling times, thus degrading the
SNR and DNL performance.

DIGITAL OUTPUT DATA

The 12-bit output data is provided at CMOS logic levels.
The standard output coding is Straight Offset Binary where
a full scale input signal corresponds to all "1's" at the output.
This condition is met with pin 19 "LO" or Floating due to an
internal pull-down resistor. By applying a logic "HI" voltage
to this pin, a Binary Two's Complement output will be
provided where the most significant bit is inverted. The
digital outputs of the ADS802 can be set to a high imped-
ance state by driving OE (pin 18) with a logic "HI". Normal
operation is achieved with pin 18 "LO" or Floating due to
internal pull-down resistors. This function is provided for
testability purposes and is not meant to drive digital buses
directly or be dynamically changed during the conversion
process.

APPLICATIONS

DRIVING THE ADS802

The ADS802 has a differential input with a common-mode
of +2.25V. For AC-coupled applications, the simplest way
to create this differential input is to drive the primary
winding of a transformer with a single-ended input. A
differential output is created on the secondary if the center
tap is tied to the common-mode voltage of +2.25V per
Figure 4. This transformer-coupled input arrangement pro-

FIGURE 4. AC-Coupled Single-Ended to Differential Drive

Circuit Using a Transformer.

Mini-circuits

T T1-6-KK81

or equivalent

ADS802

AC Input

Signal

22pF

0.1

ADS802

vides good high frequency AC performance. It is important
to select a transformer that gives low distortion and does not
exhibit core saturation at full scale voltage levels. Since the
transformer does not appreciably load the ladder, there is no
need to buffer the common-mode (CM) output in this in-
stance. In general, it is advisable to keep the current draw
from the CM output pin below 0.5

A to avoid nonlinearity

in the internal reference ladder. A FET input operational
amplifier such as the OPA130 can provide a buffered refer-
ence for driving external circuitry. The analog IN and IN
inputs should be bypassed with 22pF capacitors to minimize
track/hold glitches and to improve high input frequency
performance.

Figure 5 illustrates another possible low cost interface circuit
which utilizes resistors and capacitors in place of a trans-
former. Depending on the signal bandwidth, the component
values should be carefully selected in order to maintain the
performance outlined in the data sheet. The input capacitors,
C

, and the input resistors, R

, create a high-pass filter with

the lower corner frequency at f

= 1/(2

). The corner

frequency can be reduced by either increasing the value of
R

or C

. If the circuit operates with a 50

or 75

impedance level, the resistors are fixed and only the value of
the capacitor can be increased. Usually AC-coupling capaci-
tors are electrolytic or tantalum capacitors with values of
1

F or higher. It should be noted that these large capacitors

become inductive with increased input frequency, which
could lead to signal amplitude errors or oscillation. To
maintain a low AC-coupling impedance throughout the sig-
nal band, a small value (e.g. 1

F) ceramic capacitor could be

added in parallel with the polarized capacitor.

Capacitors C

SH1

and C

SH2

are used to minimize current

glitches resulting from the switching in the input track and
hold stage and to improve signal-to-noise performance. These
capacitors can also be used to establish a low-pass filter and
effectively reduce the noise bandwidth. In order to create a
real pole, resistors R

SER1

and R

SER2

were added in series with

each input. The cut-off frequency of the filter is determined

by f

= 1/(2

SER

·(C

ADC

)) where R

SER

is the resistor in

series with the input, C

is the external capacitor from the

input to ground, and C

ADC

is the internal input capacitance of

the A/D converter (typically 4pF).

Resistors R

and R

are used to derive the necessary common

mode voltage from the buffered top and bottom references.
The total load of the resistor string should be selected so that
the current does not exceed 1mA. Although the circuit in
Figure 5 uses two resistors of equal value so that the common
mode voltage is centered between the top and bottom refer-
ence (+2.25V), it is not necessary to do so. In all cases the
center point, V

, should be bypassed to ground in order to

provide a low impedance AC ground.

If the signal needs to be DC coupled to the input of the
ADS802, an operational amplifier input circuit is required.
In the differential input mode, any single-ended signal must
be modified to create a differential signal. This can be
accomplished by using two operational amplifiers, one in
the noninverting mode for the input and the other amplifier
in the inverting mode for the complementary input. The low
distortion circuit in Figure 6 will provide the necessary input
shifting required for signals centered around ground. It also
employs a diode for output level shifting to guarantee a low
distortion +3.25V output swing. Other amplifiers can be
used in place of the OPA642s if the lowest distortion is not
necessary. If output level shifting circuits are not used, care
must be taken to select operational amplifiers that give the
necessary performance when swinging to +3.25V with a

5V supply operational amplifier.

The ADS802 can also be configured with a single-ended
input full scale range of +0.25V to +4.25V by tying the
complementary input to the common-mode reference voltage
as shown in Figure 7. This configuration will result in
increased even-order harmonics, especially at higher input
frequencies. However, this tradeoff may be quite acceptable
for time-domain applications. The driving amplifier must
give adequate performance with a +0.25V to +4.25V output
swing in this case.

FIGURE 5. AC-Coupled Differential Input Circuit.

ADS8xx

SER1

49.9

(6k

)

(6k

)

0.1

SH1

22pF

SH2

22pF

0.1

IN1

IN2

SER2

49.9

+3.25V

Top Reference

+1.25V

Bottom Reference

NOTE: * indicates optional component.

ADS802

FIGURE 6. A Low Distortion DC-Coupled, Single-Ended to Differential Input Driver Circuit.

FIGURE 7. Single-Ended Input Connection.

ADS801

0.1µF

Single-Ended

Input Signal

Full Scale = +0.25V to +4.25V with internal references.

22pF

EXTERNAL REFERENCES AND ADJUSTMENT OF
FULL SCALE RANGE

The internal reference buffers are limited to approximately
1mA of output current. As a result, these internal +1.25V
and +3.25V references may be overridden by external refer-
ences that have at least 18mA (at room temperature) of
output drive capability. In this instance, the common-mode
voltage will be set halfway between the two references. This
feature can be used to adjust the gain error, improve gain
drift, or to change the full scale input range of the ADS801.
Changing the full scale range to a lower value has the benefit
of easing the swing requirements of external input amplifi-
ers. The external references can vary as long as the value of
the external top reference (REFT

EXT

) is less than or equal to

+3.4V and the value of the external bottom reference
(REFB

EXT

) is greater than or equal to +1.1V and the differ-

ence between the external references are greater than or
equal to 1.5V.

For the differential configuration, the full scale input range
will be set to the external reference values that are selected. For
the single-ended mode, the input range is 2·(REFT

EXT

REFB

EXT

), with the common-mode being centered at

(REFT

EXT

+ REFB

EXT

)/2. Refer to the typical performance

curves for expected performance vs full scale input range.

The circuit in Figure 8 works completely on a single +5V
supply. As a reference element, it uses the micro-power
reference REF1004-2.5, which is set to a quiescent current
of 0.1mA. Amplifier A

is configured as a follower to buffer

the +1.25V generated from the resistor divider. To provide
the necessary current drive, a pull-down resistor, R

added.

Amplifier A

is configured as an adjustable gain stage, with

a range of approximately 1 to 1.32. The pull-up resistor
again relieves the op amp from providing the full current
drive. The value of the pull-up/down resistors is not critical
and can be varied to optimize power consumption. The need
for pull-up/down resistors depends only on the drive capa-
bility of the selected drive amplifiers and thus can be
omitted.

PC BOARD LAYOUT AND BYPASSING

A well-designed, clean PC board layout will assure proper
operation and clean spectral response. Proper grounding and
bypassing, short lead lengths, and the use of ground planes
are particularly important for high frequency circuits. Mul-
tilayer PC boards are recommended for best performance
but if carefully designed, a two-sided PC board with large,
heavy ground planes can give excellent results. It is recom-
mended that the analog and digital ground pins of the
ADS801 be connected directly to the analog ground plane.
In our experience, this gives the most consistent results. The
A/D power supply commons should be tied together at the
analog ground plane. Power supplies should be bypassed
with 0.1

F ceramic capacitors as close to the pin as possible.

604

301

604

49.9

301

604

2.49k

+2.25V

OPA642

OPA130

301

0.1µF

OPA642

+5V

(2)

+5V

BAS16

(1)

BAS16

(1)

301

24.9

Input Level
Shift Buffer

Optional

High Impedance

Input Amplifier

DC-Coupled

Input Signal

26 IN

22 CM

27 IN

ADS801

NOTES: (1) A Philips BAS16 diode or equivalent
may be used. (2) Supply bypassing not shown.

22pF

604

0.1µF

ADS802

FIGURE 9. ADS802 Interface Schematic with AC-Coupling and External Buffers.

DYNAMIC PERFORMANCE TESTING

The ADS801 is a high performance converter and careful
attention to test techniques is necessary to achieve accurate
results. Highly accurate phase-locked signal sources allow
high resolution FFT measurements to be made without
using data windowing functions. A low jitter signal genera-
tor such as the HP8644A for the test signal, phase-locked
with a low jitter HP8022A pulse generator for the A/D
clock, gives excellent results. Low pass filtering (or bandpass
filtering) of test signals is absolutely necessary to test the
low distortion of the ADS801. Using a signal amplitude
slightly lower than full scale will allow a small amount of
"headroom" so that noise or DC offset voltage will not
overrange the A/D and cause clipping on signal peaks.

Sinewave Signal Power

Noise + Harmonic Power (first 15 harmonics)

DYNAMIC PERFORMANCE DEFINITIONS

1. Signal-to-Noise-and-Distortion Ratio (SINAD):

10 log

2. Signal-to-Noise Ratio (SNR):

10 log

3. Intermodulation Distortion (IMD):

10 log

IMD is referenced to the larger of the test signals f

or f

Five "bins" either side of peak are used for calculation of
fundamental and harmonic power. The "0" frequency bin
(DC) is not included in these calculations as it is of little
importance in dynamic signal processing applications.

Highest IMD Product Power (to 5th-order)

Sinewave Signal Power

Noise Power

GND

LSB

MSB

GND

CLK

MSBI

REFB

REFT

GND

ADS800

0.1µF

Ext
Clk

AC Input

Signal

Dir

G+

Dir

G+

IDT74FCT2245

Mini-Circuits
T T1-6-KK81

or equivalent

22pF

(1)

NOTE: (1) All capacitors should be located as close to the pins as the manufacturing
process will allow. Ceramic X7R surface-mount capacitors or equivalent are recommended.

+5V

FIGURE 8. Optional External Reference to Set the Full-Scale Range Utilizing a Dual, Single-Supply Op Amp.

+2.5V to +3.25V

+5V

220

10k

6.2k

0.1

+2.5V

10k

1/2

OPA2234

1/2

OPA2234

Bottom
Reference

Top
Reference

REF1004

+1.25V

10k

NOTE: (*) Use parts alternatively for adjustment capability.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADS802E

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ADS802E