Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE/ORDERING INFORMATION
- ELECTRICAL CHARACTERISTICS
- DEVICE INFORMATION
- PIN DIAGRAM
- PIN DESCRIPTIONS
- TIMING DIAGRAM
- REFERENCE AND FULL-SCALE RANGE SELECT
- TYPICAL CHARACTERISTICS
- APPLICATION INFORMATION
- THEORY OF OPERATION
- DRIVING THE ANALOG INPUTS
- Types of Applications
- Differential versus Single-Ended
- Input Full-Scale Range versus Performance
- Input Biasing (Vcm)
- Input Impedance
- INPUT DRIVER CONFIGURATIONS
- Transformer Coupled Interface Circuits
- Transformer Coupled, Single-Ended to Differential Configuration
- AC-Coupled, Differential Interface with Gain
- REFERENCE
- REFERENCE OPERATION
- Using External References
- DIGITAL INPUTS AND OUTPUTS
- CLOCK INPUT
- MINIMUM SAMPLING RATE
- DATA OUTPUT FORMAT (BTC)
- Output Enable (OE)\
- Power Down (PD)
- Over-Range Indicator (OVR)
- Output Loading
- POWER SUPPLIES
- Digital Output Driver Supply (VDRV)
- LAYOUT AND DECOUPLING CONSIDERATIONS
- LAYOUT OF PCB WITH PowerPAD THERMALLY ENHANCED PACKAGES
- PACKAGE DRAWING
- PHP (S-PQFP-G48)PowerPAD(tm) PLASTIC QUAD FLATPACK
ADS808
12-Bit
Pipelined
ADC Core
Reference and
Mode Select
Reference Ladder
and Driver
Timing Circuitry
Error
Correction
Logic
3-State
Outputs
T&H
D0
D11
+V
S
ADS808
CLK
CLK
OE
SEL2
REFB
V
REF
REFT
VDRV
IN
1Vp-p
1Vp-p
CM
(+2.5V)
SEL1
DV
OVR
IN
12-Bit, 70MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q
DYNAMIC RANGE:
SNR: 64dB at 10MHz f
IN
SFDR: 68dB at 10MHz f
IN
q
PREMIUM TRACK-AND-HOLD:
Low Jitter: 0.25ps rms
Differential or Single-Ended Inputs
Selectable Full-Scale Input Range
q
FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking
Down to 0.5Vp-p
Variable Threshold Level
DESCRIPTION
The ADS808 is a high-dynamic range, 12-bit, 70MHz,
pipelined Analog-to-Digital Converter (ADC). It includes a
high-bandwidth linear track-and-hold that has a low jitter of
only 0.25ps rms, leading to excellent SNR performance. The
clock input can accept a low-level differential sine wave or
square wave signal down to 0.5Vp-p, further improving the
SNR performance. It also accepts a single-ended clock
signal and has flexible threshold levels.
The ADS808 has a 2Vp-p differential input range (1Vp-p 2
inputs) for optimum signal-to-noise ratio. The differential
operation gives the lowest even-order harmonic compo-
nents. A lower input voltage of 1.5Vp-p or 1Vp-p can also be
selected using the internal references, further optimizing
SFDR. Alternatively, a single-ended input range can be used
by tying the IN input to the common-mode voltage, if desired.
The ADS808 also provides an over-range flag that indicates
when the input signal has exceeded the converter's full-scale
range. This flag can also be used to reduce the gain of the
front-end signal conditioning circuitry. It also employs digital
error-correction techniques to provide excellent differential
linearity for demanding imaging applications. The ADS808 is
available in a small TQFP-48 PowerPADTM thermally en-
hanced package.
APPLICATIONS
q
BASESTATION WIDEBAND RADIOS:
CDMA, GSM, TDMA, 3G, AMPS, and NMT
q
TEST INSTRUMENTATION
q
CCD IMAGING
ADS808
SBAS179C DECEMBER 2000 REVISED SEPTEMBER 2002
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments.
ADS808
2
SBAS179C
www.ti.com
ELECTRICAL CHARACTERISTICS
At T
A
= full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, V
S
= +5V, and internal reference, unless otherwise noted.
SPECIFIED
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE-LEAD
DESIGNATOR
(1)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
ADS808Y
TQFP-48
PHP
40
C to +85
C
ADS808Y
ADS808Y/250
Tape and Reel, 250
"
"
"
"
"
ADS808Y/2K
Tape and Reel, 2000
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.
PACKAGE/ORDERING INFORMATION
+V
S
....................................................................................................... +6V
Analog Input .......................................................... (0.3V) to (+V
S
+ 0.3V)
Logic Input ............................................................ (0.3V) to (+V
S
+ 0.3V)
Case Temperature ......................................................................... +100
C
Junction Temperature .................................................................... +150
C
Storage Temperature ..................................................................... +150
C
NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
(1)
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
ADS808Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
12 Tested
Bits
SPECIFIED TEMPERATURE RANGE
Ambient Air
40 to +85
C
ANALOG INPUT
Standard Differential Input Range
(1Vp-p 2, +10dBm)
1
2
V
Single-Ended Input Voltage
1Vp-p
2
3
V
Common-Mode Voltage
2.5
V
Optional Input Ranges
Selectable
1Vp-p or 1.5Vp-p
V
Analog Input Bias Current
1
A
Track-Mode Input Bandwidth
3dBFS
1
GHz
Input Impedance
Static, No Clock
1.25 || 9
M
|| pF
CONVERSION CHARACTERISTICS
Sample Rate
1M
70M
Samples/s
Data Latency
5
Clk Cyc
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
0.7
+1.7/1.0
LSB
No Missing Codes
Tested
Integral Nonlinearity Error, f = 1MHz
4.0
7.0
LSBs
Spurious-Free Dynamic Range
(1)
f = 1MHz
72
dBFS
(2)
f = 10MHz
65
68
dBFS
2-Tone Intermodulation Distortion
f
IN
= 19.4MHz and 20.4MHz (7dB each tone)
77
dBFS
Signal-to-Noise Ratio (SNR)
f = 1MHz
64.5
dBFS
f = 10MHz
64
dBFS
Signal-to-(Noise + Distortion) (SINAD)
f = 2.2MHz
64
dBFS
f = 10MHz
63
dBFS
Output Noise
Input AC-Grounded
0.3
LSBs rms
Aperture Delay Time
3
ns
Aperture Jitter
0.25
ps rms
Over-Voltage Recovery Time
2
ns
Full-Scale Step Acquisition Time
5
ns
DIGITAL INPUTS
Logic Family
+3V/+5V Logic Compatible CMOS
Convert Command
Start Conversion
Rising Edge of Convert Clock
High-Level Input Current (V
IN
= 5V)
(3)
100
A
Low-Level Input Current (V
IN
= 0V)
10
A
High-Level Input Voltage
+2.0
V
Low-Level Input Voltage
+1.0
V
Input Capacitance
5
pF
ADS808
3
SBAS179C
www.ti.com
ELECTRICAL CHARACTERISTICS
(Cont.)
At T
A
= full specified temperature range, differential input range = 1V to 2V, sampling rate = 70MHz, V
S
= +5V, and internal reference, unless otherwise noted.
ADS808Y
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+3V/+5V Compatible CMOS
Straight Offset Binary
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (I
OL
= 50
A to 1.6mA)
VDRV = 3V
+0.2
V
High Output Voltage, (I
OH
= 50
A to 0.5mA)
+2.5
V
Low Output Voltage, (I
OL
= 50
A to 1.6mA)
VDRV = 5V
+0.2
V
High Output Voltage, (I
OH
= 50
A to 1.6mA)
+2.5
V
3-State Enable Time
OE = LOW
20
40
ns
3-State Disable Time
OE = HIGH
2
10
ns
Output Capacitance
5
pF
ACCURACY (Internal Reference, = 2V, Unless Otherwise Noted)
Zero Error (Midscale)
at 25
C
0.5
%FS
Zero Error Drift (Midscale)
12
ppm/
C
Gain Error
(4)
at 25
C
1.5
%FS
Gain Error Drift
(4)
38
ppm/
C
Gain Error
(5)
at 25
C
0.75
%FS
Gain Error Drift
(5)
20
ppm/
C
Power-Supply Rejection of Gain
V
S
=
5%
68
dB
Internal REF Tolerance (V
REFP
V
REFN
)
Deviation from Ideal
10
40
mV
Reference Input Resistance
660
POWER-SUPPLY REQUIREMENTS
Supply Voltage: +V
S
Operating
+4.75
+5.0
+5.25
V
Supply Current: +I
S
Operating
142
mA
Output Driver Supply Current (VDRV)
10
mA
Power Dissipation: VDRV = 5V
Internal Reference
740
mW
VDRV = 3V
Internal Reference
720
770
mW
VDRV = 5V
External Reference
720
mW
VDRV = 3V
External Reference
700
mW
Power Down
Operating
20
mW
Thermal Resistance,
JA
TQFP-48
28.8
C/W
NOTES: (1) Spurious-Free Dynamic Range refers to the magnitude of the largest harmonic. (2) dBFS means dB relative to Full-Scale. (3) A 50k
pull-down
resistor is inserted internally. (4) Includes internal reference. (5) Excludes internal reference.
ADS808
4
SBAS179C
www.ti.com
26
VDRV
Output Bit Driver Voltage Supply
27
GND
Ground
28
I
OE
Output Enable: HI = High Impedance;
LO or Floating: Normal Operation
29
I
PD
Power Down: HI = Power Down; LO = Normal
30
I
BTC
HI = Binary Two's Complement;
LO = Straight Binary
31
GND
Ground
32
SEL2
Reference Select 2: See Table on Page 5.
33
SEL1
Reference Select 1: See Table on Page 5.
34
V
REF
Internal Reference Voltage
35
GND
Ground
36
GND
Ground
37
GND
Ground
38
GND
Ground
39
REFB
Bottom Reference Voltage Bypass
40
CM
Common-Mode Voltage (mid-scale)
41
REFT
Top Reference Voltage Bypass
42
GND
Ground
43
GND
Ground
44
I
IN
Complementary Analog Input
45
GND
Ground
46
I
IN
Analog Input
47
+V
S
Supply Voltage
48
+V
S
Supply Voltage
1
BYP
Bypass Point
2
+V
S
Supply Voltage
3
+V
S
Supply Voltage
4
+V
S
Supply Voltage
5
GND
Ground
6
I
CLK
Clock Input
7
I
CLK
Complementary Clock Input
8
GND
Ground
9
GND
Ground
10
O
OVR
Over-Range Indicator
11
O
DV
Data Valid Pulse: HI = Data Valid
12
NC
No Connection
13
NC
No Connection
14
O
D11
Data Bit 11, (MSB)
15
O
D10
Data Bit 10
16
O
D9
Data Bit 9
17
O
D8
Data Bit 8
18
O
D7
Data Bit 7
19
O
D6
Data Bit 6
20
O
D5
Data Bit 5
21
O
D4
Data Bit 4
22
O
D3
Data Bit 3
23
O
D2
Data Bit 2
24
O
D1
Data Bit 1
25
O
D0
Data Bit 0, (LSB)
36
35
34
33
32
31
30
29
28
27
26
25
GND
GND
V
REF
SEL1
SEL2
GND
BTC
PD
OE
GND
VDRV
D0 (LSB)
+V
S
+V
S
IN
GND
IN
GND
GND
REFT
CM
REFB
GND
GND
NC
D11 (MSB)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
1
2
3
4
5
6
7
8
9
10
11
12
BYP
+V
S
+V
S
+V
S
GND
CLK
CLK
GND
GND
OVR
DV
NC
48
47
46
45
44
43
42
41
40
39
38
13
14
15
16
17
18
19
20
21
22
23
37
24
ADS808Y
PIN
I/O
DESIGNATOR
DESCRIPTION
PIN
I/O
DESIGNATOR
DESCRIPTION
PIN DESCRIPTIONS
PIN DIAGRAM
Top View
TQFP
ADS808
5
SBAS179C
www.ti.com
DESIRED
INTERNAL
FULL-SCALE RANGE
SEL1
SEL2
V
REF
1Vp-p
V
REF
GND
0.5V
1.5Vp-p
GND
+V
S
0.75V
2Vp-p
GND
GND
1.0V
REFERENCE AND FULL-SCALE RANGE SELECT
NOTE: For external reference operation, tie V
REF
to +V
S
and apply REFT and REFB externally. Internal voltage buffer of CM is powered up. The full-scale input range
is equal to 2x the reference value (REFT REFB).
TIMING DIAGRAM
SYMBOL
DESCRIPTION
MIN
(1)
TYP
MAX
(1)
UNITS
t
CONV
Convert Clock Period
14.3
1
s
ns
t
H
Clock Pulse HIGH
7
t
CONV
/2
ns
t
L
Clock Pulse LOW
7
t
CONV
/2
ns
t
A
Aperture Delay
4.6
6.1
ns
t
DV
Data Valid Pulse Delay
(2)
11.5
14
ns
t
1
Data Hold Time, C
L
= 0pF
4
5
ns
t
2
New Data Delay Time, C
L
= 15pF max
9
11
ns
NOTES: (1) Timing values based on simulation at room temperature. Min/Max values provided for
design estimation only. (2) Measured from the 50% point of the clock to the time when signals are
within valid logic levels.
t
A
t
CONV
t
H
N 5
N 4
N 3
N 2
N 1
N
N + 1
Data Bits Out
Data Valid Pulse
Clock
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
Analog In
t
L
t
1
t
DV
5 Clock Cycles
t
2
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