ADS822
ADS825
10-Bit, 40MHz Sampling
ANALOG-TO-DIGITAL CONVERTERS
FEATURES
q
HIGH SNR: 60dB
q
HIGH SFDR: 72dBFS
q
LOW POWER: 190mW
q
INTERNAL/EXTERNAL REFERENCE OPTION
q
SINGLE-ENDED OR
FULLY DIFFERENTIAL ANALOG INPUT
q
PROGRAMMABLE INPUT RANGE
q
LOW DNL: 0.5LSB
q
SINGLE +5V SUPPLY OPERATION
q
+3V OR +5V LOGIC I/O COMPATIBLE (ADS825)
q
POWER DOWN: 20mW
q
28-LEAD SSOP PACKAGE
APPLICATIONS
q
MEDICAL IMAGING
q
TEST EQUIPMENT
q
COMPUTER SCANNERS
q
COMMUNICATIONS
q
VIDEO DIGITIZING
DESCRIPTION
The ADS822 and ADS825 are pipeline, CMOS analog-to-digital
converters that operate from a single +5V power supply. These
converters provide excellent performance with a single-ended
input and can be operated with a differential input for added
spurious performance. These high-performance converters in-
clude a 10-bit quantizer, high-bandwidth track-and-hold, and a
high-accuracy internal reference. They also allow for the user to
disable the internal reference and utilize external references. This
external reference option provides excellent gain and offset
matching when used in multi-channel applications or in applica-
tions where full-scale range adjustment is required.
The ADS822 and ADS825 employ digital error correction tech-
niques to provide excellent differential linearity for demanding
imaging applications. Its low distortion and high SNR give the
extra margin needed for medical imaging, communications,
video, and test instrumentation. The ADS822 and ADS825 offer
power dissipation of 190mW and also provide a power-down
mode, thus reducing power dissipation to only 20mW. The
ADS825 is +3V or +5V Logic I/O compatible.
The ADS822 and ADS825 are specified at a maximum sampling
frequency of 40MHz and a single-ended input range of 1.5V to
3.5V. The ADS822 and ADS825 are available in a 28-lead SSOP
package and are pin-for-pin compatible with the 10-bit, 60MHz
ADS823 and ADS826, and the 10-bit, 70MHz ADS824, provid-
ing an upgrade path to higher sampling frequencies.
TM
1997 Burr-Brown Corporation
PDS-1385E
Printed in U.S.A. October, 1999
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/ Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
For most current data sheet and other product
information, visit www.burr-brown.com
10-Bit
Pipelined
A/D Core
Internal
Reference
Optional External
Reference
Timing
Circuitry
Error
Correction
Logic
3-State
Outputs
T/H
CLK
VDRV
ADS822
ADS825
+V
S
OE
PD
Int/Ext
D0
D9
IN
V
IN
IN
CM
ADS822
ADS825
2
ADS822, ADS825
SPECIFICATIONS
At T
A
= full specified temperature range, V
S
= +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
CMOS-Compatible
Rising Edge of Convert Clock
CMOS-Compatible
Straight Offset Binary
CMOS-Compatible
Straight Offset Binary
ADS822E
ADS825E
(1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
RESOLUTION
10 Guaranteed
10 Guaranteed
Bits
SPECIFIED TEMPERATURE RANGE
Ambient Air
40 to +85
40 to +85
C
ANALOG INPUT
Standard Single-Ended Input Range
2Vp-p
1.5
3.5
T
T
V
Optional Single-Ended Input Range
1Vp-p
2
3
T
T
V
Common-Mode Range
2.5
T
V
Optional Differential Input Range
2Vp-p
2
3
T
T
V
Analog Input Bias Current
1
T
A
Input Impedance
1.25 || 5
T
M
|| pF
Track-Mode Input Bandwidth
3dBFS Input
300
T
MHz
CONVERSION CHARACTERISTICS
Sample Rate
10k
40M
T
T
Samples/s
Data Latency
5
T
Clk Cyc
DYNAMIC CHARACTERISTICS
Differential Linearity Error (largest code error)
f = 1MHz
0.25
1.0
T
T
LSB
f = 10MHz
0.5
T
LSB
No Missing Codes
Guaranteed
Guaranteed
Integral Nonlinearity Error, f = 1MHz
0.5
2.0
T
T
LSBs
Spurious Free Dynamic Range
(2)
Referred to Full Scale
f = 1MHz
72
71
dBFS
(3)
f = 10MHz
63
66
60
65
dBFS
Two-Tone Intermodulation Distortion
(4)
f = 9.5MHz and 9.9MHz (7dB each tone)
67
T
dBc
Signal-to-Noise Ratio (SNR)
Referred to Full Scale
f = 1MHz
60
T
dB
f = 10MHz
57
60
T
T
dB
Signal-to-(Noise + Distortion) (SINAD)
Referred to Full Scale
f = 1MHz
59
T
dB
f = 10MHz
56
58
T
T
dB
Effective Number of Bits
(5)
, f = 1MHz
9.5
T
Bits
Output Noise
Input Tied to Common-Mode
0.2
T
LSBs rms
Aperture Delay Time
3
T
ns
Aperture Jitter
1.2
T
ps rms
Overvoltage Recovery Time
2
T
ns
Full-Scale Step Acquisition Time
5
T
ns
DIGITAL INPUTS
Logic Family
Convert Command
Start Conversion
High Level Input Current
(6)
(V
IN
= 5V
DD
)
100
T
A
Low Level Input Current (V
IN
= 0V)
10
T
A
High Level Input Voltage
+3.5
+2.0
V
Low Level Input Voltage
+1.0
+0.8
V
Input Capacitance
5
T
pF
DIGITAL OUTPUTS
Logic Family
Logic Coding
Low Output Voltage (I
OL
= 50
A to 1.6mA)
VDRV = 5V
+0.1
T
V
High Output Voltage, (I
OH
= 50
A to 0.5mA)
+4.9
T
V
Low Output Voltage, (I
OL
= 50
A to 1.6mA)
VDRV = 3V
+0.1
T
V
High Output Voltage, (I
OH
= 50
A to 0.5mA)
+2.8
T
V
3-State Enable Time
OE = H to L
2
40
T
T
ns
3-State Disable Time
OE = L to H
2
10
T
T
ns
Output Capacitance
5
T
pF
ACCURACY (Internal Reference, 2Vp-p, Unless Otherwise Noted)
Zero Error (referred to FS)
at 25
C
1.0
3.0
T
T
% FS
Zero Error Drift (referred to FS)
5
T
ppm/
C
Midscale Offset Error
at 25
C
0.29
% FS
Gain Error
(7)
at 25
C
1.5
2.5
T
T
% FS
Gain Error Drift
(7)
38
T
ppm/
C
Gain Error
(8)
at 25
C
0.75
1.5
T
T
% FS
Gain Error Drift
(8)
25
T
ppm/
C
Power Supply Rejection of Gain
V
S
=
5%
70
T
dB
REFT Tolerance
Deviation From Ideal 3.5V
10
25
T
T
mV
REFB Tolerance
Deviation From Ideal 1.5V
10
25
T
T
mV
External REFT Voltage Range
REFB + 0.8
3.5
V
S
1.25
T
T
T
V
External REFB Voltage Range
1.25
1.5
REFT 0.8
T
T
T
V
Reference Input Resistance
REFT to REFB
1.6
T
k
TTL, +3V/+5V CMOS-Compatible
Rising Edge of Convert Clock
3
ADS822, ADS825
SPECIFICATIONS
(Cont.)
At T
A
= full specified temperature range, V
S
= +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
PIN
DESIGNATOR
DESCRIPTION
1
GND
Ground
2
Bit 1
Data Bit 1 (D9) (MSB)
3
Bit 2
Data Bit 2 (D8)
4
Bit 3
Data Bit 3 (D7)
5
Bit 4
Data Bit 4 (D6)
6
Bit 5
Data Bit 5 (D5)
7
Bit 6
Data Bit 6 (D4)
8
Bit 7
Data Bit 7 (D3)
9
Bit 8
Data Bit 8 (D2)
10
Bit 9
Data Bit 9 (D1)
11
Bit 10
Data Bit 10 (D0) (LSB)
12
OE
Output Enable. HI = high impedance state
LO = normal operation (internal pull-down
resistor)
13
PD
Power Down. HI = enable; LO = disable
14
CLK
Convert Clock Input
15
+V
S
+5V Supply
16
GND
Ground
17
RSEL
Input Range Select. HI = 2V; LO = 1V
18
INT/EXT
Reference Select. HI = external, LO = internal
19
REFB
Bottom Reference
20
ByB
Bottom Ladder Bypass
21
ByT
Top Ladder Bypass
22
REFT
Top Reference
23
CM
Common-Mode Voltage Output
24
IN
Complementary Input ()
25
IN
Analog Input (+)
26
GND
Analog Ground
27
+V
S
+5V Supply
28
VDRV
Output Logic Driver Supply Voltage
PIN DESCRIPTIONS
Top View
SSOP
PIN CONFIGURATION
POWER SUPPLY REQUIREMENTS
Supply Voltage: +V
S
Operating
+4.75
+5.0
+5.25
T
T
T
V
Supply Current: +I
S
Operating (External Reference)
40
T
mA
Power Dissipation: VDRV = 5V
External Reference
200
230
T
T
mW
VDRV = 3V
External Reference
190
T
mW
VDRV = 5V
Internal Reference
250
T
mW
VDRV = 3V
Internal Reference
240
T
mW
Power Down
Operating
20
T
mW
Thermal Resistance,
JA
28-Lead SSOP
89
T
C/W
T
Indicates the same specifications as the ADS822E.
NOTES: (1) ADS825E accepts a +3V clock input. (2) Spurious Free Dynamic Range refers to the magnitude of the largest harmonic. (3) dBFS means dB relative to Full Scale. (4) Two-tone intermodulation
distortion is referred to the largest fundamental tone. This number will be 6dB higher if it is referred to the magnitude of the two-tone fundamental envelope. (5) Effective number of bits (ENOB) is defined
by (SINAD 1.76)/6.02. (6) A 50k
pull-down resistor is inserted internally on OE pin. (7) Includes internal reference. (8) Excludes internal reference.
ADS822E
ADS825E
(1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
GND
Bit 1 (MSB)
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Bit 9
Bit 10 (LSB)
OE
PD
CLK
VDRV
+V
S
GND
IN
IN
CM
REFT
ByT
ByB
REFB
INT/EXT
RSEL
GND
+V
S
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS822
ADS825
4
ADS822, ADS825
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights
or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.
TIMING DIAGRAM
5 Clock Cycles
Data Invalid
t
D
t
L
t
H
t
CONV
N5
N4
N3
N2
N1
N
N+1
N+2
Data Out
Clock
Analog In
N
t
2
N+1
N+2
N+3
N+4
N+5
N+6
N+7
t
1
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
CONV
Convert Clock Period
25
100
s
ns
t
L
Clock Pulse Low
11.5
12.5
ns
t
H
Clock Pulse High
11.5
12.5
ns
t
D
Aperture Delay
3
ns
t
1
Data Hold Time, C
L
= 0pF
3.9
ns
t
2
New Data Delay Time, C
L
= 15pF max
12
ns
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
+V
S
....................................................................................................... +6V
Analog Input ............................................................. 0.3V to (+V
S
+ 0.3V)
Logic Input ............................................................... 0.3V to (+V
S
+ 0.3V)
Case Temperature ......................................................................... +100
C
Junction Temperature .................................................................... +150
C
Storage Temperature ..................................................................... +150
C
ABSOLUTE MAXIMUM RATINGS
PACKAGE
SPECIFIED
DRAWING
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
PACKAGE
NUMBER
RANGE
MARKING
NUMBER
(1)
MEDIA
ADS822E
SSOP-28
324
40
C to +85
C
ADS822E
ADS822E
Rails
"
"
"
"
"
ADS822E/1K
Tape and Reel
ADS825E
SSOP-28
324
40
C to +85
C
ADS825E
ADS825E
Rails
"
"
"
"
"
ADS825E/1K
Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of ADS822E/1K" will get a single 1000-piece Tape and Reel.
PACKAGE/ORDERING INFORMATION
PRODUCT
DEMO BOARD
ADS822E
DEM-ADS822E
DEMO BOARD ORDERING INFORMATION
5
ADS822, ADS825
SPECTRAL PERFORMANCE
Frequency (MHz)
Magnitude (dB)
0
20
40
60
80
100
0
5
10
15
20
f
IN
= 10MHz
SPECTRAL PERFORMANCE
(Single-Ended, 1Vp-p)
Frequency (MHz)
Magnitude (dB)
0
20
40
60
80
100
0
5
10
15
20
f
IN
= 20MHz
SNR = 57dBFS
SFDR = 70dBFS
SPECTRAL PERFORMANCE
(Single-Ended, 1Vp-p)
Frequency (MHz)
Magnitude (dB)
0
20
40
60
80
100
0
5
10
15
20
f
IN
= 10MHz
SNR = 57dBFS
SFDR = 71dBFS
SPECTRAL PERFORMANCE
(Differential Input, 1Vp-p)
Frequency (MHz)
Magnitude (dB)
0
20
40
60
80
100
0
5
10
15
20
f
IN
= 10MHz
SNR = 58dBFS
SFDR = 74dBFS
SPECTRAL PERFORMANCE
Frequency (MHz)
Magnitude (dB)
0
20
40
60
80
100
0
5
10
15
20
f
IN
= 1MHz
UNDERSAMPLING
(Differential Input, 2Vp-p)
Frequency (MHz)
Magnitude (dB)
0
20
40
60
80
100
0
5
10
15
20
f
S
= 40MHz
f
IN
= 45MHz
SNR = 60dBFS
SFDR = 74dBFS
TYPICAL PERFORMANCE CURVES
At T
A
= full specified temperature range, V
S
= +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
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