Document Outline
- FEATURES
- APPLICATIONS
- DESCRIPTION
- ABSOLUTE MAXIMUM RATINGS
- PACKAGE/ORDERING INFORMATION
- PACKAGE DISSIPATION RATING TABLE
- EQUIVALENT INPUT CIRCUIT
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS: V DD = +5V
- ELECTRICAL CHARACTERISTICS: V DD = +2.7V
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATION
- PIN DESCRIPTIONS
- TIMING DIAGRAMS
- TIMING CHARACTERISTICS
- TYPICAL CHARACTERISTICS: V DD = +5V
- TYPICAL CHARACTERISTICS: V DD= +2.7V
- THEORY OF OPERATION
- ANALOG INPUT
- REFERENCE INPUT
- DIGITAL INTERFACE
- SIGNAL LEVELS
- SERIAL INTERFACE
- DATA FORMAT
- POWER DISSIPATION
- LAYOUT
- APPLICATION CIRCUITS
- PACKAGE DRAWING
- DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE
- DRB (S-PDSO-N8) PLASTIC SMALL OUTLINE
ADS8325
DESCRIPTION
The ADS8325 is a 16-bit, sampling, Analog-to-Digital (A/D)
converter specified for a supply voltage range from 2.7V to
5.5V. It requires very little power, even when operating at the
full 100kHz data rate. At lower data rates, the high speed of
the device enables it to spend most of its time in the power-
down mode. For example, the average power dissipation is
less than 1mW at a 10kHz data rate.
The ADS8325 offers excellent linearity and very low noise
and distortion. It also features a synchronous serial (SPI/SSI
compatible) interface and a differential input. The reference
voltage can be set to any level within the range of 2.5V to
V
DD
.
Low power and small size make the ADS8325 ideal for
portable and battery-operated systems. It is also a perfect fit
for remote data acquisition modules, simultaneous multi-
channel systems, and isolated data acquisition. The ADS8325
is available in MSOP-8 and SON-8 packages.
The SON package size is the same as a 3x3 QFN package.
FEATURES
q
16-BITS NO MISSING CODES
q
VERY LOW NOISE: 3LSBp-p
q
EXCELLENT LINEARITY:
1.5LSB typ
q
microPOWER: 4.5mW at 100kHz
1mW at 10kHz
q
MSOP-8 AND SON-8 PACKAGES
(SON Package Size Same as 3x3 QFN)
q
16-BIT UPGRADE TO THE 12-BIT ADS7816
AND ADS7822
q
PIN-COMPATIBLE WITH THE ADS7816,
ADS7822, ADS7826, ADS7827, ADS7829, AND
ADS8320
q
SERIAL (SPI
TM
/SSI) INTERFACE
16-Bit, High-Speed, 2.7V to 5.5V
microPower Sampling
ANALOG-TO-DIGITAL CONVERTER
www.ti.com
Copyright 2002-2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SBAS226A MARCH 2002 REVISED JUNE 2003
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SAR
Serial
Interface
Comparator
ADS8325
S/H Amp
DCLOCK
D
OUT
CS/SHDN
+IN
REF
IN
CDAC
APPLICATIONS
q
BATTERY-OPERATED SYSTEMS
q
REMOTE DATA ACQUISITION
q
ISOLATED DATA ACQUISITION
q
SIMULTANEOUS SAMPLING, MULTI-CHANNEL
SYSTEMS
q
INDUSTRIAL CONTROLS
q
ROBOTICS
q
VIBRATION ANALYSIS
All trademarks are the property of their respective owners.
ADS8
325
ADS8
325
ADS8325
2
SBAS226A
www.ti.com
MAXIMUM
NO
INTEGRAL
MISSING
SPECIFIED
LINEARITY
CODES ERROR
PACKAGE-
PACKAGE
TEMPERATURE
PACKAGE
ORDERING
TRANSPORT
PRODUCT
ERROR (LSB)
(LSB)
(1)
LEAD
DESIGNATOR
(2)
RANGE
MARKING
NUMBER
MEDIA, QUANTITY
ADS8325I
6
15
MSOP-8
DGK
40
C to 85
C
B25
ADS8325IDGKT
Tape and Reel, 250
"
"
"
"
"
"
"
ADS8325IDGKR
Tape and Reel, 2500
ADS8325IB
4
16
MSOP-8
DGK
40
C to 85
C
B25
ADS8325IBDGKT
Tape and Reel, 250
"
"
"
"
"
"
"
ADS8325IBDGKR
Tape and Reel, 2500
ADS8325I
6
15
SON-8
DRB
40
C to 85
C
B25
ADS8325IDRBT
Tape and Reel, 250
"
"
"
"
"
"
"
ADS8325IDRBR
Tape and Reel, 2500
ADS8325IB
4
16
SON-8
DRB
40
C to 85
C
B25
ADS8325IBDRBT
Tape and Reel, 250
"
"
"
"
"
"
"
ADS8325IBDRBR
Tape and Reel, 2500
NOTE: (1) No Missing Codes Error specifies a 5V power supply and reference voltage. (2) For the most current specifications and package information, refer to
our web site at www.ti.com.
PACKAGE/ORDERING INFORMATION
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature, unless otherwise noted.
Supply Voltage, DGND to V
DD ..................................................................
0.3V to 6V
Analog Input Voltage
(2) ...............................................................
0.3V to V
DD
+ 0.3V
Reference Input Voltage
(2) ........................................................
0.3V to V
DD
+ 0.3V
Digital Input Voltage
(2) .............................................................
0.3V to V
DD
+ 0.3V
Input Current to Any Pin Except Supply ......................... 20mA to 20mA
Power Dissipation ....................................... See Dissipation Rating Table
Operating Virtual Junction Temperature Range, T
J
...... 40
C to +150
C
Operating Free-Air Temperature Range, T
A
.................... 40
C to +85
C
Storage Temperature Range, T
STG
................................ 65
C to +150
C
Lead Temperature 1.6mm (1/16 inch) from Case for 10sec ..................... 260
C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper han-
dling and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTES: (1) Stresses beyond those listed under "absolute maximum ratings"
may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those
indicated under "recommended operating conditions" is not implied. Exposure
to absolute-maximum-rated conditions of extended periods may affect device
reliability. (2) All voltage values are with respect to ground terminal.
EQUIVALENT INPUT CIRCUIT
DERATING FACTOR
T
A
25
C
T
A
= 70
C
T
A
= 85
C
PACKAGE
R
JC
R
JA
ABOVE T
A
= 25
C
POWER RATING
POWER RATING
POWER RATING
DGK
39.1
C/W
206.3
C/W
4.847mW/
C
606mW
388mW
315mW
DRB
5
C/W
45.8
C/W
3.7mW/
C
370mW
204mW
148mW
MIN
TYP
MAX
UNIT
Supply Voltage
Low-Voltage Levels
2.7
3.6
V
GND to V
DD
5V Logic Levels
4.5
5.0
5.5
V
Reference Input Voltage
2.5
V
DD
V
Analog Input
IN
0.3
0
0.5
V
Voltage
+IN (IN)
0
V
REF
V
Operating Junction Temperature
40
125
C
Range, T
J
RECOMMENDED OPERATING CONDITIONS
PACKAGE DISSIPATION RATING TABLE
R
ON
20
C
(SAMPLE)
20pF
Shut-Down
Switch
V
DD
I/O
GND
V
DD
ANALOG IN
GND
Diode Turn-On Voltage: 0.35V
Equivalent Analog Input Circuit
V
DD
REF
GND
Equivalent Reference
Input Circuit
Equivalent Digital Input/Output Circuit
20pF
5k
ADS8325
3
SBAS226A
www.ti.com
ELECTRICAL CHARACTERISTICS: V
DD
= +5V
Over recommended operating free-air temperature at 40
C to +85
C, V
REF
= +5V, IN = GND, f
SAMPLE
= 100kHz, and f
CLK
= 24 f
SAMPLE
, unless otherwise noted.
ADS8325I
ADS8325IB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Range
FSR
+IN (IN)
0
V
REF
V
Operating Common-Mode Signal
0.3
0.5
V
Input Resistance
IN = GND
5
G
Input Capacitance
IN = GND, During Sampling
45
pF
Input Leakage Current
IN = GND
50
nA
Differential Input Capacitance
+IN to IN, During Sampling
20
pF
Full-Power Bandwith
FSBW
f
S
Sinewave, SINAD at 3dB
20
kHz
DC ACCURACY
Resolution
16
Bits
No Missing Code
NMC
15
16
Bits
Integral Linearity Error
INL
3
6
1.5
4
LSB
Offset Error
V
OS
0.75
1.5
0.5
1
mV
Offset Error Drift
TCV
OS
0.2
ppm/
C
Gain Error
G
ERR
24
12
LSB
Gain Error Drift
TCG
ERR
0.3
ppm/
C
Noise
20
VRMS
Power-Supply Rejection
4.75V
V
DD
5.25
3
LSB
SAMPLING DYNAMICS
Conversion Time
t
CONV
24kHz < f
CLK
2.4MHz
6.667
666.7
s
Acquisition Time
t
AQ
f
CLK
= 2.4MHz
1.875
s
Throughout Rate
100
kSPS
Clock Frequency
0.024
2.4
MHz
AC ACCURACY
Total Harmonic Distortion
THD
5Vp-p Sinewave, at 1kHz
100
106
dB
Spurious-Free Dynamic Range
SFDR
5Vp-p Sinewave, at 1kHz
100
108
dB
Signal-to-Noise Ratio
SNR
90
91
dB
Signal-to-Noise + Distortion
SINAD
5Vp-p Sinewave, at 1kHz
90
91
dB
Effective Number of Bits
ENOB
14.6
14.7
Bits
VOLTAGE REFERENCE INPUT
Reference Voltage
2.5
V
DD
+ 0.3
V
Reference Input Resistance
CS = GND, f
SAMPLE
= 0Hz
5
k
CS = V
DD
5
G
Reference Input Capacitance
20
pF
Reference Input Current
1
1.5
mA
CS = V
DD
0.1
A
DIGITAL INPUTS
(1)
Logic Family
CMOS
High-Level Input Voltage
V
IH
0.7 V
DD
V
DD
+ 0.3
V
Low-Level Input Voltage
V
IL
0.3
0.3 V
DD
V
Input Current
I
IN
V
I
= V
DD
or GND
50
nA
Input Capacitance
C
I
5
pF
DIGITAL OUTPUTS
(1)
Logic Family
CMOS
High-Level Output Voltage
V
OH
V
DD
= 4.5V, I
OH
= 100
A
4.44
V
Low-Level Output Voltage
V
OL
V
DD
= 4.5V, I
OL
= 100
A
0.5
V
High-Impedance-State Output Current
I
OZ
CS = V
DD
, V
I
= V
DD
or GND
50
nA
Output Capacitance
C
O
5
pF
Load Capacitance
C
L
30
pF
Data Format
Straight Binary
indicates the same specifications as the ADS8325I.
NOTE: (1) Applies for 5.0V nominal supply: V
DD
(min) = 4.5V and V
DD
(max) = 5.5V.
ADS8325
4
SBAS226A
www.ti.com
ELECTRICAL CHARACTERISTICS: V
DD
= +2.7V
Over recommended operating free-air temperature at 40
C to +85
C, V
REF
= +2.5V, IN = GND, f
SAMPLE
= 100kHz, and f
CLK
= 24 f
SAMPLE
, unless otherwise noted.
ADS8325I
ADS8325IB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Full-Scale Range
FSR
+IN (IN)
0
V
REF
V
Operating Common-Mode Signal
0.3
0.5
V
Input Resistance
IN = GND
5
G
Input Capacitance
IN = GND, During Sampling
45
pF
Input Leakage Current
IN = GND
50
nA
Differential Input Capacitance
+IN to IN, During Sampling
20
pF
Full-Power Bandwith
FSBW
f
S
Sinewave, SINAD at 3dB
4
kHz
DC ACCURACY
Resolution
16
Bits
No Missing Code
NMC
14
15
Bits
Integral Linearity Error
INL
3
6
1.5
4
LSB
Offset Error
V
OS
0.75
1.5
0.5
1
mV
Offset Error Drift
TCV
OS
3
ppm/
C
Gain Error
G
ERR
33
16
LSB
Gain Error Drift
TCG
ERR
0.3
ppm/
C
Noise
20
VRMS
Power-Supply Rejection
2.7V
V
DD
3.6V
7
LSB
SAMPLING DYNAMICS
Conversion Time
t
CONV
24kHz < f
CLK
2.4MHz
6.667
666.7
s
Acquisition Time
t
AQ
f
CLK
= 2.4MHz
1.875
s
Throughout Rate
100
kSPS
Clock Frequency
0.024
2.4
MHz
AC ACCURACY
Total Harmonic Distortion
THD
2.5Vp-p Sinewave, at 1kHz
94
dB
Spurious-Free Dynamic Range
SFDR
2.5Vp-p Sinewave, at 1kHz
96
dB
Signal-to-Noise Ratio
SNR
85
86
dB
Signal-to-Noise + Distortion
SINAD
2.5Vp-p Sinewave, at 1kHz
85
85.5
dB
Effective Number of Bits
ENOB
13.8
13.9
Bits
VOLTAGE REFERENCE INPUT
Reference Voltage
2.5
V
DD
+ 0.3
V
Reference Input Resistance
CS = GND, f
SAMPLE
= 0Hz
5
k
CS = V
DD
5
G
Reference Input Capacitance
20
pF
Reference Input Current
0.5
0.75
mA
CS = V
DD
0.1
A
DIGITAL INPUTS
(1)
Logic Family
LVCMOS
High-Level Input Voltage
V
IH
V
DD
= 3.6V
2
V
DD
+ 0.3
V
Low-Level Input Voltage
V
IL
V
DD
= 2.7V
0.3
0.8
V
Input Current
I
IN
V
I
= V
DD
or GND
50
nA
Input Capacitance
C
I
5
pF
DIGITAL OUTPUTS
(1)
Logic Family
LVCMOS
High-Level Output Voltage
V
OH
V
DD
= 2.7V, I
OH
= 100
A
V
DD
0.2
V
Low-Level Output Voltage
V
OL
V
DD
= 2.7V, I
OL
= 100
A
0.2
V
High-Impedance-State Output Current
I
OZ
CS = V
DD
, V
I
= V
DD
or GND
50
nA
Output Capacitance
C
O
5
pF
Load Capacitance
C
L
30
pF
Data Format
Straight Binary
indicates the same specifications as the ADS8325I.
NOTE: (1) Applies for 3.0V nominal supply: V
DD
(min) = 2.7V and V
DD
(max) = 3.6V.
ADS8325
5
SBAS226A
www.ti.com
PIN CONFIGURATION
NAME
PIN
I/O
DESCRIPTION
REF
1
AI
Reference Input
+IN
2
AI
Noninverting Input
IN
3
AI
Inverting Analog Input
GND
4
P
Ground
CS/SHDN
5
DI
Chip Select when LOW, Shutdown Mode when
HIGH.
D
OUT
6
DO
The serial output data word.
DCLOCK
7
DI
Data Clock synchronizes the serial data transfer
and determines conversion speed.
V
DD
8
P
Power Supply
NOTE: AI is Analog Input, DI is Digital Input, DO is Digital Output, and P is
Power-Supply Connection.
Top View
MSOP
ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature at 40
C to 85
C, V
REF
= V
DD
, IN = GND, f
SAMPLE
= 100kHz, and f
CLK
= 24 f
SAMPLE
, unless otherwise noted.
ADS8325I
ADS8325IB
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
POWER-SUPPLY REQUIREMENTS
Power Supply (V
DD)
Low-Voltage Levels
2.7
3.6
V
5V Logic Levels
4.5
5.5
V
Operating Supply Current (I
DD
)
V
DD
= 3V
0.75
1.5
mA
V
DD
= 5V
0.9
1.5
mA
Power-Down Supply Current (I
DD
)
V
DD
= 3V
0.1
A
V
DD
= 5V
0.2
A
Power Dissipation
V
DD
= 3V
2.25
4.5
mW
V
DD
= 5V
4.5
7.5
mW
Power Dissipation in Power-Down
V
DD
= 3V, CS = V
DD
0.3
W
V
DD
= 5V, CS = V
DD
0.6
W
indicates the same specifications as the ADS8325I.
1
2
3
4
8
7
6
5
+V
DD
DCLOCK
D
OUT
CS/SHDN
REF
+IN
IN
GND
ADS8325
PIN DESCRIPTIONS
1
2
3
4
8
7
6
5
+V
DD
DCLOCK
D
OUT
CS/SHDN
REF
+IN
IN
GND
ADS8325
Top View
SON
ADS8325
6
SBAS226A
www.ti.com
D
OUT
1.4V
Test Point
3k
100pF
C
LOAD
Load Circuit for t
dDO
, t
r
, and t
f
Voltage Waveforms for D
OUT
Rise and Fall Times, t
r
, t
f
Voltage Waveforms for D
OUT
Delay Times, t
dDO
Voltage Waveforms for t
dis
Voltage Waveforms for t
en
Load Circuit for t
dis
and t
en
t
r
D
OUT
90%
10%
t
f
D
OUT
Test Point
t
dis
Waveform 2, t
en
V
CC
t
dis
Waveform 1
100pF
C
LOAD
3k
t
dis
CS/SHDN
D
OUT
Waveform 1
(1)
D
OUT
Waveform 2
(2)
90%
10%
90%
4
1
B15
5
t
en
CS/SHDN
DCLOCK
D
OUT
t
dDO
D
OUT
DCLOCK
t
hDO
NOTES: (1) Waveform 1 is for an output with internal
conditions such that the output is HIGH unless disabled by the
output control. (2) Waveform 2 is for an output with internal
conditions such that the output is LOW unless disabled by the
output control.
Timing Diagrams and Test Circuits for the Parameters in the Timing Characteristics table.
CS/SHDN
D
OUT
DCLOCK
Complete Cycle
Power Down
Conversion
Sample
Use positive clock edge for data transfer
t
SUCS
t
CONV
t
SMPL
NOTE: A minimum of 22 clock cycles are required for 16-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
B15
(MSB)
B14 B13 B12 B11 B10 B9
B8
B0
(LSB)
B7
B1
B6
B2
B5
B3
B4
Hi-Z
0
Hi-Z
t
CSD
TIMING CHARACTERISTICS
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
SMPL
Analog Input Sample Time
4.5
5.0
Clk Cycles
t
CONV
Conversion Time
16
Clk Cycles
t
CYC
Throughput Rate
100
kHz
t
CSD
CS Falling to DCLOCK LOW
0
ns
t
SUCS
CS Falling to DCLOCK Rising
20
ns
t
HDO
DCLOCK Falling to Current D
OUT
Not Valid
5
15
ns
t
DIS
CS Rising to D
OUT
Tri-State
70
100
ns
t
EN
DCLOCK Falling to D
OUT
Enabled
20
50
ns
t
F
D
OUT
Fall Time
5
25
ns
t
R
D
OUT
Rise Time
7
25
ns
TIMING DIAGRAMS
ADS8325
7
SBAS226A
www.ti.com
TYPICAL CHARACTERISTICS: V
DD
= +5V
At T
A
= 25
C, V
DD
= +5V, V
REF
= +5V, f
SAMPLE
= 100kHz, f
CLK
= 24 f
SAMPLE
, unless otherwise noted.
3
2
1
0
1
2
3
ILE(LSBS)
0000
H
4000
H
8000
H
C000
H
FFFF
H
Output Code
INTEGRAL LINEARITY ERROR vs CODE
0
20
40
60
80
100
120
140
160
Amplitude (dB)
0
10
20
30
40
50
Frequency (kHz)
FREQUENCY SPECTRUM
(8192 point FFT, F
IN
= 1.0132kHz, 0.2dB)
0
20
40
60
80
100
120
140
160
Amplitude (dB)
0
10
20
30
40
50
Frequency (kHz)
FREQUENCY SPECTRUM
(8192 point FFT, F
IN
= 10.0022kHz, 0.2dB)
SNR
SINAD
105
100
95
90
85
80
75
70
65
SNR and SINAD (dB)
1
10
100
245
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-NOISE + DISTORTION vs
INPUT FREQUENCY
3
2
1
0
1
2
3
DLE(LSBS)
0000
H
4000
H
8000
H
C000
H
FFFF
H
Output Code
DIFFERENTIAL LINEARITY ERROR vs CODE
110
105
100
95
90
85
80
75
70
110
105
100
95
90
85
80
75
70
SFDR (dB)
THD (dB)
1
10
100
245
Frequency (kHz)
SPURIOUS-FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs
INPUT FREQUENCY
SFDR
THD
(1)
NOTE: (1) First nine
harmonics of the
input frequency.
ADS8325
8
SBAS226A
www.ti.com
TYPICAL CHARACTERISTICS: V
DD
= +5V
(Cont.)
At T
A
= 25
C, V
DD
= +5V, V
REF
= +5V, f
SAMPLE
= 100kHz, f
CLK
= 24 f
SAMPLE
, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
Signal-to-Noise + Distortion (dB)
80
70
60
50
40
30
20
10
0
Input Level (dB)
SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL
F
IN
= 1.0132kHz
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
Ef
fective Number of Bits
1
10
100
Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
0.4
0.2
0.0
0.2
0.4
0.6
0.8
Delta from 25
C (dB)
50
25
0
25
50
75
100
Temperature (
C)
CHANGE IN SIGNAL-TO-NOISE + DISTORTION
vs TEMPERATURE
F
IN
= 1.0132kHz, 0.2dB
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
Delta from 25
C (LSBS)
50
25
0
25
50
75
100
Temperature (
C)
CHANGE IN GAIN vs TEMPERATURE
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.5
1.0
Delta from 25
C (LSBS)
50
25
0
25
50
75
100
Temperature (
C)
CHANGE IN UPO vs TEMPERATURE
1.1
1.0
0.9
0.8
0.7
Supply Current (mA)
50
25
0
25
50
75
100
Temperature (
C)
SUPPLY CURRENT vs TEMPERATURE
ADS8325
9
SBAS226A
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3
2
1
0
1
2
3
ILE(LSBS)
0000
H
4000
H
8000
H
C000
H
FFFF
H
Output Code
INTEGRAL LINEARITY ERROR vs CODE
3
2
1
0
1
2
3
DLE(LSBS)
0000
H
4000
H
8000
H
C000
H
FFFF
H
Output Code
DIFFERENTIAL LINEARITY ERROR vs CODE
0
20
40
60
80
100
120
140
160
Amplitude (dB)
0
10
20
30
40
50
Frequency (kHz)
FREQUENCY SPECTRUM
(8192 point FFT, F
IN
= 1.0132kHz, 0.2dB)
0
20
40
60
80
100
120
140
160
Amplitude (dB)
0
10
20
30
40
50
Frequency (kHz)
FREQUENCY SPECTRUM
(8192 point FFT, F
IN
= 10.0022kHz, 0.2dB)
SNR
SINAD
95
85
75
65
55
45
SNR and SINAD (dB)
1
10
100
245
Frequency (kHz)
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-NOISE + DISTORTION vs
INPUT FREQUENCY
100
90
80
70
60
50
40
100
90
80
70
60
50
40
SFDR (dB)
THD (dB)
1
10
100
245
Frequency (kHz)
SPURIOUS FREE DYNAMIC RANGE AND
TOTAL HARMONIC DISTORTION vs
INPUT FREQUENCY
SFDR
THD
(1)
NOTE: (1) First nine
harmonics of the
input frequency.
TYPICAL CHARACTERISTICS: V
DD
= +2.7V
At T
A
= 25
C, V
DD
= 2.7V, V
REF
= 2.5V, f
SAMPLE
= 100kHz, f
CLK
= 24 f
SAMPLE
, unless otherwise noted.
ADS8325
10
SBAS226A
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TYPICAL CHARACTERISTICS: V
DD
= +2.7V
(Cont.)
At T
A
= 25
C, V
DD
= 2.7V, V
REF
= 2.5V, f
SAMPLE
= 100kHz, f
CLK
= 24 f
SAMPLE
, unless otherwise noted.
100
90
80
70
60
50
40
30
20
10
Signal-to-Noise + Distortion (dB)
80
70
60
50
40
30
20
10
0
Input Level (dB)
SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL
F
IN
= 1.0132kHz
0.9
0.8
0.7
0.6
Supply Current (mA)
50
25
0
25
50
75
100
Temperature (
C)
SUPPLY CURRENT vs TEMPERATURE
1.2
0.8
0.4
0.0
0.4
0.8
Delta from 25
C (LSBS)
50
25
0
25
50
75
100
Temperature (
C)
CHANGE IN UPO vs TEMPERATURE
2.0
1.5
1.0
0.5
0.0
0.5
1.0
1.5
2.0
Delta from 25
C (LSBS)
50
25
0
25
50
75
100
Temperature (
C)
CHANGE IN GAIN vs TEMPERATURE
0.4
0.2
0.0
0.2
0.4
0.6
0.8
Delta from 25
C (dB)
50
25
0
25
50
75
100
Temperature (
C)
CHANGE IN SIGNAL-TO-NOISE + DISTORTION
vs TEMPERATURE
F
IN
= 1.0132kHz, 0.2dB
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
Ef
fective Number of Bits
1
10
100
Frequency (kHz)
EFFECTIVE NUMBER OF BITS
vs INPUT FREQUENCY
ADS8325
11
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THEORY OF OPERATION
The ADS8325 is a classic Successive Approximation Register
(SAR) Analog-to-Digital (A/D) converter. The architecture is based
on capacitive redistribution that inherently includes a sample-and-
hold function. The converter is fabricated on a 0.6
CMOS
process. The architecture and process allow the ADS8325 to
acquire and convert an analog signal at up to 100,000 conver-
sions per second while consuming less than 4.5mW from +V
DD
.
The ADS8325 requires an external reference, an external clock,
and a single power source (V
DD
). The external reference can be
any voltage between 2.5V and 5.5V. The value of the reference
voltage directly sets the range of the analog input. The reference
input current depends on the conversion rate of the ADS8325.
The external clock can vary between 24kHz (1kHz throughput)
and 2.4MHz (100kHz throughput). The duty cycle of the clock is
essentially unimportant as long as the minimum high and low
times are at least 200ns (V
DD
= 4.75V or greater). The minimum
clock frequency is set by the leakage on the internal capacitors
to the ADS8325.
The analog input is provided to two input pins: +IN and IN. When
a conversion is initiated, the differential input on these pins is
sampled on the internal capacitor array. While a conversion is in
progress, both inputs are disconnected from any internal function.
The digital result of the conversion is clocked out by the DCLOCK
input and is provided serially, most significant bit first, on the D
OUT
pin. The digital data that is provided on the D
OUT
pin is for the
conversion currently in progress--there is no pipeline delay. It is
possible to continue to clock the ADS8325 after the conversion
is complete and to obtain the serial data least significant bit first.
See the Digital Timing section for more information.
ANALOG INPUT
The analog input of ADS8325 is differential. The +IN and
IN input pins allow for a differential input signal. The
amplitude of the input is the difference between the +IN and
IN input, or (+IN) (IN). Unlike some converters of this
type, the IN input is not resampled later in the conversion
cycle. When the converter goes into the hold mode or
conversion, the voltage difference between +IN and IN is
captured on the internal capacitor array.
The range of the IN input is limited to 0.3V to +0.5V. Due
to this, the differential input could be used to reject signals
that are common to both inputs in the specified range. Thus,
the IN input is best used to sense a remote signal ground
that may move slightly with respect to the local ground
potential.
The general method for driving the analog input of the
ADS8325 is shown in Figures 1 and 2. The IN input is held
at the common-mode voltage. The +IN input swings from
IN (or common-mode voltage) to IN + V
REF
(or common-
mode voltage + V
REF
), and the peak-to-peak amplitude is
+V
REF
. The value of V
REF
determines the range over which
the common-mode voltage may vary (see Figure 3). Figures
5 and 6 illustrate the typical change in gain and offset as a
function of the common-mode voltage applied to the IN pin.
FIGURE 2. Methods of Driving the ADS8325
FIGURE 1. Differential Input Mode of the ADS8325.
ADS8325
0V to +V
REF
Peak-to-Peak
Common-Mode
Voltage
The input current required by the analog inputs depends on
a number of factors: sample rate, input voltage, source
impedance, and power-down mode. Essentially, the current
into the ADS8325 charges the internal capacitor array during
the sample period. After this capacitance has been fully
charged, there is no further input current. The source of the
analog input voltage must be able to charge the input
capacitance (20pF) to a 16-bit settling level within 4.5 clock
cycles (1.875
s). When the converter goes into the hold
mode, or while it is in the power-down mode, the input
impedance is greater than 1G
.
Common-Mode Voltage
+ V
REF
+V
REF
t
+IN
Common-Mode
Voltage
NOTE: The maximum differential voltage between +IN and IN of the ADS8325 is V
REF
.
See Figure 3 for a further explanation of the common-mode voltage range for differential inputs.
IN = Common-Mode Voltage
ADS8325
12
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FIGURE 3. +IN Analog Input: Common-Mode Voltage Range
vs V
REF
.
60
50
40
30
20
10
0
10
Delta Relative to V
CM
= 0V (LSBS)
0.4 0.3 0.2 0.1 0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
V
CM
(V)
CHANGE IN GAIN vs COMMON-MODE VOLTAGE
V
DD
= 5V
V
REF
= 4V
0.4 0.3 0.2 0.1 0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
V
CM
(V)
30
20
10
0
10
20
Delta Relative to V
CM
= 0V (LSBS)
CHANGE IN UPO vs COMMON-MODE VOLTAGE
V
DD
= 5V
V
REF
= 4V
FIGURE 5. Change in Gain vs Common-Mode Voltage.
FIGURE 6. Change in Unipolar Offset vs Common-Mode
Voltage.
FIGURE 4. Single-Ended and Differential Methods of Interfacing the ADS8325.
2
3
4
5
6
V
REF
(V)
Common Voltage Range (V)
1
0
1
0.3
0.5
4.8
2.5
V
DD
= 5V
50
20
OPA340
20pF
100pF
1nF
50
20
OPA340
20pF
100pF
+IN
IN
ADS8325
50
20
OPA340
20pF
100pF
20
20pF
+IN
IN
ADS8325
Single-Ended
Differential
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the IN
input should not drop below GND 0.3V or exceed
GND + 0.5V. The +IN input should always remain within the
range of GND 0.3V to V
DD
+ 0.3V, or IN to IN + V
REF
,
whichever limit is reached first. Outside of these ranges, the
converter's linearity may not meet specifications.
To minimize noise, low bandwidth input signals with low-
pass filters should be used. In each case, care should be
taken to ensure that the output impedance of the sources
driving the +IN and IN inputs are matched. Often, a small
capacitor (20pF) between the positive and negative inputs
helps to match their impedance. To obtain maximum perfor-
mance from the ADS8325, the input circuit from Figure 4 is
recommended.
ADS8325
13
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FIGURE 7. Change in Offset and Gain versus the Difference
between Power-Supply and Reference Voltage.
FIGURE 8. Input Reference Circuit and its Interface.
3.0
2.5
2.0
1.5
1.0
0.5
0
0.5
Delta (mV)
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75
0
V
DD
to V
REF
(V)
CHANGE IN OFFSET AND GAIN vs
SUPPLY/REFERENCE DIFFERENTIAL
Offset
Gain
100
OPA340
20pF
47
F
ADS8325
5k
V
REF
REFERENCE INPUT
The external reference sets the analog input range. The
ADS8325 will operate with a reference in the range of 2.5V
to V
DD
. There are several important implications to this.
As the reference voltage is reduced, the analog voltage
weight of each digital output code is reduced. This is often
referred to as the Least Significant Bit (LSB) size and is equal
to the reference voltage divided by 65,536. This means that
any offset or gain error inherent in the A/D converter will
appear to increase, in terms of LSB size, as the reference
voltage is reduced. For a reference voltage of 2.5V, the value
of LSB is 38.15
V, and for reference voltage of 5V, the LSB
is 76.3
V.
The noise inherent in the converter will also appear to
increase with lower LSB size. With a 5V reference, the
internal noise of the converter typically contributes only
1.5LSBs peak-to-peak of potential error to the output code.
When the external reference is 2.5V, the potential error
contribution from the internal noise will be 2 times larger
(3LSBs). The errors due to the internal noise are Gaussian
in nature and can be reduced by averaging consecutive
conversion results.
For more information regarding noise, consult the typical
characteristic "Peak-to-Peak Noise vs Reference Voltage."
Note that the Effective Number Of Bits (ENOB) figure is
calculated based on the converter's signal-to-(noise + distor-
tion) ratio with a 1kHz, 0dB input signal. SINAD is related to
ENOB as follows:
SINAD = 6.02 ENOB + 1.76
As the difference between the power-supply voltage and refer-
ence voltage increases, the gain and offset performance of the
converter will decrease. Figure 7 shows the typical change in
gain and offset as a function of the difference between the
power-supply voltage and reference voltage. For the combina-
tion of V
DD
= 2.7V and V
REF
= 2.5V, or V
DD
= 5V and V
REF
= 5V,
offset and gain error will be minimal. The most dramatic
difference in offset can be seen when V
DD
= 5V and V
REF
= 2.5V.
With lower reference voltages, extra care should be taken to
provide a clean layout including adequate bypassing, a clean
power supply, a low-noise reference, and a low-noise input
signal. Due to the lower LSB size, the converter will also be
more sensitive to external sources of error, such as nearby
digital signals and electromagnetic interference.
The equivalent input circuit for the reference voltage is
presented in the Figure 8. The 5k
resistor presents a
constant load during the conversion process. At the same
time, an equivalent capacitor of 20pF is switched. To obtain
optimum performance from the ADS8325, special care must
be taken in designing the interface circuit to the reference
input pin. To ensure a stable reference voltage, a 47
F
tantalum capacitor with low ESR should be connected as
close as possible to the input pin. If a high output impedance
reference source is used, an additional operational amplifier
with a current limiting resistor must be placed in front of the
capacitors.
When the ADS8325 is in power-down mode, the input resis-
tance of the reference pin will have a value of 5G
. Since the
input capacitors must be recharged before the next conversion
starts, an operational amplifier with good dynamic character-
istics must be used to buffer the reference input.
NOISE
The transition noise of the ADS8325 itself is extremely low
(see Figures 9 and 10); it is much lower than competing A/D
converters. These histograms were generated by applying a
low-noise DC input and initiating 5000 conversions. The digital
output of the A/D converter will vary in output code due to the
internal noise of the ADS8325. This is true for all 16-bit, SAR-
type A/D converters. Using a histogram to plot the output
codes, the distribution should appear bell-shaped with the
peak of the bell curve representing the nominal code for the
input value. The
1
,
2
, and
3
distributions will represent
the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The
transition noise can be calculated by dividing the number of
codes measured by 6 and this will yield the
3
distribution, or
99.7%, of all codes. Statistically, up to three codes could fall
outside the distribution when executing 1000 conversions. The
ADS8325, with < 3 output codes for the
3
distribution, will
yield a <
0.5LSBs of transition noise. Remember, to achieve
this low-noise performance, the peak-to-peak noise of the
input signal and reference must be < 50
V.
ADS8325
14
SBAS226A
www.ti.com
7FFE
4005
7FFF
476
519
8000
Code
8001
0
0
7FFD
V
DD
= 5.0V
V
REF
= 5.0V
7FFE
3499
7FFF
683
649
90
79
8000
Code
8001
7FFD
V
DD
= 2.7V
V
REF
= 2.5V
FIGURE 9. 5000 Conversion Histogram of a DC Input.
FIGURE 10. 5000 Conversion Histogram of a DC Input.
AVERAGING
The noise of the A/D converter can be compensated by
averaging the digital codes. By averaging conversion results,
transition noise will be reduced by a factor of 1/
n
, where n
is the number of averages. For example, averaging four
conversion results will reduce the transition noise from
0.5LSB to
0.25LSB. Averaging should only be used for
input signals with frequencies near DC.
For AC signals, a digital filter can be used to low-pass filter
and decimate the output codes. This works in a similar
manner to averaging; for every decimation by 2, the signal-
to-noise ratio will improve 3dB.
DIGITAL INTERFACE
SIGNAL LEVELS
The ADS8325 has a wide range of power-supply voltage.
The A/D converter, as well as the digital interface circuit, is
designed to accept and operate from 2.7V up to 5.5V. This
voltage range will accommodate different logic levels.
When the ADS8325's power-supply voltage is in the range of
4.5V to 5.5V (5V logic level), the ADS8325 can be connected
directly to another 5V CMOS integrated circuit.
Another possibility is that the ADS8325's power-supply volt-
age is in the range of 2.7V to 3.6V. The ADS8325 can be
connected directly to another 3.3V LVCMOS integrated cir-
cuit.
SERIAL INTERFACE
The ADS8325 communicates with microprocessors and other
digital systems via a synchronous 3-wire serial interface, as
illustrated in the Timing Diagram and Timing Characteristics
table. The DCLOCK signal synchronizes the data transfer
with each bit being transmitted on the falling edge of DCLOCK.
Most receiving systems will capture the bitstream on the
rising edge of DCLOCK. However, if the minimum hold time
for D
OUT
is acceptable, the system can use the falling edge
of DCLOCK to capture each bit.
A falling CS signal initiates the conversion and data transfer.
The first 4.5 to 5.0 clock periods of the conversion cycle are
used to sample the input signal. After the fifth falling DCLOCK
edge, D
OUT
is enabled and will output a LOW value for one
clock period. For the next 16 DCLOCK periods, D
OUT
will
output the conversion result, most significant bit first. After
the least significant bit (B0) has been output, subsequent
clocks will repeat the output data, but in a least significant bit
first format.
After the most significant bit (B15) has been repeated, D
OUT
will tri-state. Subsequent clocks will have no effect on the
converter. A new conversion is initiated only when CS has
been taken HIGH and returned LOW.
DATA FORMAT
The output data from the ADS8325 is in Straight Binary
format (see Figure 11). This figure represents the ideal
output code for a given input voltage and does not include
the effects of offset, gain error, or noise.
ADS8325
15
SBAS226A
www.ti.com
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
Straight Binary
Digital Output Code
VZ = VCM = 0V
38.15
V
76.29
V
152.58
V
2.499962V
2.500038V
VMS = VCM + VREF/2 = 2.5V
Unipolar Analog Input Voltage
1LSB = 76.29
V
VCM = 0V
V
REF
= 5V
4.999847V
VFS 1LSB = 4.999924V
VFS = VCM + VREF = 5V
0
1
2
32767
32768
32769
65533
65534
65535
Step
16-BIT
Zero Code
Midscale Code
Full-Scale Code
Straight Binary Output
VZ = 0000H
VMS = 8000H
VFS = 7FFFH
Unipolar Analog Input
VCODE = VCM
VCODE = VCM + VREF/2
VCODE = (VCM + VREF) 1LSB
FIGURE 11. Ideal Conversion Characteristics (Condition: VCM = 0V, VREF = 5V).
POWER DISSIPATION
The architecture of the converter, the semiconductor fabrica-
tion process, and a careful design, allow the ADS8325 to
convert at up to a 100kHz rate while requiring very little
power. However, for the absolute lowest power dissipation,
there are several things to keep in mind.
The power dissipation of the ADS8325 scales directly with
conversion rate. Therefore, the first step to achieving the
lowest power dissipation is to find the lowest conversion rate
that will satisfy the requirements of the system.
In addition, the ADS8325 is in power-down mode under two
conditions: when the conversion is complete and whenever CS
is HIGH (see Timing Diagram). Ideally, each conversion should
occur as quickly as possible, preferably at a 2.4MHz clock rate.
This way, the converter spends the longest possible time in the
power-down mode. This is very important as the converter not
only uses power on each DCLOCK transition (as is typical for
digital CMOS components), but also uses some current for the
analog circuitry, such as the comparator. The analog section
dissipates power continuously until the power-down mode is
entered.
See Figures 12 and 13 for the current consumption of the
ADS8325 versus sample rate. For these graphs, the con-
verter is clocked at 2.4MHz regardless of the sample rate.
CS is held HIGH during the remaining sample period.
There is an important distinction between the power-down
mode that is entered after a conversion is complete and the
full power-down mode that is enabled when CS is HIGH. CS
LOW will shutdown only the analog section. The digital
section is completely shutdown only when CS is HIGH.
Thus, if CS is left LOW at the end of a conversion, and the
converter is continually clocked, the power consumption will
not be as low as when CS is HIGH.
ADS8325
16
SBAS226A
www.ti.com
1000
100
10
1
Current (
A)
10
100
Sample Rate (kHz)
POWER SUPPLY AND REFERENCE
CURRENT vs SAMPLE RATE
T
A
= 25
C
V
DD
= 5.0V
V
REF
= 5.0V
F
CLK
= 2.4MHz
I
REF
I
DD
1000
100
10
1
Current (
A)
10
100
Sample Rate (kHz)
POWER SUPPLY AND REFERENCE
CURRENT vs SAMPLE RATE
T
A
= 25
C
V
DD
= 2.7V
V
REF
= 2.5V
F
CLK
= 2.4MHz
I
REF
I
DD
FIGURE 12. Power-Supply and Reference Current vs Sample
Rate at V
DD
= 5V.
FIGURE 13. Power-Supply and Reference Current vs Sample
Rate at V
DD
= 2.7V.
SHORT CYCLING
Another way to save power is to utilize the CS signal to short
cycle the conversion. Due to the ADS8325 placing the latest
data bit on the D
OUT
line as it is generated, the converter can
easily be short cycled. This term means that the conversion
can be terminated at any time. For example, if only 14 bits of
the conversion result are needed, then the conversion can be
terminated (by pulling CS HIGH ) after the 14th bit has been
clocked out.
This technique can be used to lower the power dissipation (or
to increase the conversion rate) in those applications where
an analog signal is being monitored until some condition
becomes true. For example, if the signal is outside a prede-
termined range, the full 16-bit conversion result may not be
needed. If so, the conversion can be terminated after the first
n bits, where n might be as low as 3 or 4. This results in lower
power dissipation in both the converter and the rest of the
system as they spend more time in power-down mode.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8325 circuitry. This will be particularly
true if the reference voltage is low and/or the conversion rate is
high. At a 100kHz conversion rate, the ADS8325 makes a bit
decision every 416ns. That is, for each subsequent bit decision,
the digital output must be updated with the results of the last bit
decision, the capacitor array appropriately switched and charged,
and the input to the comparator settled to a 16-bit level all within
one clock cycle.
The basic SAR architecture is sensitive to spikes on the power
supply, reference, and ground connections that occur just prior
to latching the comparator output. Thus, during any single
conversion for an n-bit SAR converter, there are n "windows" in
which large external transient voltages can easily affect the
conversion result. Such spikes might originate from switching
power supplies, digital logic, and high-power devices, to name
a few. This particular source of error can be very difficult to track
down if the glitch is almost synchronous to the converter's
DCLOCK signal as the phase difference between the two
changes with time and temperature, causing sporadic
misoperation.
With this in mind, power to the ADS8325 should be clean and
well bypassed. A 0.1
F ceramic bypass capacitor should be
placed as close as possible to the ADS8325 package. In
addition, a 1
F to 10
F capacitor and a 5
or 10
series
resistor may be used to low-pass filter a noisy supply.
The reference should be similarly bypassed with a 47
F capaci-
tor. Again, a series resistor and large capacitor can be used to
low-pass filter the reference voltage. If the reference voltage
originates from an op amp, make sure that the op amp can
drive the bypass capacitor without oscillation (the series resistor
can help in this case). Keep in mind that while the ADS8325
draws very little current from the reference on average, there
are still instantaneous current demands placed on the external
input and reference circuitry.
Texas Instrument's OPA627 op amp provides optimum perfor-
mance for buffering both the signal and reference inputs. For
low-cost, low-voltage, single-supply applications, the OPA2350
or OPA2340 dual op amps are recommended.
Also, keep in mind that the ADS8325 offers no inherent rejection
of noise or voltage variation in regards to the reference input.
This is of particular concern when the reference input is tied to
the power supply. Any noise and ripple from the supply will
appear directly in the digital results. While high-frequency noise
can be filtered out as described in the previous paragraph,
voltage variation due to the line frequency (50Hz or 60Hz) can
be difficult to remove.
The GND pin on the ADS8325 should be placed on a clean
ground point. In many cases, this will be the "analog" ground.
Avoid connecting the GND pin too close to the grounding point
for a microprocessor, microcontroller, or digital signal proces-
sor. If needed, run a ground trace directly from the converter to
the power-supply connection point. The ideal layout will include
an analog ground plane for the converter and associated analog
circuitry.
ADS8325
17
SBAS226A
www.ti.com
APPLICATION CIRCUITS
Figure 14 shows a basic data acquisition system. The
ADS8325 input range is connected to 2.5V or 4.096V. The
5
resistor and 1
F to 10
F capacitor filters the microcon-
troller "noise" on the supply, as well as any high-frequency
noise from the supply itself. The exact values should be
picked such that the filter provides adequate rejection of
noise. Operational amplifiers and voltage reference are con-
nected to analog power supply, AV
DD
.
FIGURE 14. Two Examples of a Basic Data Acquisition System.
+IN
ADS8325
100pF
50
IN
0.1
F
5
CS
D
OUT
DCLOCK
47
F
IN
GND
OUT
0.47
F
REF
V
DD
REF3025
AV
DD
2.7V to 5V
DV
DD
2.7V to 3.6V
V
CM
+ (0V to 2.5V)
GND
GND
DSP
TMS320C6xx
or
TMS320C5xx
or
TMS320C2xx
0.1
F
10
F
10
F
+
+
100
OPA340
OPA340
100pF
50
V
CM
OPA340
1nF
+IN
ADS8325
100pF
50
IN
0.1
F
5
CS
D
OUT
DCLOCK
47
F
IN
GND
OUT
0.47
F
REF
V
DD
REF3040
AV
DD
4.3V to 5.5V
DV
DD
4.5V to 5.5V
0V to 4.096V
GND
GND
Microcontroller
or
DSP
0.1
F
10
F
10
F
+
+
100
OPA340
OPA340
ADS8325
18
SBAS226A
www.ti.com
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,69
0,41
0,25
0,15 NOM
Gage Plane
4073329/C 08/01
4,98
0,25
5
3,05
4,78
2,95
8
4
3,05
2,95
1
0,38
1,07 MAX
Seating Plane
0,65
M
0,08
0
6
0,10
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
PACKAGE DRAWING
ADS8325
19
SBAS226A
www.ti.com
PACKAGE DRAWING (Cont.)
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
MSL Peak Temp
(3)
ADS8325IBDGKR
ACTIVE
MSOP
DGK
8
2500
None
Call TI
Level-1-220C-UNLIM
ADS8325IBDGKT
ACTIVE
MSOP
DGK
8
250
None
Call TI
Level-1-220C-UNLIM
ADS8325IBDRBR
ACTIVE
SON
DRB
8
2500
None
CU SNPB
Level-1-240C-UNLIM
ADS8325IBDRBT
ACTIVE
SON
DRB
8
250
None
CU SNPB
Level-1-240C-UNLIM
ADS8325IDGKR
ACTIVE
MSOP
DGK
8
2500
None
Call TI
Level-1-220C-UNLIM
ADS8325IDGKT
ACTIVE
MSOP
DGK
8
250
None
Call TI
Level-1-220C-UNLIM
ADS8325IDRBR
ACTIVE
SON
DRB
8
2500
None
Call TI
Level-1-240C-UNLIM
ADS8325IDRBT
ACTIVE
SON
DRB
8
250
None
Call TI
Level-1-240C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check
http://www.ti.com/productcontent
for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com
9-Dec-2004
Addendum-Page 1
IMPORTANT NOTICE
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