1
ADS902
Pipeline
A/D
Reference
Ladder
Timing
Circuitry
Error
Correction
Logic
3-State
Outputs
T/H
10-Bit
Digital
Data
CLK
ADS902
LV
DD
OE
Pwrdn
REFB
CM
REFT
IN
ADS902
FEATURES
q
HIGH SNR: 57dB
q
EXTERNAL REFERENCE
q
LOW POWER: 140mW
q
ADJUSTABLE FULL SCALE RANGE
q
POWER DOWN
q
28-PIN SSOP PACKAGE
DESCRIPTION
The ADS902 is a high speed pipelined analog-to-
digital converter that is specified to operate from a
single +5V supply. This converter includes a wide
bandwidth track/hold and a 10-bit quantizer. The per-
formance is specified with a single-ended input range
of 2.25V to 3.25V, or 2V to 4V. The input range is set
by the external reference values.
The ADS902 employs digital error correction tech-
niques to provide excellent differential linearity for
demanding imaging applications. Its low distortion
and high SNR give the extra margin needed for tele-
communications, video and test instrumentation appli-
cations. This high performance A/D converter is speci-
fied to operate at a 30MHz sampling rate. The ADS902
is available in a 28-pin SSOP package.
10-Bit, 30MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
TM
APPLICATIONS
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BATTERY POWERED EQUIPMENT
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CAMCORDERS
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PORTABLE TEST EQUIPMENT
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COMPUTER SCANNERS
q
COMMUNICATIONS
ADS902E
1996 Burr-Brown Corporation
PDS-1359B
Printed in U.S.A., February, 1997
2
ADS902
SPECIFICATIONS
At T
A
= +25
C, V
S
= LV
DD
= +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified.
ADS902E
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Resolution
10
10
Bits
Specified Temperature Range
Ambient Air
40
+85
40
+85
C
ANALOG INPUT
Specified Full Scale Input Range
(1)
1
2
Vp-p
Common-Mode Voltage (Midscale)
+2.75
3
V
Track-Mode Input Bandwidth
350
T
MHz
Analog Input Bias Current
1
T
A
Input Impedance
1.25 || 5
T
M
|| pF
DIGITAL INPUTS
Logic Family
High Input Voltage, V
IH
+2.0
+V
S
T
T
V
Low Input Voltage, V
IL
+0.8
T
V
High Input Current, I
IH
10
T
A
Low Input Current, I
IL
10
T
A
Input Capacitance
5
T
pF
CONVERSION CHARACTERISTICS
Sample Rate
Full
10k
30M
T
T
Samples/s
Data Latency
5
T
Clk Cyc
DYNAMIC CHARACTERISTICS
Differential Linearity Error (Largest Code Error)
f = 500kHz
Full
0.3
1.0
T
T
LSB
f = 12.5MHz
Full
0.3
1.0
T
T
LSB
No Missing Codes
Full
Guaranteed
Guaranteed
Spurious-Free Dynamic Range
f = 12.5MHz (1dBFS
(2)
input)
Full
53
50
58
dB
Integral Nonlinearity Error, f = 500kHz
Full
2.0
4.5
T
T
LSB
Signal-to-Noise Ratio (SNR)
Referred to Sinewave Input Signal
f = 500kHz (1dBFS input)
Full
48
53
dB
f = 12.5MHz (1dBFS input)
Full
48
53
52
57
dB
Maximum SNR
Referred to DC FS Input Signal
f = 9MHz (1dBFS input)
62
66
dB
Signal-to-(Noise + Distortion) (SINAD)
f = 500kHz (1dBFS input)
Full
46
50
dB
f = 3.58MHz (1dBFS input)
Full
45
50
dB
f = 12.5MHz (1dBFS) input)
Full
45
49
47
53
dB
Effective Number of Bits
(3)
, f =12.5MHz
7.8
Bits
Output Noise
Input Grounded
0.2
T
LSB rms
Aperture Delay Time
4
T
ns
Aperture Jitter
7
T
ps rms
DIGITAL OUTPUTS
C
L
= 15pF
Logic Family
Logic Coding
High Output Voltage, V
OH
+2.4
LV
DD
T
T
V
Low Output Voltage, V
OL
+0.4
T
V
3-State Enable Time
OE = L
20
40
T
T
ns
3-State Disable Time
OE = H
18
10
T
T
ns
OE Internal Pull-Down to Gnd
50
T
k
Power-Down Enable Time
Pwrdn = L
133
T
ns
Power-Down Disable Time
Pwrdn = H
18
T
ns
Power-Down Internal Pull-Down to Gnd
50
T
k
ACCURACY
Gain Error
Full
0.5
1
%FS
Input Offset Error
(4)
Full
1.4
T
%FS
Power Supply Rejection (Gain)
V
S
=
5%
Full
42
56
T
T
dB
Power Supply Rejection (Offset)
V
S
=
5%
Full
42
68
T
T
dB
External REFT Voltage Range
Full
REFB +0.5
+3.25
V
S
0.8
T
+4
T
V
External REFB Voltage Range
Full
+0.8
+2.25
REFT 0.5
T
+2
T
V
Reference Input Resistance
REFT to REFB
4
T
k
1Vp-p
2Vp-p
TTL/HCT Compatible CMOS
TTL/HCT Compatible CMOS
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility
for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights
or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life
support devices and/or systems.
TTL/HCT Compatible CMOS
Straight Offset Binary
TTL/HCT Compatible CMOS
Straight Offset Binary
3
ADS902
SPECIFICATIONS
(CONT)
At T
A
= +25
C, V
S
= LV
DD
= +5V, REFB = +2.25V, REFT = +3.25V, Sampling Rate = 30MHz, unless otherwise specified.
ADS902E
PARAMETER
CONDITIONS
TEMP
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
1Vp-p
2Vp-p
POWER SUPPLY REQUIREMENTS
Supply Voltage: +V
S
Full
+4.25
+5.0
+5.25
T
T
T
V
Supply Current: +I
S
Full
28
T
mA
Power Dissipation
Full
140
160
T
T
mW
Power Dissipation (Power Down)
Full
15
T
mW
Thermal Resistance,
JA
28-Pin SSOP
50
T
C/W
T
Specification same as 1Vp-p.
NOTES: (1) The single-ended input range is set by REFB and REFT values. (2) dBFS means dB relative to Full Scale. (3) Effective number of bits (ENOB) is defined
by (SINAD 1.76)/6.02. (4) Offset deviation from ideal negative full scale.
PACKAGE
DRAWING
TEMPERATURE
PRODUCT
PACKAGE
NUMBER
(1)
RANGE
ADS902E
28-Pin SSOP
324
40
C to +85
C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PIN CONFIGURATION
Top VIew
SSOP
PIN
DESIGNATOR
DESCRIPTION
1
+V
S
Analog Supply
2
LV
DD
Output Logic Driver Supply Voltage
3
Bit 10
Data Bit 10 (D0, LSB)
4
Bit 9
Data Bit 9 (D1)
5
Bit 8
Data Bit 8 (D2)
6
Bit 7
Data Bit 7 (D3)
7
Bit 6
Data Bit 6 (D4)
8
Bit 5
Data Bit 5 (D5)
9
Bit 4
Data Bit 4 (D6)
10
Bit 3
Data Bit 3 (D7)
11
Bit 2
Data Bit 2 (D8)
12
Bit 1
Data Bit 1 (D9, MSB)
13
GND
Analog Ground
14
GND
Analog Ground
15
CLK
Convert Clock Input
16
OE
Output Enable, Active Low
17
Pwrdn
Power Down Pin
18
+V
S
Analog Supply
19
GND
Analog Ground
20
GND
Analog Ground
21
LpBy
Positive Ladder Bypass
22
REFT
Top Reference
23
NC
No Connection
24
REFB
Bottom Reference
25
LnBy
Negative Ladder Bypass
26
CM
Common-Mode Voltage Output
27
IN
Analog Input
28
+V
S
Analog Supply
PIN DESCRIPTIONS
PACKAGE/ORDERING INFORMATION
+V
S
, LV
DD ..................................................................................................................................
+6V
Analog Input ............................................................................... +V
S
+0.3V
Logic Input ................................................................................. +V
S
+0.3V
Case Temperature ......................................................................... +100
C
Junction Temperature .................................................................... +150
C
Storage Temperature ..................................................................... +150
C
ABSOLUTE MAXIMUM RATINGS
+V
S
LV
DD
(LSB) Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
(MSB) Bit 1
GND
GND
+V
S
IN
CM
LnBY
REFB
NC
REFT
LpBY
GND
GND
+V
S
Pwrdn
OE
CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS902
4
ADS902
5 Clock Cycles
Data Invalid
t
D
t
L
t
H
t
CONV
N5
N4
N3
N2
N1
N
N+1
N+2
Data Out
Clock
Analog In
N
t
2
N+1
N+2
N+3
N+4
N+5
N+6
N+7
t
1
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
t
CONV
Convert Clock Period
33
100
s
ns
t
L
Clock Pulse Low
15.5
16.5
ns
t
H
Clock Pulse High
15.5
16.5
ns
t
D
Aperture Delay
2
ns
t
1
Data Hold Time, C
L
= 0pF
4
ns
t
2
New Data Delay Time, C
L
= 15pF max
12
ns
TIMING DIAGRAM
5
ADS902
SPECTRAL PERFORMANCE
Frequency (MHz)
0
20
40
60
80
100
120
0
2.5
5.0
7.5
12.5
10.0
15.0
Amplitude (dB)
f
IN
= 12.5MHz
2Vp-p
UNDERSAMPLING
Frequency (MHz)
0
20
40
60
80
100
120
0
2.8
5.6
8.4
11.2
14.0
Amplitude (dB)
f
IN
= 40MHz
f
S
= 28MHz
V
IN
= 1Vp-p
SPECTRAL PERFORMANCE
Frequency (MHz)
0
20
40
60
80
100
0
2.5
5.0
7.5
12.5
10.0
15.0
Amplitude (dB)
f
IN
= 12.5MHz
V
IN
= 1Vp-p
TYPICAL PERFORMANCE CURVES
At T
A
= +25
C, V
S
= LV
DD
= +5V, REFB = +2.25V, REFT = +3.25V, and Sampling Rate = 30MHz, unless otherwise specified.
DIFFERENTIAL LINEARITY ERROR
Output Code
2
1
0
1
2
DLE (LSB)
f
IN
= 12.5MHz
2Vp-p
0
256
512
768
1024
DIFFERENTIAL LINEARITY ERROR
Output Code
2
1
0
1
2
DLE (LSB)
f
IN
= 12.5MHz
V
IN
= 1Vp-p
0
256
512
768
1024
FREQUENCY SPECTRUM
Frequency (MHz)
0
10
20
30
40
50
60
70
80
90
100
0
2.50
5.00
7.50
10.00
Magnitude (dBFSR)
f
1
= 3.5MHz at 7dB
f
2
= 3.6MHz at 7dB
2f
1
f
2
= 69.5dBFS
2f
2
f
1
= 68.4dBFS
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