DAC7528
CMOS Dual 8-Bit Buffered Multiplying
DIGITAL-TO-ANALOG CONVERTER
DESCRIPTION
The DAC7528 contains two, 8-bit multiplying digital-
to-analog converters (DACs). Separate on-chip latches
hold the input data for each DAC to allow easy
interface to microprocessors.
Each DAC operates independently with separate refer-
ence input pins and internal feedback resistors. Excel-
lent converter-to-converter matching is maintained.
The DAC7528 operates from a single +5V power
supply. The inputs are TTL-compatible. Package
options include 20-pin plastic DIP and SOIC.
International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
FEATURES
q
DOUBLE BUFFERED DATA LATCHES
q
SINGLE 5V SUPPLY OPERATION
q
1/2 LSB LINEARITY
q
FOUR-QUADRANT MULTIPLICATION
q
DACs MATCHED TO 1%
APPLICATIONS
q
DIGITALLY CONTROLLED FILTERS
q
DISK DRIVES
q
AUTO CALIBRATION
q
MOTOR CONTROL SYSTEMS
q
PROGRAMMABLE GAIN/ATTENUATION
q
X-Y GRAPHICS
DAC A
DAC B
7
6
15
16
5
14
17
Latch
Latch
DAC7528
19
20
2
3
1
V
DD
DB0 (LSB)
DB7 (MSB)
DAC A/
DAC B
WR
CS
DGND
R
FB A
OUT A
AGND
R
FB B
OUT B
18
V
REF B
V
REF
A
4
Input
Buffer
Control
Logic
Data
Inputs
1993 Burr-Brown Corporation
PDS-1219A
Printed in U.S.A. June, 1994
DAC7528
2
SPECIFICATIONS
ELECTRICAL
At V
DD
= +5V; V
REFA, B
= + 10V; I
OUT
= GND = 0V: T = Full Temperature Range specification under Absolute Maximum Ratings unless otherwise noted.
DAC7528P, U
DAC7528PB, UB
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DC ACCURACY
(1)
Resolution
N
8
8
Bits
Relative Accuracy
INL
1
1/2
LSB
Differential Nonlinearity
DNL
Guaranteed Monolithic Over Temp
1
1/2
LSB
FS Gain Error
(2)
T
A
= +25
C
2
1
LSB
T
A
= T
MIN
to T
MAX
4
2
LSB
Gain Tempco
(2)(3)
2
35
ppm/
C
Supply Rejection
PSR
V
DD
=
5%, T
A
= +25
C
0.001
0.01
%FSR/%
T
A
= T
MIN
to T
MAX
0.001
0.01
%FSR/%
Output Leakage Current (OUTA)
DACA = 00
16,
T
A
= +25
C
50
nA
T
A
= T
MIN
to T
MAX
200
nA
Output Leakage Current (OUTB)
DACB = 00
16,
T
A
= +25
C
50
nA
T
A
= T
MIN
to T
MAX
200
nA
REFERENCE INPUT
Input Resistance
(V
REFA
, V
REFB
)
8
10
15
k
Input Resistance Match
(V
REFA
, V
REFB
)
1
%
DYNAMIC PERFORMANCE
(4)
Output Current Settling Time to 1/2 LSB
Enable Pins Low T
A
= +25
C
180
ns
Load = 100
/13pF, T
A
= T
MIN
to T
MAX
200
ns
Digital-to-Analog Propagation Delay
Enable Pins Low T
A
= +25
C
80
ns
to 90% of Output
Load = 100
/13pF, T
A
= T
MIN
to T
MAX
100
ns
Digital-to-Analog Impulse
125
nVs
AC Feedthrough
V
REFA
= 20Vpp Sinewave, T
A
= +25
C
70
dB
(V
REFA
to OUTA)
100kHz,V
REFB
= 0V, T
A
= T
MIN
to T
MAX
65
dB
AC Feedthrough
V
REFA
= 20Vpp Sinewave, T
A
= +25
C
70
dB
(V
REFB
to OUTB)
100kHz, V
REFB
= 0V, T
A
= T
MIN
to T
MAX
65
dB
Channel-to-Channel Isolation
V
REFA
= 20Vpp Sinewave, 100kHz,
90
dB
(V
REFA
to OUTB)
V
REFB
= 0V, Both DACs = FF
16
Channel-to-Channel Isolation
V
REFB
= 20Vpp Sinewave 100kHz,
90
dB
(V
REFB
to OUTA)
V
REFA
= 0V, Both DACs = FF
16
Digital Crosstalk
Measured With Code Transition 00
16
to FF
16
30
nVs
Harmonic Distortion
THD
V
IN
= 6Vrms at 1kHz
85
dB
ANALOG OUTPUTS
(4)
OUTA capacitance
C
OUTA
DAC = 00
16
50
pF
DAC = FF
16
120
pF
OUTB capacitance
C
OUTB
DAC = 00
16
50
pF
DAC = FF
16
120
pF
DIGITAL INPUTS
Input High Voltage
V
IH
2.4
V
Input Low Voltage
V
IL
0.8
V
Input Current
I
IN
T
A
= +25
C
1
A
T
A
= T
MIN
to T
MAX
10
A
Input Capacitance
(4)
C
IN
All Digital Inputs
10
pF
POWER REQUIREMENTS
Supply Current
I
DD
Digital Inputs = V
IH
or V
IL
, T
A
= +25
C
1
mA
T
A
= T
MIN
to T
MAX
1
mA
Digital Inputs = 0V or V
DD
, T
A
= +25
C
100
A
T
A
= T
MIN
to T
MAX
500
A
SWITCHING CHARACTERISTICS (100% tested) See Timing Diagram
Chip Select To Write Setup Time
t
CS
T
A
= +25
C
200
ns
T
A
= T
MIN
to T
MAX
230
ns
Chip Select To Write Hold Time
t
CH
T
A
= +25
C
20
ns
T
A
= T
MIN
to T
MAX
30
ns
DAC Select To Write Setup Time
t
AS
T
A
= +25
C
200
ns
T
A
= T
MIN
to T
MAX
230
ns
DAC Select To Write Hold Time
t
AH
T
A
= +25
C
20
ns
T
A
= T
MIN
to T
MAX
30
ns
Write Pulse Width
t
WR
T
A
= +25
C
180
ns
T
A
= T
MIN
to T
MAX
200
ns
Data Setup Time
t
DS
T
A
= +25
C
110
ns
T
A
= T
MIN
to T
MAX
130
ns
Data Hold Time
t
DH
T
A
= +25
C
0
ns
NOTES: (1) Specifications apply to both DACs. (2) Gain error is measured using internal feedback resistor. Full Scale Range (FSR) = V
REF
. (3) Guaranteed, but
not tested. (4) These characteristics are for design guidance only and are not subject to test.
DAC7528
3
DICE INFORMATION
PAD FUNCTION
PAD FUNCTION
PAD FUNCTION
1
V
DD
8
R
FB A
15
DB4
2
V
REF B
9
V
REF B
16
DB3
3
R
FB B
10
DGND
17
DB2
4
OUTB
11
DAC A/DAC B
18
DB1
5
AGNDB
12
DB7
19
DB0
6
AGNDA
13
DB6
20
CS
7
OUTA
14
DB5
21
WR
MECHANICAL INFORMATION
MILS (0.001")
MILLIMETERS
Die Size
104 x 124
2.6 x 3.1
Die Thickness
20
3
0.51
0.08
Min. Pad Size
4 x 4
0.10 x 0.10
DAC7528 TOPOGRAPHY
8
7
6
5
4
3
2
1
21
19
20
18
17
16
15
14
13
12
11
10
9
PACKAGE INFORMATION
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER
(1)
DAC7528P
20-Pin Plastic DIP
222
DAC7528PB
20-Pin Plastic DIP
222
DAC7528U
20-Pin SOIC
221
DAC7528UB
20-Pin SOIC
221
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
ORDERING INFORMATION
MODEL
INL
PACKAGE
TEMPERATURE RANGE
DAC7528P
1LSB
20-Pin Plastic DIP
40
C to +85
C
DAC7528PB
1/2LSB
20-Pin Plastic DIP
40
C to +85
C
DAC7528U
1LSB
20-Pin SOIC
40
C to +85
C
DAC7528UB
1/2LSB
20-Pin SOIC
40
C to +85
C
PIN CONFIGURATION
Top View
DIP/SOIC
DAC7528
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
AGND
OUT A
R
FB
A
V
REF
A
DGND
DAC A/DAC B
(MSB) DB7
DB6
DB5
DB4
OUT B
R
FB
B
V
REF B
V
DD
WR
CS
DB0 (LSB)
DB1
DB2
DB3
ELECTRICAL, (DICE)
At V
DD
= +5V; V
REFA, B
= +10V; I
OUT
= GND = 0V: T = Full Temperature Range specification under Absolute Maximum Ratings unless otherwise noted.
DAC7528AD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
(1)
Resolution
N
8
Bits
Relative Accuracy
INL
1
LSB
Differential Nonlinearity
DNL
Guaranteed Monolithic Over Temp
1
LSB
FS Gain Error
(2)
T
A
= +25
C
2
LSB
T
A
= T
MIN
to T
MAX
4
LSB
Gain Tempco
(2, 3)
2
35
ppm/
C
Supply Rejection
PSR
V
DD
=
5%, T
A
= +25
C
0.001
0.01
%FSR/%
T
A
= T
MIN
to T
MAX
0.001
0.01
%FSR/%
Output Leakage Current (OUTA)
DACA = 00
16
T
A
= +25
C
50
nA
T
A
= T
MIN
to T
MAX
200
nA
Output Leakage Current (OUTB)
DACB = 00
16
T
A
= +25
C
50
nA
T
A
= T
MIN
to T
MAX
200
nA
REFERENCE INPUT
Input Resistance
(V
REF A
, V
REF B
)
8
10
15
k
Input Resistance Match
(V
REF A
, V
REF B
)
1
%
NOTES: (1) Specifications apply to both DACs. (2) Gain error is measured using internal feedback resistor. Full Scale Range (FSR) = V
REF
. (3) Guaranteed, but not
tested. (4) These characteristics are for design guidance only and are not subject to test.
DAC7528
4
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degrada-
tion to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet
published specifications.
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND ................................................................................. 0V, +7V
V
REFA, B
to GND ................................................................................
25V
R
FA,B
to GND ...................................................................................
25V
Digital Input Voltage Range ................................................ 0.3V to V
DD
Output Voltage (pins 2, 20) ................................................ 0.3V to V
DD
Operating Temperature Range U,P ................................ 40
C to +85
C
DICE ............................... 0
C to +70
C
Junction Temperature .................................................................. +150
C
Storage Temperature ..................................................... 60
C to +150
C
Lead Temperature (soldering, 10s) ............................................. +300
C
JA
U package ........................................................................ 105
C/W
P package ........................................................................... 85
C/W
JC
U package ......................................................................... 60
C/W
P package .......................................................................... 35
C/W
NOTES:
JA
is specified for worst case mounting conditions, i.e.,
JA
is
specified for device in socket for PDIP package.
CAUTION: (1) Do not apply voltages higher than V
DD
or less than GND
potential on any terminal except V
REFA, B
(pins 4 and 18) and R
FBA, B
(pins
3 and 19). (2) The digital control inputs are zener-protected: however,
permanent damage may occur on unprotected units from high-energy
electrostatic fields. Keep units in conductive foam at all times until ready
to use. (3) Use proper antistatic handling procedures. (4) Absolute
Maximum Ratings apply to both packaged devices and DICE. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device.
TYPICAL PERFORMANCE CURVES
At V
DD
= +5V; V
REFA,B
= +10V; I
OUT
= GND = 0V: T = Full Temperature Range Specification under Absolute Maximum Ratings unless otherwise noted.
WRITE CYCLE TIMING DIAGRAM
t
DS
V
IH
V
IL
Data
In Stable
V
DD
0
t
WR
t
AS
t
AH
V
DD
0
V
DD
0
Data In
(DB0-DB7)
WR
DAC A/DAC B
t
CS
t
CH
V
DD
0
CS
t
DH
NOTE: All input signal rise and fall times are measured from 10% to 90%
of V
DD
. V
DD
= +5V, t
r
= t
f
= 20ns; V
DD
= +15V, t
r
= t
f
= 40ns. Timing
measurement reference level is (V
IH
+ V
IL
)/2.
Digital Inputs: All digital inputs of the DAC7528 incorpo-
rate on-chip ESD protection circuitry. This protection is
designed and has been tested to withstand five 2500V
positive and negative discharges (100pF in series with 1500
)
applied to each digital input.
Analog Pins: Each analog pin has been tested to Burr-
Brown's analog ESD test consisting of five 1000V positive
and negative discharges (100pF in series with 1500
) ap-
plied to each pin. R
FB A
, V
REF A
, R
FB B
, and V
REF B
show
some sensitivity.
MODE SELECTION TABLE
DAC A/DAC B
CS
WR
DAC A
DAC B
L
L
L
WRITE
HOLD
H
L
L
HOLD
WRITE
X
H
X
HOLD
HOLD
X
X
H
HOLD
HOLD
SUPPLY CURRENT vs DIGITAL INPUT VOLTAGE
0
1.0
2.0
3.0
4.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
V
DD
= +5V
V
IN
(V)
I
DD
(mA)
5
DAC7528 GAIN TC
4
3
2
1
0
1
2
3
4
5
40
20
0
20
40
60
80
100
Temperature (C)
Gain TC (ppm/C)
DAC7528
5
DISCUSSION OF
SPECIFICATIONS
RELATIVE ACCURACY
This term, also known as end point linearity or integral
linearity, describes the transfer function of analog output to
digital input code. Relative accuracy describes the deviation
from a straight line, after zero and full scale errors have been
adjusted to zero.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is the deviation from an ideal 1LSB
change in the output when the input code changes by 1LSB.
A differential nonlinearity specification of 1LSB maximum
guarantees monotonicity.
GAIN ERROR
Gain error is the difference between the full-scale DAC
output and the ideal value. The ideal full scale output value
for the DAC7528 is (255/256)V
REF
. Gain error may be
adjusted to zero using external trims as shown in Figure 4.
OUTPUT LEAKAGE CURRENT
The current which appears at I
OUT A
and I
OUT B
with the
DAC loaded with all zeros.
OUTPUT CAPACITANCE
The parasitic capacitance measured from I
OUT A
or I
OUT B
to
AGND.
CHANNEL-TO-CHANNEL ISOLATION
The AC output error due to capacitive coupling from DAC
A to DAC B or DAC B to DAC A.
AC FEEDTHROUGH ERROR
The AC output error due to capacitive coupling from V
REF
to I
OUT
with the DAC loaded with all zeros.
OUTPUT CURRENT SETTLING TIME
The time required for the output current to settle to within
0.195% of final value for a full scale step.
DIGITAL-TO-ANALOG IMPULSE
The integrated area of the glitch pulse measured in nanovolt-
seconds. The key contributor to digital-to-analog glitch is
charge injected by digital logic switching transients.
DIGITAL CROSSTALK
Glitch impulse measured at the output of one DAC but
caused by a full scale transition on the other DAC. The
integrated area of the glitch pulse is measured in nanovolt-
seconds.
CIRCUIT DESCRIPTION
Figure 1 shows a simplified schematic of one half of a
DAC7528. The current from the V
REF
A
pin is switched
between I
OUT A
and AGND by 8 single-pole double-throw
CMOS switches. This maintains a constant current in each
leg of the ladder regardless of the input code. The input
resistance at V
REF A
is therefore constant and can be driven
by either a voltage or current, AC or DC, positive or
negative polarity, and have a voltage range up to
20V.
A CMOS switch transistor, included in series with the ladder
terminating resistor and in series with the feedback resistor,
R
FB A
, compensates for the temperature drift of the ON
resistance of the ladder switches.
Figure 2 shows an equivalent circuit for DAC A. C
OUT
is the
output capacitance due to the N-channel switches and varies
from about 30pF to 70pF with digital input code. The current
source I
LKG
is the combination of surface and junction
leakages to the substrate. I
LKG
approximately doubles every
10
C. R
O
is the equivalent output resistance of the D/A and
it varies with input code.
OUT A
I
AGND
FB A
R
2R
2R
2R
2R
2R
R
R
R
V
REF A
DB7
(MSB)
DB6
DB5
DB0
(LSB)
R
FIGURE 1. Equivalent Circuit for DAC A.
FIGURE 2. Simplified Circuit Diagram for DAC A.
FB A
R
OUT A
I
V
REF A
I
LKG
R
OUT
C
O
R
AGND
D
IN
256
x
V
REF
R
R
INSTALLATION
ESD PROTECTION
All digital inputs of the DAC7528 incorporate on-chip ESD
protection circuitry. This protection is designed to withstand
2.5kV (using the Human Body Model, 100pF and 1500
).
However, industry standard ESD protection methods should
be used when handling or storing these components. When
not in use, devices should be stored in conductive foam or
rails. The foam or rails should be discharged to the destina-
tion socket potential before devices are removed.
DAC7528
6
POWER SUPPLY CONNECTIONS
The DAC7528 is designed to operate on V
DD
= +5V +10%.
For optimum performance and noise rejection, power supply
decoupling capacitors C
D
should be added as shown in the
application circuits. These capacitors (1
F tantalum recom-
mended) should be located close to the D/A. AGND and
DGND should be connected together at one point only, pre-
ferably at the power supply ground point. Separate returns
minimize current flow in low-level signal paths if properly
connected. Output op amp analog common (+ input) should
be connected as near to the AGND pin of the DAC7528 as
possible.
WIRING PRECAUTIONS
To minimize AC feedthrough when designing a PC board,
care should be taken to minimize capacitive coupling be-
tween the V
REF
lines and the I
OUT
lines. Similarly, capacitive
coupling between DACs may compromise the channel-to-
channel isolation. Coupling from any of the digital control or
data lines might degrade the glitch and digital crosstalk
performance. Solder the DAC7528 directly into the
PC
board without a socket. Sockets add parasitic capacitance
(which can degrade AC performance).
AMPLIFIER OFFSET VOLTAGE
The output amplifier used with the DAC7528 should have
low input offset voltage to preserve the transfer function
linearity. The voltage output of the amplifier has an error
component which is the offset voltage of the op amp multi-
plied by the "noise gain" of the circuit. This "noise gain" is
equal to (R
F
/ R
O
+ 1) where R
O
is the output impedance of
the D/A I
OUT
terminal and R
F
is the feedback network
impedance. The nonlinearity occurs due to the output im-
pedance varying with code. If the 0 code case is excluded
(where R
O
= infinity), the R
O
will vary from R to 3R
providing a "noise gain" variation between 4/3 and 2. In
addition, the variation of R
O
is nonlinear with code, and the
largest steps in R
O
occur at major code transitions where the
worst differential nonlinearity is also likely to be experi-
enced. The nonlinearity seen at the amplifier output is
2VOS 4V
OS
/3 = 2V
OS
/3. Thus, to maintain good
nonlinearity the op amp offset should be much less than
1/2LSB.
UNIPOLAR CONFIGURATION
Figure 3 shows DAC7528 in a typical unipolar (two-quad-
rant) multiplying configuration. The analog output values
versus digital input code are listed in Table I. The opera-
tional amplifiers used in this circuit can be single amplifiers
such as the OPA602, or a dual amplifier such as the OPA2107.
C1 and C2 provide phase compensation to minimize settling
time and overshoot when using a high speed operational
FIGURE 3. Unipolar Configuration 2 Quadrant Multiplica-
tion.
DAC A
I
OUT A
DAC B
I
OUT B
R
FB B
R
FB A
C1
10pF
C2
10pF
DAC7528
V
OUT A
V
OUT B
+
+
A1
A2
DGND
V
REF B
V
REF A
V
DD
+5V
C
D
A1, A2 OPA602 or 1/2 OPA2107.
+
1F
AGND
V
OUT
=
D
IN
256
V
REF
amplifier.
If an application requires the D/A to have zero gain error, the
circuit shown in Figure 4 may be used. Resistors R2 and R4
induce a positive gain error greater than worst-case initial
negative gain error. Trim resistors R1 and R3 provide a
variable negative gain error and have sufficient trim range to
correct for the worst-case initial positive gain error plus the
error produced by R2 and R4.
BIPOLAR CONFIGURATION
Figure 5 shows the DAC7528 in a typical bipolar (four-
quadrant) multiplying configuration. The analog output val-
ues versus digital input code are listed in Table II.
The operational amplifiers used in this circuit can be single
amplifiers such as the OPA602, a dual amplifier such as the
OPA2107, or a quad amplifier like the OPA404. C1 and C2
provide phase compensation to minimize settling time and
overshoot when using a high speed operational amplifier.
The bipolar offset resistors R1R3 and R4R6 should be
ratio-matched to 0.195% to ensure the specified gain error
performance.
DAC7528
7
FIGURE 4. Unipolar Configuration with Gain Trim.
R
100
3
REF B
R
2
47
R
4
47
DAC A
I
OUT A
DAC B
I
OUT B
R
FB B
R
FB A
C1 10pF
C2 10pF
DAC7528
V
OUT A
V
OUT B
+
+
A1
A2
DGND
V
DD
+5V
C
D
A1, A2 OPA602 or 1/2 OPA2107.
+
1F
AGND
V
IN A
R
100
1
REF A
V
V
IN B
V
R
3
10k
1
C
10pF
DAC A
DAC B
R
10k
5
DAC7528
DGND
V
REF A
V
DD
+5V
C
D
2
R
6
20k
R
2
20k
R
10k
C
10pF
V
OUT A
V
OUT B
A1
A3
A1A4, OPA602 or 1/2 OPA2107.
+
A2
+
A4
5
R
1
20k
R
4
20k
REF B
V
I
OUT B
R
FB B
+
I
OUT A
R
FB A
+
1F
+
AGND
FIGURE 5. Bipolar Configuration 4 Quadrant Multiplication.
APPLICATION INFORMATION
DATA INPUT
ANALOG OUTPUT
MSB LSB
1111 1111
V
REF
(255/256)
1000 0000
V
REF
(255/256) = 1/2V
REF
0000 0001
V
REF
(1/256)
0000 0000
0V
TABLE I. Unipolar Output Code.
DATA INPUT
ANALOG OUTPUT
MSB LSB
1111 1111
+V
REF
(127/128)
1000 0001
+V
REF
(1/128)
1000 0000
0V
0111 1111
V
REF
(1/128)
0000 0000
V
REF
(127/128)
TABLE II. Bipolar Output Code.
DAC7528
8
APPLICATIONS CIRCUIT: 8-BIT PLUS SIGN DAC
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
1
C
10pF
I
OUT A
DAC A
DAC B
R
FB A
DAC7528
DGND
V
DD
+5V
A1
A1 OPA602 or 1/2 OPA2107.
REF102
10V
9 Bits
V
REF B
+15V
V
REF A
R
R
R
AGND
+10V
I
OUT B
R
FB B
2
C
10pF
A2
R
C
D
INA105
2
4
6
1F
2
3
6
1
The DACs are loaded with same 8-bit word,
except that one code is inverted first.
If sign bit = 1; invert DAC B's data.
If sign bit = 0; invert DAC A's data.
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