Document Outline
- FEATURES
- DESCRIPTION
- ELECTRICAL CHARACTERISTICS
- PIN CONFIGURATION
- TRUTH TABLES
- ABSOLUTE MAXIMUM RATINGS(1)
- PACKAGE/ORDERING INFORMATION
- TYPICAL PERFORMANCE CURVES
- DISCUSSION OF SPECIFICATIONS
- DC CHARACTERISTICS
- Single-Ended Multiplexer Static Accuracy
- Input Offset Voltage
- Differential Multiplexer Static Accuracy
- Load (Output Device) Characteristics
- SOURCE CHARACTERISTICS
- DYNAMIC CHARACTERISTICS
- Settling Time
- Switching Time
- Crosstalk
- Common-Mode Rejection (MPC507A Only)
- SWITCHING WAVEFORMS
- PERFORMANCE CHARACTERISTICS AND TEST CIRCUITS
- INSTALLATION AND OPERATING INSTRUCTIONS
- CHANNEL EXPANSION
- Single-Ended Multiplexer (MPC506A)
- Differential Multiplexer (MPC507A)
- Single-Node Expansion
- Two-Tier Expansion
- Single vs Multitiered Channel Expansion
MPC506A
MPC507A
SBFS018A JANUARY 1988 REVISED OCTOBER 2003
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1988-2003, Texas Instruments Incorporated
Single-Ended 16-Channel/Differential 8-Channel
CMOS ANALOG MULTIPLEXERS
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
FEATURES
q
ANALOG OVERVOLTAGE PROTECTION: 70V
PP
q
NO CHANNEL INTERACTION DURING
OVERVOLTAGE
q
BREAK-BEFORE-MAKE SWITCHING
q
ANALOG SIGNAL RANGE:
15V
q
STANDBY POWER: 7.5mW typ
q
TRUE SECOND SOURCE
Level
Shift
1k
1k
1k
Overvoltage
Clamp and
Signal
Isolation
5V
Ref
Decoder/
Driver
NOTE: (1) Digital
Input Protection.
In 1
In 2
In 16
V
REF
MPC506A
A
0
A
1
A
2
A
3
EN
(1)
Out
(1)
(1) (1)
(1)
Level
Shift
1k
1k
1k
Overvoltage
Clamp and
Signal
Isolation
5V
Ref
Decoder/
Driver
NOTE: (1) Digital
Input Protection.
In 1A
In 1B
In 8B
V
REF
MPC507A
A
0
A
1
A
2
EN
Out A
1k
In 8A
Out B
(1) (1)
(1)
(1)
FUNCTIONAL DIAGRAMS
DESCRIPTION
The MPC506A is a 16-channel single-ended analog multi-
plexer, and the MPC507A is an 8-channel differential multi-
plexer.
The MPC506A and MPC507A multiplexers have input over-
voltage protection. Analog input voltages may exceed either
power supply voltage without damaging the device or dis-
turbing the signal path of other channels. The protection
circuitry assures that signal fidelity is maintained even under
fault conditions that would destroy other multiplexers. Analog
inputs can withstand 70V
PP
signal levels and standard ESD
tests. Signal sources are protected from short circuits should
multiplexer power loss occur; each input presents a 1k
resistance under this condition. Digital inputs can also sus-
tain continuous faults up to 4V greater than either supply
voltage.
These features make the MPC506A and MPC507A ideal for
use in systems where the analog signals originate from
external equipment or separately powered sources.
The MPC506A and MPC507A are fabricated with Burr-
Brown's dielectrically isolated CMOS technology. The multi-
plexers are available in plastic DIP and plastic SOIC pack-
ages. Temperature range is 40/+85
C.
MPC
506
MPC
507
MPC506A, MPC507A
2
SBFS018A
www.ti.com
ELECTRICAL CHARACTERISTICS
Supplies = +15V, 15V; V
REF
(Pin 13) = Open; V
AH
(Logic Level High) = +4.0V; V
AL
(Logic Level Low) = +0.8V unless otherwise specified.
MPC506A/MPC507A
PARAMETER
TEMP
MIN
TYP
MAX
UNITS
ANALOG CHANNEL CHARACTERISTICS
V
S
, Analog Signal Range
Full
15
+15
V
R
ON
, On Resistance
(1)
+25
C
1.3
1.5
k
Full
1.5
1.8
k
I
S
(OFF), Off Input Leakage Current
+25
C
0.5
nA
Full
10
nA
I
D
(OFF), Off Output Leakage Current
+25
C
0.2
nA
MPC506A
Full
5
nA
MPC507A
Full
5
nA
I
D
(OFF) with Input Overvoltage Applied
(2)
+25
C
2
A
I
D
(ON), On Channel Leakage Current
+25
C
2
nA
MPC506A
Full
10
nA
MPC507A
Full
10
nA
I
DIFF
Differential Off Output Leakage Current
(MPC507A Only)
Full
10
nA
DIGITAL INPUT CHARACTERISTICS
V
AL
, Input Low Threshold
Full
0.8
V
V
AH
, Input High Threshold
(3)
Full
4.0
V
V
AL
, MOS Drive
(4)
+25
C
0.8
V
V
AH
, MOS Drive
(4)
+25
C
6.0
V
I
A
, Input Leakage Current (High or Low)
(5)
Full
1.0
A
SWITCHING CHARACTERISTICS
t
A
, Access Time
+25
C
0.3
s
Full
0.6
s
t
OPEN
, Break-Before-Make Delay
+25
C
25
80
ns
t
ON
(EN), Enable Delay (ON)
+25
C
200
ns
Full
500
ns
t
OFF
(EN), Enable Delay (OFF)
+25
C
250
ns
Full
500
ns
Settling Time (0.1%)
+25
C
1.2
s
(0.01%)
+25
C
3.5
s
"OFF Isolation"
(6)
+25
C
50
68
dB
C
S
(OFF), Channel Input Capacitance
+25
C
5
pF
C
D
(OFF), Channel Output Capacitance: MPC506A
+25
C
50
pF
MPC507A
+25
C
25
pF
C
A
, Digital Input Capacitance
25
C
5
pF
C
DS
, (OFF), Input to Output Capacitance
+25
C
0.1
pF
POWER REQUIREMENTS
P
D
, Power Dissipation
Full
7.5
mW
I+, Current Pin 1
(7)
Full
0.7
1.5
mA
I, Current Pin 27
(7)
Full
5
20
A
NOTES: (1) V
OUT
=
10V, I
OUT
= 100
A. (2) Analog overvoltage =
33V. (3) To drive from DTL/TTL circuits. 1k
pull-up resistors to +5.0V supply are recommended.
(4) V
REF
= +10V. (5) Digital input leakage is primarily due to the clamp diodes. Typical leakage is less than 1nA at 25
C. (6) V
EN
= 0.8V, R
L
= 1k
,
C
L
= 15pF, V
S
= 7Vrms, f = 100kHz. Worst-case isolation occurs on channel 8 due to proximity of the output pins. (7) V
EN
, V
A
= 0V or 4.0V.
MPC506A, MPC507A
3
SBFS018A
www.ti.com
PIN CONFIGURATION
MPC507A
"ON"
A
3
A
2
A
1
A
0
EN
CHANNEL
X
X
X
X
L
None
L
L
L
L
H
1
L
L
L
H
H
2
L
L
H
L
H
3
L
L
H
H
H
4
L
H
L
L
H
5
L
H
L
H
H
6
L
H
H
L
H
7
L
H
H
H
H
8
H
L
L
L
H
9
H
L
L
H
H
10
H
L
H
L
H
11
H
L
H
H
H
12
H
H
L
L
H
13
H
H
L
H
H
14
H
H
H
L
H
15
H
H
H
H
H
16
"ON"
CHANNEL
A
2
A
1
A
0
EN
PAIR
X
X
X
L
None
L
L
L
H
1
L
L
H
H
2
L
H
L
H
3
L
H
H
H
4
H
L
L
H
5
H
L
H
H
6
H
H
L
H
7
H
H
H
H
8
MPC506A
TRUTH TABLES
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
9
10
11
12
13
14
20
19
18
17
16
15
+V
SUPPLY
NC
NC
In 16
In 15
In 14
In 13
In 12
In 11
In 10
In 9
Ground
V
REF
Address A
3
Out
V
SUPPLY
In 8
In 7
In 6
In 5
In 4
In 3
In 2
In 1
Enable
Address A
0
Address A
1
Address A
2
Top View
MPC506A (Plastic)
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
9
10
11
12
13
14
20
19
18
17
16
15
+V
SUPPLY
Out B
NC
In 8B
In 7B
In 6B
In 5B
In 4B
In 3B
In 2B
In 1B
Ground
V
REF
NC
Out A
V
SUPPLY
In 8A
In 7A
In 6A
In 5A
In 4A
In 3A
In 2A
In 1A
Enable
Address A
0
Address A
1
Address A
2
Top View
MPC507A (Plastic)
MPC506A, MPC507A
4
SBFS018A
www.ti.com
Voltage between supply pins ............................................................... 44V
V
REF
to ground, V+ to ground ............................................................... 22V
V to ground ........................................................................................ 25V
Digital input overvoltage:
V
EN
, V
A
: V
SUPPLY
(+) ............................................................................ +4V
V
SUPPLY
() ............................................................................ 4V
or 20mA, whichever occurs first.
Analog input overvoltage:
V
S
: V
SUPPLY
(+) .................................................................................. +20V
V
SUPPLY
() .................................................................................. 20V
Continuous current, S or D ............................................................... 20mA
Peak current, S or D
(pulsed at 1ms, 10% duty cycle max) ............................................ 40mA
Power dissipation* ............................................................................. 2.0W
Operating temperature range ........................................... 40
C to +85
C
Storage temperature range ............................................. 65
C to +150
C
*Derate 20.0mW/
C above T
A
= 70
NOTE: (1) Absolute maximum ratings are limiting values, applied individu-
ally, beyond which the serviceability of the circuit may be impaired. Func-
tional operation under any of these conditions is not necessarily implied.
ABSOLUTE MAXIMUM RATINGS
(1)
TYPICAL PERFORMANCE CURVES
T
A
= +25
C unless otherwise noted.
SETTLING TIME vs
SOURCE RESISTANCE FOR 20V STEP CHANGE
1k
100
10
1
0.1
0.01
0.1
1
10
100
Source Resistance (k
)
Settling Time (s)
To 0.01%
To 0.1%
COMBINED CMR vs
FREQUENCY MPC507A AND INA110
120
100
80
60
40
20
0
1
10
100
1k
10k
Frequency (Hz)
Common-Mode Rejection (dB)
G = 500
G = 100
G = 10
CROSSTALK vs SIGNAL FREQUENCY
1
0.1
0.01
0.001
0.0001
1
10
100
1k
10k
Signal Frequency (Hz)
Crosstalk (% of Off Channel Signal)
R
s
= 100k
R
s
= 1k
R
s
= 100
R
s
= 10k
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum located at the end of this
data sheet.
MPC506A, MPC507A
5
SBFS018A
www.ti.com
DISCUSSION OF
SPECIFICATIONS
DC CHARACTERISTICS
The static or dc transfer accuracy of transmitting the multi-
plexer input voltage to the output depends on the channel
ON resistance (R
ON
), the load impedance, the source imped-
ance, the load bias current and the multiplexer leakage
current.
Single-Ended Multiplexer Static Accuracy
The major contributors to static transfer accuracy for single-
ended multiplexers are:
Source resistance loading error
Multiplexer ON resistance error
dc offset error caused by both load bias current and
multiplexer leakage current.
Resistive Loading Errors
The source and load impedances will determine the input
resistive loading errors. To minimize these errors:
Keep loading impedance as high as possible. This mini-
mizes the resistive loading effects of the source resistance
and multiplexer ON resistance. As a guideline, load
impedance of 10
8
or greater will keep resistive loading
errors to 0.002% or less for 1000
source impedances. A
10
6
load impedance will increase source loading error
to 0.2% or more.
Use sources with impedances as low as possible. A
1000
source resistance will present less than 0.001%
loading error and 10k
source resistance will increase
source loading error to 0.01% with a 10
8
load impedance.
Input resistive loading errors are determined by the follow-
ing relationship (see Figure 1).
Input Offset Voltage
Bias current generates an input OFFSET voltage as a result
of the IR drop across the multiplexer ON resistance and
source resistance. A load bias current of 10nA will generate
an offset voltage of 20
V if a 1k
source is used. In general,
for the MPC506A, the OFFSET voltage at the output is
determined by:
V
OFFSET
= (I
B
+ I
L
) (R
ON
+ R
S
)
where I
B
= Bias current of device multiplexer is driving
I
L
= Multiplexer leakage current
R
ON
= Multiplexer ON resistance
R
S
= Source resistance
Differential Multiplexer Static Accuracy
Static accuracy errors in a differential multiplexer are diffi-
cult to control, especially when it is used for multiplexing
low-level signals with full-scale ranges of 10mV to 100mV.
The matching properties of the multiplexer, source and
output load play a very important part in determining the
transfer accuracy of the multiplexer. The source impedance
unbalance, common-mode impedance, load bias current
mismatch, load differential impedance mismatch, and com-
mon-mode impedance of the load all contribute errors to the
multiplexer. The multiplexer ON resistance mismatch, leak-
age current mismatch and ON resistance also contribute to
differential errors.
Referring to Figure 2, the effects of these errors can be
minimized by following the general guidelines described in
this section, especially for low-level multiplexing applica-
tions.
FIGURE 1. MPC506A Static Accuracy Equivalent Circuit.
Source and Multiplexer Resistive Loading Error
+
=
+
+
+
(
)
R
R
R
R
R
R
R
S
ON
S
ON
S
ON
L
100
where R
S
= source resistance
R
L
= load resistance
R
ON
= multiplexer ON resistance
R
S1
R
S16
R
ON
R
OFF
V
S1
V
S16
Z
L
Measured
Voltage
I
L
V
M
I
BIAS
FIGURE 2. MPC507A Static Accuracy Equivalent Circuit.
Z
L
R
S8A
R
S8B
R
OFF8A
R
OFF8B
C
CM
R
S1A
R
S1B
R
ON1A
R
ON1B
I
L
Cd/2
Cd/2
R
CM
Rd/2
Rd/2
I
BIAS A
I
BIAS B
R
CM8
R
CM1
R
CM
V
S1
V
S8
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