PCM67P/U
PCM69AP/AU
FEATURES
q
18-BIT RESOLUTION DUAL AUDIO DAC
q
EXCELLENT THD PERFORMANCE:
0.0025% (92dB) at F/S, K Grade
1.0% (40dB) at 60dB, K Grade
q
HIGH S/N RATIO: 110dB typ (IHF-A)
q
DUAL, CO-PHASE
q
SINGLE SUPPLY +5V OPERATION
q
LOW POWER: 75mW typical
q
CAPABLE OF 16X OVERSAMPLING
q
AVAILABLE IN SPACE SAVING
16-PIN DIP OR 20-PIN SOIC
q
OPERATING TEMP RANGE:
25
C to +85
C
q
EXTREMELY LOW GLITCH ENERGY
DESCRIPTION
The PCM67 and PCM69A dual 18-bit DAC are low
cost, dual output 18-bit BiCMOS digital-to-analog con-
verters utilizing a novel architecture to achieve excel-
lent low level performance.
By combining a conventional thin-film R-2R ladder
DAC, a digital offset technique with analog correction
and an advanced one-bit DAC using first order noise
shaping technique, the PCM67 and PCM69A achieve
high resolution, minimal glitch, and low zero-crossing
distortion.
PCM67 digital offset occurs at bit 9, making it ideal for
high-performance CD players. PCM69A digital offset
occurs at bit 4, making it an excellent choice for digital
musical instruments and audio DSP.
Both PCM67 and PCM69A operate from a single +5V
supply. The low power consumption and small size (16-
pin PDIP or 20-pin SOIC) make these converters ideal
for a variety of digital audio applications.
Reference
Servo
Input
Interface
Digital Signal In
10-Bit DAC plus
Analog Correction
Advanced 1-Bit
DAC
10-Bit DAC plus
Analog Correction
Advanced 1-Bit
DAC
Analog Output Lch
Analog Output Rch
Buffer
V
COM
Lch
Buffer
V
COM
Rch
Advanced 1-Bit BiCMOS Dual 18-Bit
DIGITAL-TO-ANALOG CONVERTER
International Airport Industrial Park Mailing Address: PO Box 11400 Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd. Tucson, AZ 85706
Tel: (520) 746-1111 Twx: 910-952-1111 Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
1992 Burr-Brown Corporation
PDS-1168A
Printed in U.S.A. August, 1993
SBAS024
2
PCM67/69A
USA OEM PRICES
SPECIFICATIONS
ELECTRICAL
All specifications at +25
C and +V
A
, +V
D
= +5V unless otherwise noted
PCM67/69A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
RESOLUTION
18
Bits
DYNAMIC RANGE, THD+N at 60dB Referred to Full Scale
106
dB
DIGITAL INPUT
Logic Family
TTL/CMOS Compatible
Logic Level: V
IH
I
IH
=
5
A
+2
+V
D
V
V
IL
I
IL
=
5
A
0
0.8
V
Data Format
Serial, MSB First, BTC
(1)
Input System Clock Frequency
16.9344
MHz
TOTAL HARMONIC DISTORTION + N
(2,3,4)
PCM67P/69AP, PCM67U/69AU
f = 991Hz (0dB)
f
S
= 352.8kHz
86
82
dB
f = 991Hz (20dB)
f
S
= 352.8kHz
68
dB
f = 991Hz (60dB)
f
S
= 352.8kHz
40
34
dB
PCM67P-J/69AP-J, PCM67U-J/69AU-J
f = 991Hz (0dB)
f
S
= 352.8kHz
91
88
dB
f = 991Hz (20dB)
f
S
= 352.8kHz
72
dB
f = 991Hz (60dB)
f
S
= 352.8kHz
46
40
dB
PCM67P-K/69AP-K, PCM67U-K/69AU-K
f = 991Hz (0dB)
f
S
= 352.8kHz
95
92
dB
f = 991Hz (20dB)
f
S
= 352.8kHz
74
dB
f = 991Hz (60dB)
f
S
= 352.8kHz
46
40
dB
CHANNEL SEPARATION
(f = 1kHz)
106
dB
ACCURACY
Level Linearity
at 90dB Signal Level
1
dB
Gain Error
3
10
%
Gain Mismatch, Channel-to-Channel
1
5
%
Gain Drift
0
C to +70
C
95
ppm/
C
Warm-up Time
1
Minute
IDLE CHANNEL SNR
(5)
20Hz to 40kHz at BPZ
(6)
110
dB
ANALOG OUTPUT
Output Range (
3%)
1.2
mA
Output Impedance (
30%)
1.8
k
V
COM
3.35
3.50
3.65
V
Glitch Energy
No Glitch Around Zero
POWER SUPPLY REQUIREMENTS, System Clock = 16.9344MHz
+V
A
, +V
D
Supply Voltage Range
+V
A
= +V
D
+4.75
+5.00
+5.25
V
+I
A
, +I
D
Combined Supply Current
+V
A
, +V
D
= +5V
15
20
mA
Power Dissipation
+V
A
, +V
D
= +5V
75
105
mW
TEMPERATURE RANGE
Operating
25
+85
C
Storage
55
+100
C
NOTES: (1) Binary Two's Complement coding. (2) Ratio of (Distortion
RMS
+ Noise
RMS
)/Signal
RMS
. (3) D/A converter output frequency/signal level (both left and right
channels are "on"). (4) D/A converter sample frequency (8 x 44.1kHz; 8
X
oversampling per channel). (5) Ratio of Noise
RMS
/Signal
RMS
. Measured using a 40kHz
3rd-order GIC (Generalized Immittance Converter) filter and an A-weighted filter. (6) Bipolar Zero.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
3
PCM67/69A
PCM67P
PCM67U
PCM69AP PCM69AU
DESCRIPTION
MNEMONIC
1
1
+5V Analog Supply Voltage
+V
A
2
2
Left Voltage Common
LV
COM
3
No Connection
NC
3
4
Left Current Output (0 to 1.2mA)
LI
OUT
4
5
Servo Decoupling Capacitor
SRVCAP
5
6
Reference Decoupling Capacitor
REFCAP
6
7
Right Current Output (0 to 1.2mA) RI
OUT
8
No Connection
NC
7
9
Right Voltage Common
RV
COM
8
10
Analog Common
ACOM
9
11
Digital Common
DCOM
12
Mode Control 2
MC2
10
13
Right Data Input
RDATA
11
14
Bit Clock
BTCK
12
15
System Clock
SYSCK
13
16
Word Clock
WDCK
14
17
Left Data Input
LDATA
18
Mode Control 3
MC3
15
19
Mode Control 1
MC1
16
20
+5V Digital Supply Voltage
+V
D
ABSOLUTE MAXIMUM RATINGS
+V
A
, +V
D
to ACOM, DCOM ................................................... 0V to +6.5V
ACOM to DCOM ...............................................................................
0.5V
Digital Inputs to DCOM ............................................ 0.3V to +V
D
+ 0.3V
Power Dissipation ................ 300mW (U Package), 500mW (P Package)
Lead Temperature, (soldering, 10s) .............................................. +260
C
Max Junction Temperature ............................................................ +165
C
NOTE: Stresses above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
PACKAGE INFORMATION
PACKAGE DRAWING
MODEL
PACKAGE
NUMBER
(1)
PCM67P/69AP
16-Pin Plastic DIP
180
PCM67U/69AU
20-Pin SOIC
248
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix D of Burr-Brown IC Data Book.
PIN ASSIGNMENTS
4
PCM67/69A
PIN CONFIGURATION -- PCM67P/69AP (16-Pin DIP)
PIN CONFIGURATION -- PCM67U/69AU (20-Pin SOIC)
Rch
OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PCM67P/69AP
R
NF
Lch
OUT
R
NF
10
F
1
F
Data-L
WDCK
SYS CLOCK
BCK
Data-R
+V
CC
(+5V)
3.3F
3.3F
10F
10F
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
PCM67U/69AU
Lch
OUT
R
NF
Rch
OUT
10
F
1
F
Data-L
WDCK
SYS CLOCK
BCK
Data-R
+V
CC
(+5V)
9
10
12
11
3.3F
3.3F
10F
10F
R
NF
5
PCM67/69A
CHANNEL SEPARATION vs SIGNAL FREQUENCY
115
110
105
100
95
100
500
1k
2k
4k
8k 16k
f (Hz)
Separation (dB)
... 128k
0.01%
0.001%
0.002%
0.005%
384
48
fs (Hz)
THD (F/S)
1.0%
0.1%
0.2%
0.5%
THD (60dB)
THD vs SYSTEM CLOCK FREQUENCY
192
96
60dB
F/S
fs = 44.1kHz
GAIN ERROR / V
COM
vs TEMPERATURE
Gain Error (%)
3
2
1
0
1
2
3
Temperature (%)
25
0
25
3.70
3.60
3.50
3.40
V
COM
(V)
50
75
100
85
0.01%
0.001%
0.002%
0.005%
25
0
25
50
85
100
Temperature (C)
THD (F/S)
1.0%
0.1%
0.2%
0.5%
THD (60dB)
THD vs TEMPERATURE
60dB
F/S
GAIN ERROR / V
COM
vs POWER SUPPLY
Gain Error (%)
3
2
1
0
1
2
3
V
CC
(V)
4.75
5.0
5.25
Gain Error
V
COM
3.70
3.60
3.50
3.40
V
COM
(V)
0.01%
0.005%
0.002%
0.001%
THD (F/S)
4.75
5.0
5.25
V
CC
(V)
THD vs POWER SUPPLY VOLTAGE
1.0%
0.5%
0.2%
0.1%
THD (60dB)
F/S
60dB
TYPICAL PERFORMANCE CURVES
All specifications at +25
C and V
CC
= +5.0V unless otherwise noted.
6
PCM67/69A
DISCUSSION OF
SPECIFICATIONS
The PCM67 and PCM69A are specified to provide critical
performance criteria for a variety of applications. The accu-
racy of a D/A converter is described by the transfer function
shown in Figure 1.
V
COM
R
NF
1.2mA
I
OUT
V
COM
(3.5V)
V
OUT
V
OUT
V
OUT
= 1.2mA R
NF
FIGURE 2. I/V Amplifier Circuit.
S/N RATIO
S/N ratio is defined as the ratio of full scale output and no input
noise level at BPZ point. The PCM67/69A is specified at
110dB typical with "IHF-A" filter.
LEVEL LINEARITY ERROR
Level linearity error is defined as the deviation of actual
analog output level from digital input level. PCM67/69A is
specified at 1dB typical at 90dB output level. The 0.5LSB
quantization error at 90dB of 16-bit conversion is equal to
+1.94dB, 2.5dB.
TOTAL HARMONIC DISTORTION
THD is a key parameter in audio applications, THD is a
measure of the magnitude and distribution of the linearity
error, differential linearity error, and noise, as well as quanti-
zation error. To be useful, THD should be specified for both
high level and low level input signals. This error is unadjustable
and is the most meaningful indicator of D/A converter accu-
racy for audio applications.
THD is defined as the ratio of the square root of the sum of the
squares of the values of the harmonics to the value of the
fundamental input frequency and is expressed in percent or
dB. The rms value of the PCM67/69A error referred to the
input can be shown to be
(1)
where n is the number of samples in one cycle of any given
sine wave, E
L
(i) is the linearity error of the PCM67 or
PCM69A at each sampling point. THD can then be expressed
as
(2)
where E
rms
is the rms signal-voltage level.
rms
=
1
n
E
L
(i )
+
E
Q
(i )
2
i
=
1
n
THD
=
rms
E
r ms
=
1
n
E
L
(i )
+
E
Q
(i )
2
i
=
1
n
E
rms
100 %
Analog
Out
Gain Error
Digital In
FSR
(V
COM
= 3.5V)
+FSR
011...11
000...00
111...11
100...00
BPZ
BPZ 1LSB
FIGURE 1. Transfer Performance.
DIGITAL INPUT CODE
The PCM67/69A accepts Binary Two's Complement (BTC)
digital input code (MSB FIRST).The relationship of digital
input to analog output is shown in Table 1.
ANALOG OUTPUT
ANALOG OUTPUT
DIGITAL INPUT
(VOLTAGE)
(CURRENT)
7FFFFF (HEX)
+FSR
1.2mA
00003F (HEX)
BPZ
0.6mA
FFFFFF (HEX)
BPZ 1LSB
0.59995mA
80003F (HEX)
FSR
0mA
TABLE I. Digital Code and Analog Out.
GAIN ERROR AND GAIN MISMATCH,
CHANNEL-TO-CHANNEL
Gain error is defined as deviation of the output current span
from the ideal span of 1.2mA (FSR) on each channel. Gain
error of PCM67/69A is typically
3% of FSR.
Gain mismatch, channel-to-channel is defined as the differ-
ence in gain error between the left channel and right channel.
THE RELATIONSHIP OF V
COM
AND I/V OUT
The output current range of PCM67 and PCM69A is 0mA to
1.2mA as shown in Table 1.
In the typical application, the non-inverting input of the
external I/V op amp is connected to the V
COM
pin of PCM67
and PCM69A. Accordingly, the output voltage level at FSR
after I/V conversion is V
COM
voltage (+3.5V) as shown in
Figure 2.
7
PCM67/69A
This expression indicates that, in general, there is a correlation
between the THD and the square root of the sum of the squares
of the linearity errors at each digital word of interest. How-
ever, this expression does not mean that the worst-case linear-
ity error of the D/A is directly correlated to THD.
For PCM67 and PCM69A the test period is set at an 8X
oversampling rate (352.8kHz = 44.1kHz
8), which is the
typical sample rate for CD player applications.
The test signal frequency is 991Hz and the amplitude of the
signal level is F/S (0dB), and 60dB down from F/S.
All THD tests are performed without a deglitcher circuit and
without a 20kHz low pass filter.
SYSTEM CLOCK REQUIREMENTS
The PCM67 and PCM69A need a system clock for the one-bit
noise shaping DAC operation.
The PCM67 is capable of only a 384Fs corollary system clock
frequency such as 192Fs, 96Fs (24 times word rate or integer
multiple of 24).
The PCM69A is capable of any system clock up from 48Fs to
384Fs such as 384Fs, 256Fs, 100Fs with condition for timing
as described in "Timing of PCM69A" in Figure 5.
The user can choose either model for their application.
Table II shows the different SYSCLK options.
LOGIC TIMING
The serial data bit transfers are triggered on positive bit clock
(BCK) edges. The serial-to-parallel data transfer to the DAC
occurs on the falling edge of Word Clock (WDCK). The
change in the output of the DAC coincides with the falling
edge of WDCK.
Refer to Figure 3 for graphical relationships of these signals.
The setup and hold timing relationships for these signals are
shown in Figure 4.
The PCM67/69A accepts TTL compatible logic input levels.
The data format of the PCM67/69A is BTC with the most
significant bit (MSB) being first in the serial input bit stream.
OTHER CAPABLE
MODEL
BASIC SYSCLK
SYSCLK
PCM67
384Fs
192Fs, 96Fs
PCM69A
Any Clock (with timing condition)
Examples: 384Fs, 300Fs, 256Fs, 200Fs, 90Fs
TABLE II. System Clock Requirements.
MSB
MSB
bit2
bit2
bit17
bit17
LSB
LSB
MSB
MSB
bit2
bit2
bit17
bit17
LSB
LSB
1 WDCK
R-ch Data
L-ch Data
Bit Clock
WD Clock
SYS Clock
FIGURE 3. Timing Diagram.
FIGURE 4. Timing Specification.
FIGURE 5. Timing of PCM69A for SYSCLK and WDCK.
Data
Bit Clock
WD Clock
SYS Clock
t
DH
t
DSU
t
DHO
t
CH
t
CW
t
CL
t
WC
t
SL
t
SH
t
WH
t
WL
LSB
t
SH
:
t
SL
:
t
DW
:
t
DSU
:
t
DHO
:
t
CH
:
t
CL
:
t
CW
:
t
WC
:
t
WH
:
t
WL
:
SYS Clock High Pulse Width : 15ns, min
SYS Clock Low Pulse Width : 15ns, min
Data Valid Time : 20ns, min
Data Setup Time : 10ns, min
Data Hold Time : 5ns, min
Bit Clock High Pulse Width : 15ns, min
Bit Clock Low Pulse Width : 15ns, min
WD Clock Fall Time From Bit Clock Rise : 10ns, min
Bit Clock Rise Time From WD Clock Fall : 15ns, min
WD Clock High Pulse Width : 1 SYS Clock Cycle, min
WD Clock Low Pulse Width : 1 SYS Clock Cycle, min
TIMING OF PCM69A
PCM69A timing is similar to PCM67 except that PCM69A is
capable of operating from any system clock up to 384Fs. For
synchronized operation, PCM69A system clock and WDCK
timing must be as shown in Figure 5.
WDCK
SYSCLK
t
n1
t
n2
SYSCLK
t
n1
: WDCK Fall Delay From Rise of SYSCLK : min 10ns
t
n2
: SYSCLK Rise Delay From Fall of WDCK : min 20ns
8
PCM67/69A
INSTALLATION
POWER SUPPLIES
Refer to "Pin Configuration" diagram for proper connection
of the PCM67/69A. The PCM67/69A requires only a +5V
supply. Both analog and digital supplies should be tied to-
gether at a single point, as no real advantage is gained by using
separate supplies. It is more important that both these supplies
be as "clean" as possible to reduce coupling of supply noise to
the output.
FILTER CAPACITOR REQUIREMENTS
As shown in the "Pin Configuration" diagram, various sizes of
decoupling capacitors can be used with no special tolerances
required. All capacitors should be as close to the appropriate
pins of the PCM67/69A as possible to reduce noise pickup
from surrounding circuitry.
A power supply decoupling capacitor should be used near the
analog supply pin to maximize power supply rejection, as
shown in Figure 6, regardless of how good the supplies are.
Both commons should be connected to an analog ground
plane as close to the PCM67/69A as possible.
The value of these capacitors is influenced by actual board
layout design and noise from power supplies and other digital
input lines.
The best suitable value for the capacitors should be deter-
mined by the user's actual application board.
FIGURE 6. Shift of I/V Out Voltage.
SHIFT OF I/V OUT VOLTAGE
If the user requires a bipolar voltage output centered around
0V or one-half of V
CC
, the output can be shifted by adding an
offset current on the inverting point of the I/V op amp as
shown in Figure 6.
FIGURE 7. Useful Application Circuit for Shift of I/V Out
Voltage.
INTERFACE CONTROL FUNCTION
Both the PCM67 and PCM69A (SOIC package type) are
capable of 16-bit L/R serial input and 20-bit L/R parallel input
as shown in Table 3.
R
OS
R
NF
+V
CC
I
OUT
V
COM
(3.5V)
V
CC
2
V
S
V
O
V
OUT
or 0V
In case of shift to
3V swing, 0V center
R
NF
= = = 5k
1.2mA
V
OUT
1.2mA
6V
FSR(V
S
) = 3V after offset addition, shift voltage
V
SHT
is given by
V
SHT
= V
COM
+ 3V = 3.5 + 3 = 6.5V
Offset Current I
OS
is given by
I
OS
= = = 1.3mA
R
NF
5k
6.5V
V
SHT
Offset Resistor R
OS
is given by
I
OS
1.3mA
5 3.5V
V
CC
V
COM
R
OS
= = = 1.15k
V
O
2
V
COM
(+3.5V)
V
O
V
COM
+
V
SHT
I
OS
MC1
MC2
MC3
DATA-R
INPUT FORMAT
0
0
1
0
16-Bit L/R Serial
(1)
0
0
1
1
16-Bit L/R Serial
(1)
0
1
1
0
18-Bit L/R Serial
(1)
0
1
1
1
18-Bit L/R Serial
(1)
1
0
1
X
20-Bit L/R Parallel
1
0
0
X
20-Bit L/R Parallel
[WDCK Invert]
1
1
1
X
18-Bit L/R Parallel
1
1
0
X
18-Bit L/R Parallel
[WDCK Invert]
L R
R
L
WDCK
L R
R
L
WDCK
L R
R
L
WDCK
L R
R
L
WDCK
NOTE: (1) Data input to Data-Lch (Pin 17) for L/R serial format.
TABLE III. Interface Control Function of SOIC.
MC1
DATA-R
INPUT FORMAT
0
0
18-Bit L/R Serial
0
1
18-Bit L/R Serial
1
X
18-Bit L/R Parallel
TABLE IV. Interface Control Function of DIP.
L R
R
L
WDCK
L R
R
L
WDCK
PCM67P and PCM69AP (DIP package) have only 18-bit
L/R serial input function as shown in Table 4.
R
2
330
R
NF
+V
CC
(+5V)
I
OUT
V
COM
0V
6V
V
OUT
5k
R
1
820
+
+
C
1
C
2
10
F ~ 100
F
10
F ~ 100
F
Note: R
1
and C
1
are noise de-coupling circuits from noise
on +V
CC
power supply line.
9
PCM67/69A
DIGITAL FILTER INTERFACE
16-Bit L/R Serial -- 1
FIGURE 8. Using Sony CXD2551.
16-Bit L/R Serial -- 2
FIGURE 9. Using NPC SM5807.
FIGURE 11. Using Burr-Brown DF1700.
FIGURE 10. Using NPC SM5840.
18-Bit L/R Parallel
DGND
MC2
Data R-ch
BCK
SYSCLK
WDCK
Data L-ch
MC3
MC1
+V
DD
11
12
13
14
15
16
17
18
19
20
PCM67U/69AU
DOR
BCK0
XTi
WDCK0
DOL
DF1700
+V
DD
20-Bit Mode
20-Bit L/R Parallel
DGND
MC2
Data R-ch
BCK
SYSCLK
WDCK
Data L-ch
MC3
MC1
+V
DD
11
12
13
14
15
16
17
18
19
20
PCM67U/69AU
BCK0
X0 or X1
LRCK0
Data L-ch
+V
DD
CXD2551
4FS, 16-Bit Mode
DGND
MC2
Data R-ch
BCK
SYSCLK
WDCK
Data L-ch
MC3
MC1
+V
DD
11
12
13
14
15
16
17
18
19
20
PCM67U/69AU
BCK0
XTi
LRC0
D
OUT
SM5807
+V
DD
SOMD = H
DGND
MC2
Data R-ch
BCK
SYSCLK
WDCK
Data L-ch
MC3
MC1
+V
DD
11
12
13
14
15
16
17
18
19
20
PCM67U/69AU
DOR
BCK0
XTi
WDCK0
DOL
SM5840
V
DD
18-Bit Mode
10
PCM67/69A
THEORY OF OPERATION
Digital converters in audio systems have traditionally utilized
a laser-trimmed, current-source DAC architecture. Unfortu-
nately, this type of technology suffers from the problems
inherent in switching widely varying current levels. Design
improvements have helped, but DACs of this type still exhibit
low-level nonlinearity due to errors at the major carry.
Recently, DACs employing a different architecture have been
introduced. Most of these DACs utilize a one-bit DAC with
"noise shaping" techniques and very high oversampling rate
to achieve the digital-to-analog conversion. Basically, the
trade-off is from very accurate but slow current sources to one
rapidly sampled current source whose average output in the
audio frequency range is equal to the current desired. Noise
shaping insures that the "undesirable" frequencies associated
with one-bit DAC output lie outside the audio range.
These "Bitstream", "MASH", or one-bit DACs overcome the
low level linearity problems of conventional DACs, since
there can be no major carry error. However, this architecture
exhibits problems of its own: signal-to-noise performance is
usually worse than a similar conventional DAC, "dither
noise" may be needed in order to get rid of unwanted tones, a
separate high-speed clock may be required, the part may show
sensitivity to clock jitter, and a high-order low-pass filter is
necessary to filter the DAC output.
The PCM67/69A is a cross between these two architectures.
It includes both a conventional laser-trimmed, current-source
DAC and an advanced one-bit DAC. The conventional DAC
is a 10-bit DAC where each bit weight has been trimmed to 18-
bit linearity. The one-bit DAC has a weight equal to bit 10 and
employs a first-order noise shaper to generate the "bitstream."
This approach does not eliminate all the problems associated
with the two architectures but rather minimizes them as much
as possible. The conventional DAC still exhibits some major
carry error which would normally reduce low-level linearity.
However, to reduce this error even further, the PCM67/69A
utilizes an offset technique whereby bit n is subtracted from
the digital input code whenever it is positive (see Figure 1 and
Table I). When this is done, an offset current equal to the
weight of bit n is switched in to compensate. This offset comes
from a one-bit DAC which has also been trimmed to 18-bit
linearity. While this technique doesn't remove the major carry
error completely, the "glitch" is only present in higher ampli-
tude signals where it is much less audible.
As for the one-bit DAC, a number of problems with this
architecture are also reduced: the DAC is designed to operate
from the system clock, thus eliminating the need for a separate
clock; the lower quantizing level of the DAC make it less
sensitive to clock jitter; and output filtering requirements are
reduced because "out-of-band noise" has smaller amplitude,
is "farther-out," and increases much more slowly due to the
first-order noise shaper. Still, it is important to keep in mind
that the one-bit DAC imposes some design considerations.
Figure 2 shows the THD + N of the converter versus "System
Clock" frequency. This is the clock used to operate the one-bit
DAC and noise shaper. Generally, the higher the oversampling
the better. However, near full-scale, the converter is limited by
other constraints and higher clock frequencies (past 96f
s
) tend
to slightly worsen its performance. At low levels, perfor-
mance improves almost linearly with increasing clock fre-
quency. The one-bit DAC was designed to operate between
96f
s
(4X oversampling) and 384f
s
(16X oversampling). But,
it can be operated at 48f
s
(2X oversampling) with slightly
reduced performance.
TOTAL HARMONIC DISTORTION + NOISE
A key specification for audio DACs is usually total harmonic
distortion plus noise (THD + N). For the PCM67/69A, THD
+ N is tested in production as shown in Figure 12. Digital data
words are read into the PCM67/69A at eight times the stan-
dard compact disk audio sampling frequency of 44.1kHz
(352.8kHz) so that a sine wave output of 991Hz is realized.
The output of the DAC goes to an I-to-V converter, then to a
programmable gain amplifier to provide gain at lower signal
output test levels, and then through a 40kHz low pass filter
before being fed into an analog type distortion analyzer.
11
PCM67/69A
FIGURE 12. PCM67/69A THD+N Production Test.
FIGURE 13. Single +5V Power Supply, with LPF, I/V Amp Application Circuit for Portable Digital Audio.
+ C
12
2200pF
11
12
13
14
15
16
17
18
19
20
10
9
8
7
6
5
4
3
2
1
PCM67
or
PCM69A
A
1
+ C
6
100
F
R
4
680
R
3
680
+
C
8
10
F
+
C
5
10
F
+
C
4
10
F
1000pF
C
10
R
5
2k
+5V
1000pF
C
9
R
6
2k
C
3
100
F
+
R
2
680
R
1
680
+
C
7
10
F
C
2
100
F
+
C
1
0.1
F
+
V
CC
(+5V)
A
2
R
7
200
+ C
11
2200pF
R
8
200
OUT R-ch
2.5V
1.2V
OUT L-ch
2.5V
1.2V
Digital
In
A
1
, A
2
; NJM2100 or LM833
Distortion
Analyzer
Use 400Hz High-Pass
Filter and 30kHz
Low-Pass Filter
Meter Settings
Programmable
Gain Amp
0dB to 60dB
Low-Pass
Filter
40kHz 3rd-Order
GIC Type
Parallel-to-Serial
Conversion
Digital Code
(EPROM)
Binary
Counter
Timing
Logic
Bit Clock
Sampling Rate = 44.1kHz x 8 (352.8kHz)
Output Frequency = 991Hz
(Shiba Soku Model
725 or Equivalent)
I-to-V
Converter
OPA627
System Clock
Word Clock
DUT
(PCM67/69A)
12
PCM67/69A
FIGURE 14. HiFi D/A Converter Unit Application with Digital Audio Interface Format.
1M
16.9344MHz
18-Bit D/A
Converter
16
1
1F
+5V
3.3F
9
8
2
3
LV
COM
11
10
8X Interpolation
Digital Filter
17
22
3
+5V
23
100pF
14
21
16
4.7F
1
28
2
26
25
24
4.7F
6
10
4
Digital Interface
Format Receiver
17
+5V
8
4700pF
31
4
5
6
12
15
17
0.1F
28
4
4.7F
17.1k
+5V
(192F )
S
10pF
10pF
Interleaved
Digital
Input
150
A
BCO
L/R
DA
AGND
Burr-Brown
PCM67P/69AP
(Note: 16-Pin DIP)
Burr-Brown
DF1700P
8
DOR
BCO
WCK
DOL
4.7F
RDATA
A
1
5
6
+
+
14
13
3.3F
4
5
NOTE: Only left channel shown.
BTCK
SYSCK
WDCK
LDATA
LI
OUT
DGND
Yamaha
YM3623
12
+
10F
15
2.7k
5k
220pF
A
2
2
3
1
+15V
+
4.7
F
8
+
4.7
F
4
15V
V
OUT
Left
A
3
2
3
1
+15V
+
4.7
F
8
+
4.7
F
4
15V
100k
3.3
F
510
2200pF
1.5k
1.5k
1.5k
2200pF
A
4
5
6
7
2200pF
A
1
to A
4
= Burr-Brown OPA2604AP
or NE5532 equivalent.
10F
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Copyright
2000, Texas Instruments Incorporated
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