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PLL1700
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
MULTI-CLOCK GENERATOR
DESCRIPTION
The PLL1700 is a low cost, multi-clock generator
Phase Lock Loop (PLL).
The PLL1700 can generate four systems clocks from a
27MHz reference input frequency.
The device gives customers both cost and space savings
by eliminating external components and enables cus-
tomers to achive the very low jitter performance needed
for high performance audio digital-to-analog convert-
ers (DAC) and/or analog-to-digital converters (ADC).
The PLL1700 is ideal for MPEG-2 applications which
use a 27MHz master clock such as DVD players, DVD
add-on cards for multimedia PCs, digital HDTV sys-
tems, and set-top boxes.
FEATURES
q
27MHZ MASTER CLOCK INPUT
q
GENERATED AUDIO SYSTEM CLOCK:
SCKO1: 33.8688MHz (Fixed)
SCKO2: 256f
S
SCKO3: 384f
S
SCKO4: 768f
S
q
ZERO PPM ERROR OUTPUT CLOCKS
q
LOW CLOCK JITTER: 150ps at SCKO3
q
MULTIPLE SAMPLING FREQUENCIES:
f
S
= 32kHz, 44.1kHz, 48kHz, 64kHz,
88.2kHz, 96kHz
q
+3.3V CMOS LOGIC INTERFACE
q
DUAL POWER SUPPLIES: +5V and +3.3V
q
SMALL PACKAGE: 20-Lead SSOP
OSC
PLL2
PLL1
Counter Q
Counter P
SCKO2
SCKO3
SCKO4
MCKO
MCKO
XT1
XT2
Reset
Mode
Control
I/F
Power Supply
RST
MODE
ML
MC
MD
V
DDP
V
DDB
V
DD
GNDP
GNDB
GND
SCKO1
1998 Burr-Brown Corporation
PDS-1455A
Printed in U.S.A. August, 1998
PLL1700
2
PLL1700
SPECIFICATIONS
All specifications at T
A
= +25
C, V
DD
= V
DDP
= +5V, V
DDB
= +3.3V, f
M
= 27MHz crystal oscillation and f
S
= 48kHz, unless otherwise noted.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
PLL1700E
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUT/OUTPUT
Input Logic Level:
TTL-Compatible
V
IH
2.0
VDC
V
IL
0.8
VDC
Input Logic Current:
I
IH
(1)
V
IN
= V
DD
200
A
I
IL
(1)
V
IN
= 0V
1
A
I
IH
(2)
V
IN
= V
DD
4
mA
I
IL
(2)
V
IN
= 0V
800
A
Output Logic Level:
CMOS
V
OH
(3)
I
OH
= 4mA
V
DDB
0.4V
VDC
V
OL
(3)
I
OL
= 4mA
0.4
VDC
Sampling Frequency (f
S
)
Standard f
S
32
44.1
48
kHz
Double f
S
64
88.2
96
kHz
MASTER CLOCK (MCKO, MCKO)
f
M
= 27MHz, C
L
= 20pF
Master Clock Frequency
26.73
27
27.27
MHz
Clock Jitter
(4)
300
ps
Clock Duty Cycle
MCKO
40
50
60
%
For Crystal Oscillation
MCKO
40
50
60
%
Clock Duty Cycle
MCKO
40
%
For External Clock
MCKO
60
%
PHASE LOCK LOOP (PLL)
f
M
= 27MHz, C
L
= 20pF
Generated System Clock Frequency
SCKO1
Fixed
33.8688
MHz
SCKO2
256f
S
8.192
24.576
MHz
SCKO3
384f
S
12.288
36.864
MHz
SCKO4
768f
S
24.576
36.864
MHz
Generated Clock Rise Time
(3)
20% to 80% V
DDB
5
ns
Generated Clock Fall Time
(3)
80% to 20% V
DDB
5
ns
Generated Clock Duty Cycle
SCKO1, SCKO3, SCKO4
40
50
60
%
SCKO2 (standard)
40
50
60
%
SCKO2 (double)
(5)
25
33
40
%
Generated Clock Jitter
(4)
SCKO1, SCKO2 (standard), SCKO4
300
ps
SCKO3
150
ps
SCKO2 (double)
450
ps
Settling Time
To Programmed Frequency
20
ms
Power-Up Time
To Programmed Frequency
15
30
ms
POWER SUPPLY REQUIREMENTS
Voltage Range
V
DD
, V
DDP
+4.5
+5
+5.5
VDC
V
DDB
+2.7
+3.3
+3.6
VDC
Supply Current
(6)
:
I
DD
+ I
DDP
V
DD
= V
DDP
= 5V, f
S
= 48kHz
11
16
mA
I
DDB
V
DDB
= +3.3V, f
S
= 48kHz
6
9
mA
Power Dissipation
f
S
= 48kHz
75
110
mW
TEMPERATURE RANGE
Operation
25
+85
C
Storage
55
+125
C
NOTES: (1) ML, MC, MD, MODE, RST (Schmitt-trigger input with internal pull-down resistor). (2) XT1, when an external 27MHz clock is used, the buffer ICs, such
as 74HC04, are recommended to interface to XT1. (3) MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1. (4) Jitter performance is specified as standard
deviation of jitter under 27MHz crystal oscillation. (5) When SCKO2 is set to double rate clock output, its duty cycle is 33%. (6) f
M
= 27MHz crystal oscillation, no
load on MCKO, MCKO, SCKO4, SCKO3, SCKO2, and SCKO1.
3
PLL1700
PIN ASSIGNMENTS
PIN CONFIGURATION
TOP VIEW
SSOP
PACKAGE INFORMATION
PACKAGE
TEMPERATURE
DRAWING
PRODUCT
PACKAGE
RANGE
NUMBER
(1)
PLL1700E
20-Lead SSOP
25
C to +85
C
334-1
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (+V
DD
, +V
DDP
, +V
DDB
) .............................................. +6.5V
Supply Voltage Differences (+V
DD
, +V
DDP
) .......................................
0.1V
GND Voltage Differences: GND, GNDP, GNDB ...............................
0.1V
Digital Input Voltage ................................................. 0.3V to (V
DD
+ 0.3V)
Digital Output Voltage ............................................ 0.3V to (V
DDB
+ 0.3V)
Input Current (any pins except supply pins) ...................................
10mA
Power Dissipation .......................................................................... 300mW
Operating Temperature Range ......................................... 25
C to +85
C
Storage Temperature ...................................................... 55
C to +125
C
Lead Temperature (soldering, 5s) ................................................. +260
C
Package Temperature (IR reflow, 10s) .......................................... +235
C
PIN
NAME
I/O
FUNCTION
1
ML/SR0
IN
Latch Enable for Software Mode/Sampling Rate
Selection for Hardware Mode. When MODE pin
is LOW, ML is selected.
(1)
2
MODE
IN
Mode Control Select. When this pin is HIGH,
device is operated in hardware mode using SR0
(pin 1), FS0 (pin 19), and FS1 (pin 20). When
this pin is LOW, device is operated in software
mode by three-wire interface using ML (pin 1),
MD (pin 19) and MC (pin 20).
(1)
3
V
DD
--
Digital Power Supply, +5V.
4
GND
--
Digital Ground.
5
XT2
--
27MHz Crystal. When an external 27MHz clock
is applied to XT1 (pin 6), this pin must be
connected to GND.
6
XT1
IN
27MHz Oscillator Input/External 27MHz Input.
7
GNDP
--
Ground for PLL.
8
V
DDP
--
Power Supply for PLL, +5V.
9
RSV
--
Reserved. Must be left open.
10
MCKO
OUT
27MHz Output.
11
MCKO
OUT
Inverted 27MHz Output.
12
SCKO1
OUT
Fixed 33.8688MHz Clock Output.
13
SCKO4
OUT
768f
S
Clock Output.
14
SCKO2
OUT
256f
S
Clock Output.
15
GNDB
--
Digital Ground for V
DDB
.
16
V
DDB
--
Digital Power Supply for Clock Output Buffers,
+3.3V.
17
SCKO3
OUT
384f
S
Output. This output has been optimized
for the lowest jitter and should be connected to
the audio DAC(s).
18
RST
IN
Reset. When this pin is LOW, device is held in
reset.
(1)
19
MD/FS0
IN
Serial Data Input for Software Mode/Sampling
Frequency Selection for Hardware Mode. When
MODE pin is LOW, MD is selected.
(1)
20
MC/FS1
IN
Shift Clock Input for Software Mode/Sampling
Frequency Selection for Hardware Mode. When
MODE pin is LOW, MC is selected.
(1)
NOTE: (1) Schmitt-trigger input with internal pull-down resistors.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
ML/SR0
MODE
V
DD
GND
XT2
XT1
GNDP
V
DDP
RSV
MCKO
MC/FS1
MD/FS0
RST
SCKO3
V
DDB
GNDB
SCKO2
SCKO4
SCKO1
MCKO
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PLL1700E
4
PLL1700
TYPICAL PERFORMANCE CURVES
At T
A
= +25
C, V
DD
= V
DDP
= +5V, V
DDB
= +3.3V, C
L
= 20pF, unless otherwise noted.
JITTER vs SAMPLING FREQUENCY
Sampling Frequency, f
S
(kHz)
Jitter (pS rms)
400
300
200
100
0
44.1
32
48
96
SCKO1
SCKO3
MCKO
DUTY CYCLE RATIO vs SAMPLING FREQUENCY
Sampling Frequency, f
S
(kHz)
Duty Cycle Ratio (%)
70
60
50
40
30
44.1
32
48
96
SCKO3
MCKO (XTAL Operation)
MCKO (External Clock)
300
200
100
0
25
+25
+85
Temperature (
C)
SCKO Jitter (pS rms)
SCKO3 JITTER vs TEMPERATURE
48kHz
32kHz
96kHz
300
200
100
0
2.7
3.3
3.6
V
DDB
(V)
SCKO Jitter (pS rms)
SCKO3 JITTER vs V
DDB
48kHz
32kHz
96kHz
5
PLL1700
THEORY OF OPERATION
MASTER CLOCK AND SYSTEM CLOCK OUTPUT
The PLL1700 consists of a dual PLL clock and master clock
generator which generates four system clocks and two buff-
ered 27MHz clocks from a 27MHz master clock. Figure 1
shows the block diagram of the PLL1700. The PLL is
designed to accept a 27MHz master clock or crystal oscilla-
tor. The master clock can be either a crystal oscillator placed
between XT1 (pin 6) and XT2 (pin 5), or an external input
to XT1. If an external master clock is used, XT2 should be
connected to ground. Figure 2 illustrates possible system
clock connection options, and Figure 3 illustrates the 27MHz
master clock timing requirements.
FIGURE 1. Block Diagram of PLL1700.
FIGURE 2. Master Clock Generator Connection Diagram.
FIGURE 3. External Master Clock Timing Requirement.
t
XT1H
t
XT1L
2.0V
XT1
0.8V
DESCRIPTION
SYMBOL
MIN
TYP
MAX
UNITS
System Clock Pulse Width HIGH
t
XT1H
15
ns
System Clock Pulse Width LOW
t
XT1L
15
ns
OSC
Counter N
Counter M
Counter P
Counter Q
SCKO2
256f
S
SCKO1
33.8688MHz
SCKO4
768f
S
SCKO3
384f
S
Data
ROM
Frequency Control
PLL2
PLL1
Phase Detector
and
Loop Filter
VCO
VCO
Counter M
Counter N
Phase Detector
and
Loop Filter
MCKO
27MHz
MCKO
XT2
XT1
C
1
C
2
C
1
, C
2
= 10pF to 33pF
27MHz Internal
Master Clock
XTI
XT2
Crystal
OSC
Circuit
Xtal
PLL1700
MCKO
Buffer
External Clock
Crystal Resonator Connection
MCKO
Buffer
Crystal
OSC
Circuit
27MHz Internal
Master Clock
XT1
XT2
PLL1700
MCKO
Buffer
External Clock Input
MCKO
Buffer
6
PLL1700
The PLL1700 provides a very low jitter, high accuracy
clock. SCKO1 is a fixed frequency clock which is
33.8688MHz (768 x 44.1kHz) for a CD-DA DSP. The
output frequency of the remaining clocks is determined by
the sampling frequency (f
S
) by software or hardware control.
SCKO2 and SCKO3 output 256f
S
and 384f
S
systems clocks,
respectively. SCKO4 output is 768f
S
if the sampling fre-
quency is 32kHz, 44.1kHz, 48kHz, or the output is 384f
S
if
the sampling frequency is 64kHz, 88.2kHz, or 96kHz. Table
I shows each sampling frequency. The system clock output
frequencies are generated by a 27MHz master clock and
programmed sampling frequencies are shown in Table II.
SAMPLING
FREQUENCY
SAMPLING
SKCO2
SCKO3
SCKO4
(kHz)
RATE
(MHz)
(MHz)
(MHz)
32
Standard
8.192
12.288
24.576
44.1
Standard
11.2896
16.9344
33.8688
48
Standard
12.288
18.4320
36.8640
64
Double
16.384
24.576
24.576
88.2
Double
22.5792
33.8688
33.8688
96
Double
24.576
36.8640
36.8640
TABLE II. Sampling Frequencies and Master Clock Output
Frequencies.
SAMPLING
SAMPLING RATE
FREQUENCY (kHz)
Standard Sampling Frequencies
32
44.1
48
Double of Standard Sampling Frequencies
64
88.2
96
TABLE I. Sampling Frequencies.
FUNCTION CONTROL
The built-in function of the PLL1700 can be controlled in
the software mode (serial mode), which uses a three-wire
interface by ML (pin 1), MC (pin 20), and MD (pin 19),
when MODE (pin 2) = L. They can also be controlled in the
hardware mode (parallel mode) which uses SR0 (pin 1), FS1
(pin 20) and FS0 (pin 19), when MODE (pin 2) = H. The
selectable functions are shown in Table III.
HARDWARE
SOFTWARE
MODE
MODE
FUNCTION
(MODE = H)
(MODE = L)
Sampling Frequency Select
(32kHz, 44.1kHz, 48kHz)
Yes
Yes
Sampling Rate Select (Standard/Double)
Yes
Yes
Each Clock Output Enable/Disable
No
Yes
TABLE III. Selectable Functions.
Response time from power-on (or applying the clock to
XT1) to SCKO settling time is typically 15ms. Delay time
from sampling frequency change to SCKO settling time is
20ms maximum. Figure 4 illustrates SCKO transient timing.
External buffers are recommended on all output clocks in
order to avoid degrading the jitter performance of the
PLL1700.
RESET
The PLL1700 has an internal power-on reset circuit, as well
as an external forced reset (RST, pin 18). Both resets have
the same effect on the PLL1700's functions. The mode
register's default settings for software mode are initialized
by reset. Throughout the reset period, all clock outputs are
enabled with the default settings. Initialization for the inter-
nal power-on reset is done automatically during 1024 master
clocks at V
DD
2.2V (1.8V to 2.6V). When using the
internal power-on reset, RST should be HIGH. Power-on
reset timing is shown in Figure 5. RST (pin 18) accepts an
external forced reset by RST = L. Initialization (reset) is
done when RST = L and 1024 master clocks after RST =
H. External reset timing is shown in Figures 6 and 7.
FUNCTION
DEFAULT
Sampling Frequency Select (32kHz, 44.1kHz, 48kHz)
48kHz Group
Sampling Rate Select (Standard/Double)
Standard
Each Clock Output Enable/Disable
Enable
TABLE IV. Selectable Functions.
FS1 (Pin 20)
FS0 (Pin 19)
SAMPLING GROUP
L
L
48kHz
L
H
44.1kHz
H
L
32kHz
H
H
Reserved
SR0 (Pin 1)
SAMPLING RATE SELECT
L
Standard
H
Double
HARDWARE MODE (MODE = H)
In the hardware mode, the following functions can be
selected:
Sampling Group Select
The sampling frequency group can be selected by FS1 (pin
20) and FS0 (pin 19).
Sampling Rate Select
The sampling rate can be selected by SR0 (pin 1)
SOFTWARE MODE (MODE = L)
The PLL1700's special function in software mode is shown
in Table IV. These functions are controlled using ML, MC,
and MD serial control signal.
7
PLL1700
FIGURE 4. System Clock Transient Timing Chart.
1024 System Clock Periods
Reset
Reset Removal
2.6V
2.2V
1.8V
V
DD
Internal Reset
Master Clock
FIGURE 5. Power-On Reset Timing.
FIGURE 6. External Reset Timing.
FIGURE 7. Reset Pulse Timing Requirement.
3 clocks of MCKO
ML
SCKO2
SCKO3
SCKO4
SCKO1
Clock Transistion Region
33.8688MHz
Stable
Stable
20ms
1024 System Clock Periods
Reset
Reset Removal
Master Clock
Internal Reset
RST
t
RST
System Clock Pulse Width LOW
t
RST
20ns
(min)
t
RST
1.4V
RST
8
PLL1700
FIGURE 8. Software Mode Control Format.
FS1
FS0
SAMPLING FREQUENCY
DEFAULT
0
0
48kHz
O
0
1
44.1kHz
1
0
32kHz
1
1
Reserved
PROGRAM REGISTER BIT-MAPPING
The built-in functions of the PLL1700 are controlled through
a 16-bit program register. This register is loaded using MD.
After the 16 data bits are clocked in using the rising edge of
MC, ML is used to latch the data into the register. Table V
shows the bit-mapping of the registers. The software mode
control format and control data input timing is shown in
Figures 8 and 9, respectively.
Mode Register
CE [1:6]:
Clock Output Control
DESCRIPTION
SYMBOL
MIN
TYP
MAX
UNITS
MC Pulse Cycle Time
t
MCY
100
ns
MC Pulse Width LOW
t
MCL
40
ns
MC Pulse Width HIGH
t
MCH
40
ns
MD Hold Time
t
MDH
40
ns
MD Set-Up Time
t
MDS
40
ns
ML Low Level Time
t
MLL
16
MC Clocks
(1)
ML High Level Time
t
MHH
200
ns
ML Hold Time
(2)
t
MLH
40
ns
ML Set-Up Time
(3)
t
MLS
40
ns
NOTES: (1) MC clocks: MC clock period. (2) MC rising edge for LSB to ML rising edge. (3) ML rising edge
to the next MC rising edge. If the MC Clock is stopped after the LSB, any ML rising time is accepted.
FIGURE 9. Control Data Input Timing.
REGISTER
BIT NAME
DESCRIPTION
MODE
CE6
MCKO Output Enable/Disable
CE5
MCKO Output Enable/Disable
CE4
SCKO4 Output Enable/Disable
CE3
SCKO3 OUtput Enable/Disable
CE2
SCKO2 Output Enable/Disable
CE1
SCKO1 Output Enable/Disable
SR [1:0]
Sampling Rate Select
FS [1:0]
Sampling Frequency Select
TABLE V. Register Mapping.
Mode Register
FS [1:0]:
Sampling Frequency Group Select
SR [1:0]:
Sample Rate Select
SR1
SR0
SAMPLING RATE
DEFAULT
0
0
Standard
O
0
1
Double
1
0
Reserved
1
1
Reserved
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ML (pin 1)
MC (pin 20)
MD (pin 19)
D15 D14 D13 D12 D11 D0 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
CE6 CE5 CE4 CE3 CE2 CE1 SR1 SR0 FS1 FS0
CE1 - CE6
CLOCK OUTPUT CONTROL
DEFAULT
0
Clock Output Disable
1
Clock Output Enable
O
MSB
LSB
1.4V
1.4V
1.4V
t
MLS
t
MCH
t
MCL
t
MLL
t
MHH
t
MLH
t
MLS
t
MDS
t
MDH
t
MCY
ML (pin 1)
MC (pin 20)
MD (pin 19)
9
PLL1700
CONNECTION DIAGRAM
Figure 10 shows the typical connection circuit for the
PLL1700. There are three grounds for digital, analog and
PLL power supply. However, the use of one common
ground connection is recommended to avoid latch-up prob-
lems. Power supplies should be bypassed as close as pos-
sible to the device.
MPEG-2 APPLICATIONS
Typical applications for the PLL1700 are MPEG-2 based
systems such as DVD players, DVD add-on cards for mul-
timedia PCs, digital HDTV systems, and step-top boxes.
The PLL1700 provides audio system clocks for a CD-DA
DSP, DVD DSP, Karaoke DSP, and DAC(s) from a 27MHz
video clock.
FIGURE 11. PLL1700 System Application Block Diagram.
FIGURE 10. Typical Connection Diagram.
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
Clock
Output
(3)
Mode
Control
0.1
F and 10
F
(1)
PLL1700E
ML/SR01
MODE
V
DD
GND
XT2
XT1
GNDP
V
DDP
RSV
MCKO
MC/FS1
MD/FS0
RST
SCKO3
V
DDB
GNDB
SCKO2
SCKO4
SCKO1
MCKO
C
3
C
2
0.1
F
and
10
F
(1)
22
F - 47
F
(1)
C
1
22
F - 47
F
(1)
0.1
F
and
10
F
(1)
C
5
C
4
(2)
+5V
+3.3 V
NOTES: (1) 0.1
F ceramic and 10
F tantalum capacitor typical, depending on quality of power supply and
pattern layout. (2) 27MHz quartz crystal and 10pF through two 33pF ceramic capacitors. (3) To achieve
best possible jitter performance, it is recommended to minimize the load capacitance on the clock output.
+
+
PCM1716
PCM1716
PCM1716
Front
Surround
Center
Subwoofer
384f
S
768f
S
256f
S
SCKO3
SCKO4
SCKO2
MCKO
PLL1700
27MHz
27MHz
Crystal
CD-DA/
DVD DSP
M P E G / A C - 3
A u d i o D e c o d e r
K a r a o k e
D S P
SCKO1
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