Monolithic
SAMPLE/HOLD AMPLIFIER
FEATURES
q
12-BIT THROUGHPUT ACCURACY
q
LESS THAN 10
s ACQUISITION TIME
q
WIDEBAND NOISE LESS THAN 20
Vrms
q
RELIABLE MONOLITHIC CONSTRUCTION
q
10
10
INPUT RESISTANCE
q
TTL-CMOS-COMPATIBLE LOGIC INPUT
SHC298
SHC298A
DESCRIPTION
The SHC298 and SHC298A are high-performance
monolithic sample/hold amplifiers featuring high DC
accuracy with fast acquisition times and a low droop
rate. Dynamic performance and holding performance
can be optimized with proper selection of the external
holding capacitor. With a 1000pF holding capacitor,
12-bit accuracy can be achieved with a 6
s acquisition
time. Droop rates less than 5mV/min are possible with
a 1
F holding capacitor.
These sample/holds will operate over a wide supply
voltage ranging from
5V to
18V with very little
change in performance. A separate Offset Adjust pin
is used to adjust the offset in either the Sample on the
Hold modes. The fully differential logic inputs have
low input current, and are compatible with TTL, 5V
CMOS, and CMOS logic families.
The SHC298AM is available in a hermetically sealed
8-pin TO-99 package and is specified over a tempera-
ture range from 25
C to +85
C. The SHC298JP and
SHC298JU are 8-pin plastic DIP and SOIC packaged
parts specified over 0
C to +70
C.
The SHC298AJP, specified over 0
C to +70
C, is
available in an 8-pin plastic DIP. The SHC298A grade
features improved gain and offset error, improved drift
over temperature, and faster acquisition time.
The SHC298 family is a price-performance bargain. It
is well suited for use with several 12-bit A/D convert-
ers in data acquisition systems, data distribution
systems, and analog delay circuits.
A
1
A
2
C
1
30k
2
Offset Adjust
3
8
7
Analog
Input
Logic
Logic
Reference
6
Hold
Capacitor
5
Output
Mode Control (S/H) Input
150
1977 Burr-Brown Corporation
PDS-373E
Printed in U.S.A. August, 1996
International Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111
Internet: http://www.burr-brown.com/ FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
2
SHC298/298A
SPECIFICATIONS
ELECTRICAL
At T
J
= +25
C,
15V supplies, 1000pF holding capacitor, 11.5V
V
IN
+11.5, R
L
= 10k
, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless
otherwise noted.
T
Same as specifications for SHC298AM, JP, JU.
NOTES: (1) These parameters guaranteed over a supply voltage range of
5V to =
18V. (2) Charge offset is sensitive to stray capacitive coupling between input
logic signals and the hold capacitor. 1pF, for instance, will create an additional 0.5mV step with a 5V logic swing and a 0.01
F hold capacitor. Magnitude of the
charge offset is inversely proportional to hold capacitor value.
SHC298AM, JP, JU
SHC298AJP
PARAMETER
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
ANALOG INPUT
Resistance
10
10
T
Bias Current
(1)
10
50
T
25
nA
DIGITAL INPUT
Pin 7
Pin 8
Circuit State
Mode Control Truth Table
0V
+2.4V
Sample (Track)
0V
+0.8V
Hold
+2.4V
+2.8V
Hold
+0.8V
+2.8V
Sample (Track)
Mode Control and Mode Control Reference Input Current
10
A
Differential Logic Threshold
0.8
1.4
2.4
V
TRANSFER CHARACTERISTICS
ACCURACY (+25
C)
Gain
+1
T
V/V
Gain Error
0.004
0.010
0.001
0.005
%
Input Voltage Offset (adjust to zero)
(1)
2
7
1
2
mV
Droop Rate
(1)
30
T
V/ms
Power Supply Rejection
25
100
T
T
V/V
ACCURACY DRIFT
Gain Drift
3
4
1
2
ppm/
C
Input Offset Drift
15
70
T
25
V/
C
Droop Rate at T
J
= +85
C
10
T
mV/ms
DYNAMIC CHARACTERISTICS
Aperture Time : Negative Input Step
200
T
ns
Positive Input Step
150
T
ns
Acquisition Time (C = 1000pF): to
0.1%, 10V Step
5
4
6
s
Sample/Hold Transient: Peak Amplitude
160
T
mV
Settling to 1mV
1
T
s
Feedthrough (Response to 10V Input Step)
0.007
0.004
% of 20V
OUTPUT
ANALOG OUTPUT
Voltage Range
11.5
T
V
Current Range
2
T
mA
Impedance (in Hold Mode)
0.5
4
T
T
POWER SUPPLY
Rate Voltage
15
T
VDC
Range
5
18
T
T
VDC
Current
(1)
4.5
6.5
T
T
mA
3
SHC298/298A
PIN CONFIGURATIONS
Mode Control (S/H) Input
Tab
8
1
2
6
5
3
4
+V
CC
Output
Hold Cap
Mode Control
Reference
V
CC
Analog
Input
Offset Adjust
24k
1k
+V
CC
Logic
7
Top View
TO-99
Top View
Plastic DIP/Small Outline
Offset
Adjust
1
2
3
4
8
7
6
5
Logic
Hold Capacitor
Output
Mode Control
Input
Mode Control
Reference
+V
CC
V
CC
Analog
Input
PACKAGE
DRAWING
TEMPERATURE
PRODUCT
PACKAGE
NUMBER
(1)
RANGE
SHC298AM
TO-99
001
25
C to +85
C
SHC298JP
8-Pin Plastic DIP
006
0
C to +70
C
SHC298JU
8-Lead SOIC
182
0
C to +70
C
SHC298AJP
8-Pin Plastic DIP
006
0
C to +70
C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
PACKAGE/ORDERING INFORMATION
Supply Voltage ..................................................................................
18V
Power Dissipation (Package Limitation) ........................................ 500mV
Junction Temperature, T
J MAX
AM ................................................................................................ 125
C
JP, JU .......................................................................................... 100
C
Operating Temperature Range ....................................... 25
C to +85
C
Storage Temperature Range ........................................ 65
C to +150
C
Input Voltage ....................................................... Equal to Supply Voltage
Logic-to-Logic Reference Differential Voltage
(1)
..................... +7V, 30V
Output Short Circuit Duration ...................................................... Indefinite
Hold Capacitor Short Circuit Duration ................................................. 10s
Lead Temperature (soldering, 10s) ................................................. 300
C
NOTE: (1) Although the differential voltage may not exceed the limits given,
the common-mode voltage on the logic pins may be equal to the supply
voltages without causing damage to the circuit. For proper logic operation,
however, one of the logic pins must always be at least 2V below the positive
supply and 3V above the negative supply.
ABSOLUTE MAXIMUM RATINGS
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
4
SHC298/298A
OUTPUT NOISE
10
Frequency (Hz)
100
10k
100k
1k
"Hold" Mode
160
140
120
100
80
60
40
20
0
Noise (nV/
Hz)
"Sample" Mode
ACQUISITION TIME
1
10
100
Time (s)
1000
0.001
Hold Capacitor (F)
0.01
0.1
1
V
IN
= 0V to 10V
T
J
= 25C
0.1%
0.01%
10
4
Hold Capacitor (F)
OUTPUT DROOP RATE
V/
T (V)
1
0.001
0.01
0.0001
0.1
10
0
10
1
10
2
10
3
T
J
= 0C
T
J
= 25C
T
J
= 125C
T
J
= 70C
SAMPLE-TO-HOLD
TRANSIENT SETTLING TIME
25
0
25
50
75
100
125
150
Junction Temperature (C)
50
2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
Time (ns)
0
+V
CC
= V
CC
= 15V
Settling to 1mV
0.01
Hold Capacitor (F)
CHARGE OFFSET
Hold Step (mV)
1
0.001
0.01
0.0001
0.1
100
10
1
0.1
V
IN
= 0V
T
J
= 25C
TYPICAL PERFORMANCE CURVES
At T
J
= +25
C,
15V supplies, 1000pF holding capacitor, 11.5V
V
IN
+11.5, R
L
= 10k
, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless
otherwise noted.
APERTURE TIME
25
0
25
50
75
100
125
150
Junction Temperature (C)
50
500
400
300
200
100
Time (ns)
0
V
OUT
mV
V
IN
= 10V
+V
CC
= V
CC
= 15V
Negative
Input Step
Positive
Input Step
5
SHC298/298A
10
100
1k
10k
100k
1M
Frequency (Hz)
FEEDTHROUGH REJECTION RATIO
130
120
110
100
90
80
70
60
50
Rejection Ratio (dB)
C
H
0.1F
C
H
= 0.01F
C
H
= 1000pF
+V
CC
= V
CC
= 15V
V
IN
= 10Vp-p
T
J
= 25C
INPUT BIAS CURRENT
Junction Temperature (C)
Current (nA)
25
20
15
10
5
0
5
10
15
50
25
100
0
25
50
75
125
150
POWER SUPPLY REJECTION
100
Frequency (Hz)
1k
100k
1M
10k
160
140
120
100
80
60
40
20
Rejection Ratio (dB)
T
J
= 25C
+V
CC
= V
CC
= 15V
V
OUT
= 0V
0
Positive Supply
Negative Supply
CHARGE OFFSET
Input Voltage (V)
15
15
10
10
5
0
5
T
J
= 55C
Hold Step (mV)
1.6
1.2
0.8
0.4
0
0.4
0.8
1.2
1.6
T
J
= 25C
T
J
= 125C
C
H
= 0.01F
T
J
= 25C
GAIN ERROR
Output Voltage (V)
Input-Output Voltage (mV)
0.3
15
15
10
10
5
0
5
0.3
0.2
0.1
0
0.1
0.2
Slope
0.0007%
T
J
= 25C
R
L
= 10k
Sample Mode
0.01
Input Slew Rate (V/ms)
DYNAMIC SAMPLING ERROR
Error (mV)
1000
1
10
0.1
100
100
10
1
0.1
+V
CC
= V
CC
= 15V
T
J
= 25C
3000pF
1F
0.1F
Hold Capacitor
0.01F
1000pF
TYPICAL PERFORMANCE CURVES
(CONT)
At T
J
= +25
C,
15V supplies, 1000pF holding capacitor, 11.5V
V
IN
+11.5, R
L
= 10k
, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless
otherwise noted.
6
SHC298/298A
CHARGE OFFSET
0.01
Logic Slew Rate (V/s)
0.1
10
100
1
3.5
3
2.5
2
1.5
1
0.5
0
Hold Step (mV)
C
H
= 0.01F
T
J
= 25C
V
IN
= 0V
0.5
PHASE AND GAIN
(Input to Output, Small Signal)
1k
Frequency (Hz)
10k
1M
10M
100k
5
0
5
10
Gain Input to Output (dB)
C
H
= 0
80
70
60
50
40
30
20
10
Input to Output Phase Delay ()
0
C
H
= 1000pF
C
H
= 0.01F
C
H
0.1F
C
H
= 0
C
H
= 0.01F
C
H
= 1000pF
TYPICAL PERFORMANCE CURVES
(CONT)
DISCUSSION OF
SPECIFICATIONS
THROUGHPUT NONLINEARITY
Throughput nonlinearity is defined as total Hold mode,
nonadjustable, input to output error caused by charge offset,
gain nonlinearity, 1ms of droop, feedthrough, and thermal
transients. It is the inaccuracy due to these errors which
cannot be corrected by offset and gain adjustments. Through-
put nonlinearity is tested with a 1000pF holding capacitor,
10V input changes, 10
s acquisition time, and 1ms Hold
time (see Figure 1).
GAIN ACCURACY
Gain Accuracy is the difference between input and output
voltage (when in the Sample mode) due to amplifier gain
errors.
DROOP RATE
Droop Rate is the voltage decay at the output when in the
Hold mode due to storage capacitor, FET switch leakage
currents, and output amplifier bias current.
FEEDTHROUGH
Feedthrough is the amount of the input voltage change that
appears at the output when the amplifier is in the Hold mode.
APERTURE TIME
Aperture Time is the time required to switch from Sample to
Hold. The time is measured from the 50% point of the mode
control transition to the time at which the output stops
tracking the input.
ACQUISITION TIME
Acquisition Time is the time required for the sample/hold
output to settle within a given error band of its final value
when the mode control is switched from Hold to Sample.
FIGURE 1. Sample/Hold Errors.
At T
J
= +25
C,
15V supplies, 1000pF holding capacitor, 11.5V
V
IN
+11.5, R
L
= 10k
, Logic Reference Voltage = 0V, and Logic Voltage = 2.5 V, unless
otherwise noted.
Control
Signal
Sample
Hold
Input
Voltage
Time
Output
Voltage
Aperture Time
Gain
Error
Actual
Acquisition
Time
Throughput
Error
Ideal
Time
Time
Offset Error
Sample
7
SHC298/298A
CHARGE OFFSET
Charge Offset is the offset that results from the charge
coupled through the gate capacitance of the switching FET.
This charge is coupled into the storage capacitor when the
FET is switched to the "hold" mode.
OPERATING INSTRUCTIONS
EXTERNAL CAPACITOR SELECTION
Capacitors with high insulation resistance and low dielectric
absorption, such as Teflon
, polystyrene or polypropylene
units, should be used as storage elements (polystyrene should
not be used above +85
C). Care should be taken in the
printed circuit layout to minimize AC and DC leakage
currents from the capacitor to reduce charge offset and
droop errors.
The value of the external capacitor determines the droop,
charge offset and acquisition time of the Sample/Hold. Both
droop and charge offset will vary linearly with capacitance
from the values given in the specification table for a 0.001
F
capacitor. With a capacitor of 0.01
F, the droop will reduce
to approximately 2.5
V/ms and the charge offset to approxi-
mately 1.5mV. The behavior of acquisition time with changes
in external capacitance is shown in the Typical Performance
Curves.
OFFSET ADJUSTMENT
The offset should be adjusted with the input grounded.
During the adjustment, the sample/hold should be switching
continuously between the Sample and the Hold mode. The
error should then be adjusted to zero when the unit is in the
Hold mode. In this way, charge offset as well as amplifier
offset will be adjusted. When a 0.001
F capacitor is used, it
will not be possible to adjust the full offset error at the
sample/hold. It should be adjusted elsewhere in the system.
APPLICATIONS
DATA ACQUISITION
The SHC298 may be used to hold data for conversion with
an analog-to-digital converter or used to provide Pulse
Amplitude Modulation (PAM) data output (see Figures 2
and 3).
DATA DISTRIBUTION
The SHC298 may be used to hold the output of a digital-to-
analog converter whose digital inputs are multiplexed (see
Figure 4).
TEST SYSTEMS
The SHC298 is also well suited for use in test systems to
acquire and hold data transients for human operators or for
the other parts of the test system such as comparators, digital
voltmeters, etc.
With a 0.1
F storage capacitor, the output may be held 10
seconds with less than 0.1% error. With a 1
F storage
capacitor, the output may be held more than 15 minutes with
less than 1% error.
CAPACITIVE LOADING
SHC298 is sensitive to capacitive loading on the output and
may oscillate. When driving long lines, a buffer should be
used.
HIGH SPEED DATA ACQUISITION
The minimum sample time for one channel in a data acqui-
sition system is usually considered to be the acquisition time
of the sample/hold plus the conversion time of the analog-to-
digital converter. If two or more sample/holds are used with
a high-speed multiplexer, the acquisition time of the sample/
hold can be virtually eliminated. While the first channel is in
hold and switched on to the ADC, the multiplexer may be
addressed to the next channel. The second sample/hold will
have acquired this data by the time the conversion is com-
plete. Then, the sample/holds reverse roles and another
channel is addressed (see Figure 5). For low-level systems,
and instrumentation amplifier and double-ended multiplexer
may be connected to the sample/hold inputs. The settling
time of the multiplexer, instrumentation amplifier, and
sample/hold can be eliminated from the channel conversion
time as before.
FIGURE 2. Data Acquisition.
FIGURE 3. PAM Output.
Mode Control Hold
Actual Input
PAM Output
0.1F
SHC298
0.005F
Storage
4
6
15VDC
0.1F
24k
1k
+15VDC
To A/D
Converter
PAM
Output
Mode
Control
7
2
1
5
3
8
Analog
Multiplexer
Analog
Inputs
Teflon, DuPont de Nemours
8
SHC298/298A
FIGURE 4. Data Distribution.
0.1F
SHC298
Storage
Capacitor
4
6
15VDC
0.1F
24k
1k
+15VDC
Channel 1
7
2
1
5
3
8
SHC298
4
6
15VDC
+15VDC
Channel 2
7
2
1
5
3
8
SHC298
4
6
+15VDC
Channel N
7
2
1
5
3
8
D/A
Converter
15VDC
Analog
Output
Offset
Adjust
Additional SHC298 Units
Digital
Inputs
Mode
Control
Logic
Digital
Inputs
SHC298
1000pF
6
3
5
8
SHC298
1000pF
6
3
5
8
(1)
(0)
High
Speed
Switch
A/D
Converter
B1
B2
B12
Digital
Output
Ch1
Ch2
ChN
MUX
Address
Analog
Input
Mode Control
1
2
FIGURE 5. "Ping-Pong" Sample Holds.
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