1
HA
LOGEN FREE
TM
LEAD FREE
CS
SK
DI
DO
VCC
RDY/BUSY
RESET
GND
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
RDY/BUSY
RESET
GND
1
2
3
4
8
7
6
5
RDY/BUSY
VCC
CS
SK
RESET
GND
DO
DI
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
RDY/
BUSY
RESET
GND
1
2
3
4
8
7
6
5
RDY/
BUSY
VCC
CS
SK
RESET
GND
DO
DI
CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM
FEATURES
s
SPI bus compatible
s
Low power CMOS technology
s
2.5V to 6.0V operation
s
Self-timed write cycle with auto-clear
s
Hardware reset pin
s
Hardware and software write protection
s
Commercial, industrial and automotive
temperature ranges
s
Power-up inadvertant write protection
s
RDY/
BSY
BSY
BSY
BSY
BSY
pin for end-of-write indication
s
1,000,000 program/erase cycles
s
100 year data retention
DESCRIPTION
The CAT64LC10/20/40 is a 1K/2K/4K-bit Serial EEPROM
which is configured as 64/128/256 registers by 16 bits.
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT64LC10/20/40 is
manufactured using Catalyst's advanced CMOS
EEPROM floating gate technology. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, SOIC and TSSOP packages.
BLOCK DIAGRAM
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W) TSSOP Package (U, Y)
PIN FUNCTIONS
Pin Name
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
V
CC
+2.5V to +6.0V Power Supply
GND
Ground
RESET
Reset
RDY/BUSY
Ready/BUSY Status
2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1021, Rev. B
SOIC Package (S, V) TSSOP Package (UR, YR)
64LC10/20/40 F02
VCC
ADDRESS
DECODER
MEMORY ARRAY
64/128/256 x 16
DATA
REGISTER
MODE DECODE
LOGIC
CLOCK
GENERATOR
OUTPUT
BUFFER
DO
SK
CS
DI
RESET
GND
RDY/BUSY
2
CAT64LC10/20/40
Doc. No. 1021, Rev. B
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. 55
C to +125
C
Storage Temperature ....................... 65
C to +150
C
Voltage on any Pin with
Respect to Ground
(1)
............ 2.0V to +V
CC
+2.0V
V
CC
with Respect to Ground ............... 2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25
C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300
C
Output Short Circuit Current
(2)
........................ 100 mA
*COMMENT
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max.
UnitsReference Tes
t Method
N
END
(3)
Endurance
1,000,000
Cycles/Byte
MIL-STD-883, Test Method 1033
T
DR
(3)
Data Retention
100
Years
MIL-STD-883, Test Method 1008
V
ZAP
(3)
ESD Susceptibility
2000
Volts
MIL-STD-883, Test Method 3015
I
LTH
(3)(4)
Latch-Up
100
mA
JEDEC Standard 17
CAPACITANCE (T
A
= 25
C, f= 1.0 MHz, V
CC
=6.0V)
Symbol
Test
Max.
Units
Conditions
C
I/O
(3)
Input/Output Capacitance (DO, RDY/
BSY
)
8
pF
V
I/O
= 0V
C
IN
(3)
Input Capacitance (
CS
, SK, DI, RESET)
6
pF
V
IN
= 0V
Note:
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+2.0V for periods of less than 20 ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V
CC
+1V.
3
CAT64LC10/20/40
Doc. No. 1021, Rev. B
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Note:
(1) V
OH
and V
OL
spec applies to READY/
BUSY
pin also
Limits
Sym.
Parameter
Min.
Typ.
Max.
UnitsTes
t Conditions
I
CC
Operating Current
2.5V
0.4
mA
f
SK
= 250 kHz
EWEN, EWDS, READ 6.0V
1
mA
f
SK
= 1 MHz
I
CCP
Program Current
2.5V
2
mA
6.0V
3
mA
I
SB
(1)
Standby Current
1
A
V
IN
= GND or V
CC
CS = V
CC
I
LI
Input Leakage Current
2
A
V
IN
= GND to V
CC
I
LO
Output Leakage Current
10
A
V
OUT
= GND to V
CC
V
IL
Low Level Input Voltage, DI
0.1
V
CC
x 0.3
V
V
IH
High Level Input Voltage, DI
V
CC
x 0.7
V
CC
+ 0.5
V
V
IL
Low Level Input Voltage,
0.1
V
CC
x 0.2
V
CS
, SK, RESET
V
IH
High Level Input Voltage,
V
CC
x 0.8
V
CC
+ 0.5
V
CS
, SK, RESET
V
OH
(1)
High Level Output Voltage
2.5V
V
CC
0.3
V
I
OH
= 10
A
6.0V
V
CC
0.3
V
I
OH
= 10
A
2.4
V
I
OH
= 400
A
V
OL
(1)
Low Level Output Voltage
2.5V
0.4
V
I
OL
= 10
A
6.0V
0.4
V
I
OL
= 2.1mA
4
CAT64LC10/20/40
Doc. No. 1021, Rev. B
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) This parameter is sampled but not 100% tested.
(3) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
WRITE CYCLE LIMIITS
Symbol
Parameter
Min.
Max.
Units
t
WR
Program Cycle Time
2.5V
10
ms
4.5V6.0V
5
A.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
t
CSS
CS
Setup Time
100
ns
t
CSH
CS
Hold Time
100
ns
t
DIS
DI Setup Time
200
ns
t
DIH
DI Hold Time
200
ns
t
PD1
Output Delay to 1
300
ns
t
PD0
Output Delay to 0
300
ns
t
HZ
(2)
Output Delay to High Impendance
500
ns
t
CSMIN
Minimum
CS
High Time
250
ns
t
SKHI
Minimum SK High Time
2.5V
1000
ns
4.5V6.0V
400
t
SKLOW
Minimum SK Low Time
2.5V
1000
ns
4.5V6.0V
400
t
SV
Output Delay to Status Valid
500
ns
f
SK
Maximum Clock Frequency
2.5V
250
kHz
4.5V6.0V
1000
t
RESS
Reset to
CS
Setup Time
0
ns
t
RESMIN
Minimum RESET High Time
250
ns
t
RESH
RESET to READY Hold Time
0
ns
t
RC
Write Recovery
100
ns
POWER-UP TIMING
(1)(3)
Symbol
Parameter
Min.
Max.
Units
t
PUR
Power-Up to Read Operation
10
s
t
PUW
Power-Up to Program Operation
1
ms
5
CAT64LC10/20/40
Doc. No. 1021, Rev. B
INSTRUCTION SET
Instruction
Opcode
Address
Data
Read
64LC10
10101000
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10101000
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10101000
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write
64LC10
10100100
A5 A4 A3 A2 A1 A0 0
0
D15 - D0
64LC20
10100100
A6 A5 A4 A3 A2 A1 A0
0
D15 - D0
64LC40
10100100
A7 A6 A5 A4 A3 A2 A1 A0
D15 - D0
Write Enable
10100011
X X X X X X X X
Write Disable
10100000
X X X X X X X X
[Write All Locations]
(1)
10100001
X X X X X X X X
D15D0
Figure 1. A.C. Testing Input/Output Waveform
(2)(3(4)
(C
L
= 100 pF)
Note:
(1)
(Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
(2)
Input Rise and Fall Times (10% to 90%) < 10 ns.
(3)
Input Pulse Levels = V
CC
x 0.2 and V
CC
x 0.8.
(4)
Input and Output Timing Reference = V
CC
x 0.3 and V
CC
x 0.7.
INPUT PULSE LEVELS
REFERENCE POINTS
VCC x 0.7
VCC x 0.3
VCC x 0.8
VCC x 0.2
6
CAT64LC10/20/40
Doc. No. 1021, Rev. B
DEVICE OPERATION
The CAT64LC10/20/40 is a 1K/2K/4K-bit nonvolatile
memory intended for use with all standard controllers.
The CAT64LC10/20/40 is organized in a 64/128/256 x
16 format. All instructions are based on an 8-bit format.
There are four 16-bit instructions: READ, WRITE, EWEN,
and EWDS. The CAT64LC10/20/40 operates on a single
power supply ranging from 2.5V to 6.0V and it has an on-
chip voltage generator to provide the high voltage needed
during a programming operation. Instructions, addresses
and data to be written are clocked into the DI pin on the
rising edge of the SK clock. The DO pin is normally in a
high impedance state except when outputting data in a
READ operation or outputting RDY/
BSY
status when
polled during a WRITE operation.
The format for all instructions sent to this device includes
a 4-bit start sequence, 1010, a 4-bit op code and an 8-
bit address field or dummy bits. For a WRITE operation,
Figure 2. Sychronous Data Timing
Figure 3. Read Instruction Timing
* Please check the instruction set table for address
SK
DI
CS
DO
tPD0,tPD1
tCSS
tDIS
tSKHI
tSKLOW
RESET
RDY/
BUSY
tRESS
tRC
tDIH
tCSH
tCSMIN
tHZ
tSV
tSV
tRESH
SK
DI
CS
DO
RESET
1
0
1
0
1
0
0
0
ADDRESS*
D15 D14
D1
D0
HIGH
RDY/
BUSY
7
CAT64LC10/20/40
Doc. No. 1021, Rev. B
a 16-bit data field is also required following the 8-bit
address field.
The CAT64LC10/20/40 requires an active LOW
CS
in
order to be selected. Each instruction must be preceded
by a HIGH-to-LOW transition of
CS
before the input of
the 4-bit start sequence. Prior to the 4-bit start sequence
(1010), the device will ignore inputs of all other logical
sequence.
Figure 4. Write Instruction Timing
Figure 5. Ready/
BUSY
BUSY
BUSY
BUSY
BUSY
Status Instruction Timing
Read
Upon receiving a READ command and address (clocked
into the DI pin), the DO pin will output data one t
PD
after
the falling edge of the 16th clock (the last bit of the
address field). The READ operation is not affected by
the RESET input.
Write
After receiving a WRITE op code, address and data, the
device goes into the AUTO-Clear cycle and then the
* Please check instruction set table for address
SK
DI
CS
DO
RESET
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
RDY/
BUSY
SK
DI
CS
DO
RESET
WRITE INSTRUCTION
NEXT INSTRUCTION
HIGH
LOW
RDY/
BUSY
8
CAT64LC10/20/40
Doc. No. 1021, Rev. B
WRITE cycle. The RDY/
BSY
pin will output the
BUSY
status (LOW) one t
SV
after the rising edge of the 32nd
clock (the last data bit) and will stay LOW until the write
cycle is complete. Then it will output a logical "1" until the
next WRITE cycle. The RDY/
BSY
output is not affected
by the input of
CS
.
An alternative to get RDY/
BSY
status is from the DO pin.
During a write cycle, asserting a LOW input to the
CS
pin
will cause the DO pin to output the RDY/
BSY
status.
Bringing
CS
HIGH will bring the DO pin back to a high
impedance state again. After the device has completed
a WRITE cycle, the DO pin will output a logical "1" when
the device is deselected. The rising edge of the first "1"
input on the DI pin will reset DO back to the high
impedance state again.
The WRITE operation can be halted anywhere in the
operation by the RESET input. If a RESET pulse occurs
during a WRITE operation, the device will abort the
operation and output a READY status.
NOTE: Data may be corrupted if a RESET occurs while
the device is
BUSY
. If the reset occurs before the
BUSY
period, no writing will be initiated. However, if RESET
occurs after the
BUSY
period, new data will have been
written over the old data.
Figure 6. RESET During
BUSY
BUSY
BUSY
BUSY
BUSY
Instruction Timing
Figure 7. EWEN Instruction Timing
5064 FHD F09
* Please check instruction set table for address
SK
DI
CS
DO
RESET
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
tWR
RDY/
BUSY
SK
DI
CS
DO
RESET
1
0
1
0
0
0
1
1
HIGH-Z
HIGH
RDY/
BUSY
9
CAT64LC10/20/40
Doc. No. 1021, Rev. B
RESET
The RESET pin, when set to HIGH, will reset or abort a
WRITE operation. When RESET is set to HIGH while the
WRITE instruction is being entered, the device will not
execute the WRITE instruction and will keep DO in High-
Z condition.
When RESET is set to HIGH, while the device is in a
clear/write cycle, the device will abort the operation and
will display READY status on the RDY/
BSY
pin and on
the DO pin if
CS
is low.
The RESET input affects only the WRITE and WRITE
ALL operations. It does not reset any other operations
such as READ, EWEN and EWDS.
ERASE/WRITE ENABLE and DISABLE
The CAT64LC10/20/40 powers up in the erase/write
disabled state. After power-up or while the device is in an
erase/write disabled state, any write operation must be
preceded by an execution of the EWEN instruction.
Once enabled, the device will stay enabled until an
EWDS has been executed or a power-down has occured.
The EWDS is used to prevent any inadvertent over-
writing of the data. The EWEN and EWDS instructions
have no affect on the READ operation and are not
affected by the RESET input.
Figure 8. EWDS Instruction Timing
SK
DI
CS
DO
RESET
1
0
1
0
0
0
0
0
HIGH-Z
HIGH
RDY/
BUSY
10
CAT64LC10/20/40
Doc. No. 1021, Rev. B
ORDERING INFORMATION
Notes:
(1) The device used in the above example is a 64LC10SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
P: PDIP
S: SOIC (JEDEC)
J: SOIC (JEDEC)
U: TSSOP
UR: TSSOP (Rotated)
L: PDIP (Lead free, Halogen free)
V: SOIC (JEDEC) (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
YR: TSSOP (Rotated) (Lead free, Halogen free)
11
CAT64LC10/20/40
Doc. No. 1021, Rev. B
PACKAGING INFORMATION
8-LEAD TSSOP (U)
7.72 TYP
4.16 TYP
(1.78 TYP)
0.42 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
-A-
-B-
3.2
6.4
A
B
C
0.2
8
5
3.0 + 0.1
4.4 + 0.1
ALL LEAD TIPS
PIN #1 IDENT.
1
4
ALL LEAD TIPS
1.1 MAX TYP
0.1 C
(0.9)
0.10 + 0.05 TYP
0.19 - 0.30 TYP
0.3 M A B S C S
0.65 TYP
SEE DETAIL A
0.09 - 0.20 TYP
0.6+0.1
SEATING PLANE
GAGE PLANE
0.25
0
o
- 8
o
DETAIL A
-C-
12
CAT64LC10/20/40
Doc. No. 1021, Rev. B
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
www.catalyst-semiconductor.com
Publication #:
1021
Revison:
B
Issue date:
9/3/04
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM
AE
2
TM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
REVISION HISTORY
Date
Rev.
Reason
9/3/2004
B
Added Green packages in all areas
Updated DC Operating Characteristics table & notes
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.
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