Document Outline
- CS4630
- Features
- Description
- ORDERING INFORMATION
- TABLE OF CONTENTS
- LIST OF FIGURES
- Contacting Cirrus Logic Support
- 1. CHARACTERISTICS/SPECIFICATIONS
- 2. OVERVIEW
- 3. SYSTEM ARCHITECTURES
- 4. HOST INTERFACE
- 5. SERIAL PORT CONFIGURATIONS
- 6. GAME PORT
- 7. EEPROM INTERFACE
- 8. GENERAL PURPOSE I/O PINS
- 9. ZV PORT SERIAL INTERFACE
- 10. CONSUMER IEC-958 DIGITAL INTERFACE (S/PDIF)
- 11. PCI POWER MANAGEMENT
- 12. PIN DESCRIPTION
- 13.PACKAGE OUTLINE
- 128L MQFP PACKAGE DRAWING
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
1
Copyright
Cirrus Logic, Inc. 1999
(All Rights Reserved)
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CS4630
Features
l
420 MIPs SLIMD
TM
DSP Architecture with
increased internal memory for greater
performance
l
Hardware acceleration for Microsoft
DirectSound
and DirectSound3D
Positional Audio
l
SensauraTM 3-D, 2 or 4 channel audio
l
EAXTM 1.0 enhanced environmental audio
standard
l
Unlimited-Voice Wavetable Synthesis with
Effects including DLS support
l
Acoustic Echo Cancellation Hardware
Acceleration for NetMeeting
TM
l
10 Band Graphic Equalization
l
High Quality Hardware Sample Rate
Conversion (90+ dB Dynamic Range)
l
PC/PCI, DDMA, and CrystalClear Legacy
Support (CCLS
TM
)
l
PCI 2.1 Compliant PCI Interface
l
Full duplex, 128 Stream DMA Interface with
Hardware Scatter/Gather Support
l
PCI Power Management (D0 through
D3
cold
), APM 1.2, and ACPI 1.0
l
Power Management Event (PME#)
Generation within D0-D3
cold
l
Dual AC `97 2.1 Codec Interface
l
Asynchronous Digital Serial
Interface (ZV Port)
l
S/PDIF Digital Input and Output
support for PCM and AC3
encoded 5.1 Channel Formats
l
DirectInput
TM
Joystick and MPU-
401 MIDI In/Out
l
3.3 V / 2.5 V Power Supply (5 V
tolerant I/O)
l
PC 98 and PC 99 Compliant
Description
The CS4630 is a high performance upgrade to the
CS4624 PCI audio accelerator. With support for legacy
compatibility modes, the CS4630 enables real mode
DOS compatibility within PCI-only audio subsystems.
This device, combined with application and driver
software, provides a complete system solution for
hardware acceleration of Microsoft's DirectSound,
DirectSound3D, DirectInput, and Wavetable Synthesis.
WDM drivers provide support for both Windows 98
and
Windows 2000
.
The CS4630 is based on the Cirrus Logic CrystalClear
TM
Stream Processor (SP) DSP core. The SP core is
optimized for digital audio processing, and is powerful
enough to handle complex signal processing tasks such
as Sensaura 3D, 4-channel output, and hardware
wavetable synthesis. The SP core is supported by a bus
mastering PCI interface and a built-in dedicated DMA
engine with hardware scatter-gather support. These
support functions ensure extremely efficient transfer of
audio data streams to and from host-based memory
buffers, providing a system solution with maximum
performance and minimal host CPU loading.
ORDERING INFORMATION
CS4630-CM 128-pin MQFP 14x20x2.85 mm
NOV `99
DS445PP1
CrystalClear
TM
SoundFusion
PCI Audio Accelerator
28-Stream
DMA Controller
with Hardware
Scatter/Gather
MPU-401
MIDI Interface
PCI
Interface
Joystick
In terface
PC/PCI &
CCLS Legacy
S/PDIF In
S/PDIF Out
ZV Port
Program
ROM
Parameter
RAM
SLIMD
SP Core
Sample
RAM
Program
RAM
Coefficient
ROM
Dual Codec
AC '97 2.1
Interface
Async. Serial
Port Interface
1
EGPIO
CS4630
2
DS445PP1
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS .................................................. 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
RECOMMENDED OPERATING CONDITIONS ....................................................................... 4
AC CHARACTERISTICS (PCI SIGNAL PINS ONLY) .............................................................. 5
DC CHARACTERISTICS.......................................................................................................... 6
PCI INTERFACE PINS ............................................................................................................. 7
AC '97 SERIAL INTERFACE TIMING ...................................................................................... 8
ZV PORT TIMING..................................................................................................................... 9
INDEPENDENT TIMING ENVIRONMENT ............................................................................. 10
EEPROM TIMING CHARACTERISTICS................................................................................ 11
2. OVERVIEW ................................................................................................... 12
2.1 Stream Processor DSP Core ........................................................................................... 13
2.2 Legacy Support ................................................................................................................ 13
3. SYSTEM ARCHITECTURES ...................................................................... 14
4. HOST INTERFACE ...................................................................................... 15
4.1 PCI bus Transactions ....................................................................................................... 15
4.2 Configuration Space ........................................................................................................ 17
4.3 Subsystem Vendor ID Fields ........................................................................................... 19
4.4 Dynamic Config Register ................................................................................................. 19
4.5 Interrupt Signal ................................................................................................................ 19
5. SERIAL PORT CONFIGURATIONS ......................................................... 20
6. GAME PORT ................................................................................................. 22
6.1 MIDI Port .......................................................................................................................... 22
6.2 Joystick Port ..................................................................................................................... 22
7. EEPROM INTERFACE ................................................................................ 23
8. GENERAL PURPOSE I/O PINS .................................................................. 24
8.1 EGPIO ............................................................................................................................. 24
9. ZV PORT SERIAL INTERFACE ................................................................ 24
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
CCLS, SLIMD, and CrystalClear are trademarks of Cirrus Logic, Inc.
DirectInput and DirectX are trademarks of Microsoft Corporation.
DirectSound, DirectSound3D, Windows 98 and Windows 2000 are registered trademarks of Microsoft Corporation.
EAX is a trademark of Creative Technology, Ltd.
Intel is a registered trademark of Intel.
NetMeeting is a trademark of Microsoft Corporation.
Sensaura is a trademark of Sensaura, Inc.
Sound Blaster Pro is a trademark of Creative Technology, Ltd.
SoundFusion is a registered trademark of Cirrus Logic, Inc.
All other names are trademarks, registered trademarks, or service marks of their respective companies.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance prod-
uct information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure
that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided
"AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for
infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copy-
rights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form
or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus
Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a
retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent
of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written
consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trade-
marks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service
marks can be found at http://www.cirrus.com.
CS4630
DS445PP1
3
10. CONSUMER IEC-958 DIGITAL INTERFACE (S/PDIF) ...................... 24
11. PCI POWER MANAGEMENT .................................................................. 26
11.1 D0 State ......................................................................................................................... 26
11.2 Dl State .......................................................................................................................... 26
11.3 D2 State ......................................................................................................................... 26
11.4 D3hot State .................................................................................................................... 26
11.5 D3
cold
State ................................................................................................................... 26
11.6 CS4630 PME# Assertion ............................................................................................... 27
11.6.1 ABITCLK ON ..................................................................................................... 27
11.6.2 ABITCLK OFF ................................................................................................... 27
11.7 On Card Vaux Switching Logic ...................................................................................... 27
12. PIN DESCRIPTION ............................................................................................................... 29
12.1 PCI Interface .................................................................................................................. 30
12.2 PCI Power Management Interface Pins ........................................................................ 31
12.3 External Interface Pins .................................................................................................. 32
12.4 Clock / Miscellaneous .................................................................................................... 33
12.5 Serial Codec Interface ................................................................................................... 34
12.6 ZV Port Serial Interface ................................................................................................. 35
12.7 Consumer Digital Audio I/O (S/PDIF) ............................................................................ 35
12.8 Asynchronous Serial Interface and Enhanced General Purpose I/O ............................ 36
13. PACKAGE OUTLINE ................................................................................ 37
LIST OF FIGURES
Figure 1.
AC Characteristics ...................................................................................................... 5
Figure 2.
PCI Timing Measurement Conditions ......................................................................... 7
Figure 3.
AC '97 Configuration Timing Diagram ........................................................................ 8
Figure 4.
ZV PORT .................................................................................................................... 9
Figure 5.
Independent Timing Configuration ........................................................................... 10
Figure 6.
EEPROM Timing ...................................................................................................... 11
Figure 7.
CS4630 Block Diagram ............................................................................................ 12
Figure 8.
AC `97 Codec Interface ............................................................................................ 14
Figure 9.
Portable Docking Station Scenario ........................................................................... 14
Figure 10. Host Interface Base Address Registers .................................................................... 15
Figure 11. AC `97 Codec Connection Diagram .......................................................................... 20
Figure 12. Dual AC `97 Codec Connection Diagram ................................................................. 21
Figure 13. Joystick Logic ........................................................................................................... 22
Figure 14. External EEPROM Connection ................................................................................. 23
Figure 15. EEPROM Read Sequence ....................................................................................... 23
Figure 16. ZV Port Clocking Format .......................................................................................... 24
Figure 17. IEC Consumer Interface Implementation Circuit ...................................................... 25
Figure 18. Optional Fiber Optic Circuit ...................................................................................... 25
Figure 19. On-Card 3.3Vaux Switching Logic ............................................................................ 28
CS4630
4
DS445PP1
1. CHARACTERISTICS/SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PCIGND = CGND = CRYGND = 0 V, all voltages
with respect to 0 V)
Notes: 1. Includes all power generated by AC and/or DC output loading.
2. The power supply pins are at recommended maximum values. XTALI & XTALO are at 3.6 V maximum.
3. At ambient temperatures above 70 C, total power dissipation must be limited to less than 0.4 Watts.
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(PCIGND = CGND = CRYGND = 0 V,
all voltages with respect to 0 V)
Specifications are subject to change without notice.
Parameter
Symbol
Min
Typ
Max
Unit
Power Supplies
PCIVDD
CVDD
CRYVDD
VDD5REF
-
-
-
-
-
-
-
-
4.6
TBD
4.6
5.5
V
V
V
V
Total Power Dissipation
(Note 1)
-
-
TBD
W
Input Current per Pin, DC (Except supply pins)
-
-
TBD
mA
Output current per pin, DC
-
-
TBD
mA
Input voltage
(Note 2)
TBD
-
TBD
V
Ambient temperature (power applied)
(Note 3)
-45
-
85
C
Storage temperature
-55
-
150
C
Parameter
Symbol
Min
Typ
Max
Unit
Power Supplies
PCIVDD
CVDD
CRYVDD
VDD5REF
3
2.25
3
3/4.75
3.3
2.5
3.3
3.3/5
3.6
2.75
3.6
3.6/5.25
V
V
V
V
Internal DSP Frequency
CS4630
-
-
140
MHz
Operating Ambient Temperature
T
A
0
25
70
C
CS4630
DS445PP1
5
AC CHARACTERISTICS (PCI SIGNAL PINS ONLY)
(T
A
= 0 to 70 C;
PCIVDD = CRYVDD = 3.3 V; CVDD = 2.5 V; VDD5REF = 5 V; PCIGND = CGND = CRYGND = 0 V;
Logic 0 = 0 V, Logic 1 = 3.3 V; Reference levels = 1.4 V; unless otherwise noted; (Note 4))
Notes: 4. Specifications guaranteed by characterization and not production testing.
5. Refer to V/I curves in Figure 1. Specification does not apply to PCICLK and RST# signals. Switching
Current High specification does not apply to SERR#, PME#, and INTA# which are open drain outputs.
6. Cumulative edge rate across specified range. Rise slew rates do not apply to open drain outputs.
7. Equation A: I
OH
= 11.9 * (Vout - 5.25) * (Vout + 2.45) for 3.3 V > Vout > 3.1 V
8. Equation B: I
OL
= 78.5 * Vout * (4.4 - Vout) for 0 V < Vout < 0.71 V
Parameter
Symbol
Min
Max
Unit
Switching Current High
(Note 5)
0 < Vout < 1.4
1.4 < Vout < 2.4
3.1 < Vout < 3.3
I
OH
-44
-
-
-
Note 7
mA
mA
Switching Current Low
(Note 5)
Vout > 2.2
2.2 > Vout > 0.55
0.71 > Vout > 0
I
OL
95
Vout/0.023
-
-
-
Note 8
mA
mA
Low Clamp Current
-5 < Vin < -1
I
CL
-
mA
Output rise slew rate
0.4 V - 2.4 V load
(Note 6)
slewr
1
5
V/ns
Output fall slew rate
2.4 V - 0.4 V load
(Note 6)
slewf
1
5
V/ns
Pull Up
Equation A:
3.3
2.4
voltage
1.4
DC
drive point
AC drive
point
I
= 11.9*(Vout-5.25)*(Vout+2.45)
for 3.3V > Vout > 3.1V
OH
test
point
-2
-44
Current (mA)
-176
Pull Down
Equation B:
3.3
2.2
0.55
voltage
DC drive
point
I
= 78.5*Vout*(4.4-Vout)
for 0V < Vout < 0.71V
OL
AC drive
point
test
point
3, 6
95
380
Current (mA)
Figure 1. AC Characteristics
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