128-Macrocell MAX
EPLD
CY7C342B
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-03014 Rev. *A
Revised April 8, 2002
Features
128 macrocells in eight logic array blocks (LABs)
Eight dedicated inputs, 52 bidirectional I/O pins
Programmable interconnect array
Advanced 0.65-micron CMOS technology to increase
performance
Available in 68-pin HLCC, PLCC, and PGA packages
Functional Description
The CY7C342B is an Erasable Programmable Logic Device
(EPLD) in which CMOS EPROM cells are used to configure
logic functions within the device. The MAX
architecture is
100% user-configurable, allowing the device to accommodate
a variety of independent logic functions.
The 128 macrocells in the CY7C342B are divided into eight
LABs, 16 per LAB. There are 256 expander product terms, 32
per LAB, to be used and shared by the macrocells within each
LAB.
Each LAB is interconnected with a programmable interconnect
array, allowing all signals to be routed throughout the chip.
The speed and density of the CY7C342B allows it to be used in a
wide range of applications, from replacement of large amounts of
7400-series TTL logic, to complex controllers and multifunction
chips. With greater than 25 times the functionality of 20-pin PLDs,
the CY7C342B allows the replacement of over 50 TTL devices. By
replacing large amounts of logic, the CY7C342B reduces board
space, part count, and increases system reliability.
MACROCELL 101
MACROCELL 100
MACROCELL 99
MACROCELL 98
MACROCELL 97
Logic Block Diagram
MACROCELL 85
MACROCELL 84
MACROCELL 83
MACROCELL 82
MACROCELL 81
MACROCELL 33
MACROCELL 34
MACROCELL 35
MACROCELL 36
MACROCELL 37
MACROCELL 17
MACROCELL 18
MACROCELL 19
MACROCELL 20
MACROCELL 21
MACROCELL 1
MACROCELL 2
MACROCELL 3
MACROCELL 4
MACROCELL 5
MACROCELL 6
MACROCELL 7
MACROCELL 8
MACROCELL 121128
MACROCELL 102112
MACROCELL 8696
MACROCELL 3848
MACROCELL 2232
MACROCELL 916
SYSTEM CLOCK
P
I
A
INPUT
(A7)
68
INPUT
(A8)
66
INPUT
(L6)
36
INPUT
(K6)
35
(B8) 65
(A9) 64
(B9) 63
(A10) 62
(B10) 61
(B11) 60
(C11) 59
(C10) 58
(D11) 57
(D10) 56
(E11) 55
(F11) 53
(F10) 52
(G11) 51
(H11) 49
(H10) 48
(J11) 47
(J10) 46
(K11) 45
(K10) 44
(L10) 43
(L9) 42
(K9) 41
(L8) 40
(K8) 39
(L7) 38
4 (A5)
5 (B4)
6 (A4)
7 (B3)
8 (A3)
9 (A2)
10 (B2)
11 (B1)
12 (C2)
13 (C1)
14 (D2)
15 (D1)
17 (E1)
18 (F2)
19 (F1)
21 (G1)
22 (H2)
23 (H1)
24 (J2)
25 (J1)
26 (K1)
27 (K2)
28 (L2)
29 (K3)
30 (L3)
31 (K4)
LAB H
LAB G
LAB F
LAB E
LAB A
LAB B
LAB C
LAB D
3, 20, 37, 54 (B5, G2, K7, E10)
16, 33, 50, 67 (E2, K5, G10, B7)
V
CC
GND
() PERTAIN TO 68-PIN PGA PACKAGE
1 (B6)
INPUT/CLK
2 (A6)
INPUT
32 (L4)
INPUT
34 (L5)
INPUT
MACROCELL 120
MACROCELL 119
MACROCELL 118
MACROCELL 117
MACROCELL 116
MACROCELL 115
MACROCELL 114
MACROCELL 113
MACROCELL 7380
MACROCELL 72
MACROCELL 71
MACROCELL 70
MACROCELL 69
MACROCELL 68
MACROCELL 67
MACROCELL 66
MACROCELL 65
MACROCELL 5764
MACROCELL 49
MACROCELL 50
MACROCELL 51
MACROCELL 52
MACROCELL 53
MACROCELL 54
MACROCELL 55
MACROCELL 56
CY7C342B
Document #: 38-03014 Rev. *A
Page 2 of 14
Selection Guide
7C342B-15
7C342B-20
7C342B-25
7C342B-30
7C342B-35
Unit
Maximum Access Time
15
20
25
30
35
ns
Pin Configurations
I/O
Top View
HLCC, PLCC
7
6
4
5
3
11
12
10
9
8
43
42
44
45
46
21
22
24
23
25
13
14
41
40
2
1
26 27
18
19
17
16
15
20
28 29
31
30
32 33
36
35
37 38 39
34
52
51
49
50
48
47
V
CC
53
54
55
60
58
59
57
56
66 65
63
64
62
68 67
61
I/O
INP
U
T
INP
U
T
/
CLK
INP
U
T
GND
INP
U
T
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
V
CC
INP
U
T
INP
U
T
GND
INP
U
T
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INP
U
T
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
I/O
I/O
V
CC
I/O
INPUT/
CLK
INPUT
GND
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
INPUT
INPUT
GND
INPUT
I/O
INPUT
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
V
CC
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PGA
Bottom View
I/O
INPUT INPUT
I/O
I/O
I/O
I/O
I/O
I/O
L
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
7C342B
7C342B
CY7C342B
Document #: 38-03014 Rev. *A
Page 3 of 14
Logic Array Blocks
There are eight logic array blocks in the CY7C342B. Each LAB
consists of a macrocell array containing 16 macrocells, an
expander product term array containing 32 expanders, and an
I/O block. The LAB is fed by the programmable interconnect
array and the dedicated input bus. All macrocell feedbacks go
to the macrocell array, the expander array, and the program-
mable interconnect array. Expanders feed themselves and the
macrocell array. All I/O feedbacks go to the programmable
interconnect array so that they may be accessed by macrocells
in other LABs as well as the macrocells in the LAB in which
they are situated.
Externally, the CY7C342B provides eight dedicated inputs,
one of which may be used as a system clock. There are 52 I/O
pins that may be individually configured for input, output, or
bidirectional data flow.
Programmable Interconnect Array
The Programmable Interconnect Array (PIA) solves inter-
connect limitations by routing only the signals needed by each
logic array block. The inputs to the PIA are the outputs of every
macrocell within the device and the I/O pin feedback of every
pin on the device.
Unlike masked or programmable gate arrays, which induce
variable delay dependent on routing, the PIA has a fixed delay.
This eliminates undesired skews among logic signals that may
cause glitches in internal or external logic. The fixed delay,
regardless of programmable interconnect array configuration,
simplifies design by assuring that internal signal skews or
races are avoided. The result is ease of design implemen-
tation, often in a signal pass, without the multiple internal logic
placement and routing iterations required for a programmable
gate array to achieve design timing objectives.
Timing Delays
Timing delays within the CY7C342B may be easily determined
using Warp
, Warp ProfessionalTM, or Warp EnterpriseTM
software by the model shown in Figure 1. The CY7C342B has
fixed internal delays, allowing the user to determine the
worst-case timing delays for any design.
Design Recommendations
Operation of the devices described herein with conditions
above those listed under "Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other
conditions above those indicated in the operational sections of
this datasheet is not implied. Exposure to absolute maximum
ratings conditions for extended periods of time may affect
device reliability. The CY7C342B contains circuitry to protect
device pins from high static voltages or electric fields, but
normal precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages.
For proper operation, input and output pins must be
constrained to the range GND < (V
IN
or V
OUT
) < V
CC
. Unused
inputs must always be tied to an appropriate logic level
(either V
CC
or GND). Each set of V
CC
and GND pins must
be connected together directly at the device. Power supply
decoupling capacitors of at least 0.2
F must be connected
between V
CC
and GND. For the most effective decoupling,
each V
CC
pin should be separately decoupled to GND
directly at the device. Decoupling capacitors should have
good frequency response, such as monolithic ceramic types
have.
LOGIC ARRAY
CONTROL DELAY
t
LAC
EXPANDER
DELAY
t
EXP
CLOCK
DELAY
t
IC
t
RD
t
COMB
t
LATCH
INPUT
DELAY
t
IN
REGISTER
OUTPUT
DELAY
t
OD
t
XZ
t
ZX
LOGIC ARRAY
DELAY
t
LAD
FEEDBACK
DELAY
t
FD
OUTPUT
INPUT
SYSTEM CLOCK DELAY t
ICS
t
RH
t
RSU
t
PRE
t
CLR
PIA
DELAY
t
PIA
I/O DELAY
t
IO
Figure 1. CY7C342B Internal Timing Model
CY7C342B
Document #: 38-03014 Rev. *A
Page 4 of 14
Design Security
The CY7C342B contains a programmable design security
feature that controls the access to the data programmed into
the device. If this programmable feature is used, a proprietary
design implemented in the device cannot be copied or
retrieved. This enables a high level of design control to be
obtained since programmed data within EPROM cells is
invisible. The bit that controls this function, along with all other
program data, may be reset simply by erasing the entire
device.
The CY7C342B is fully functionally tested and guaranteed
through complete testing of each programmable EPROM bit
and all internal logic elements thus ensuring 100%
programming yield.
The erasable nature of these devices allows test programs to
be used and erased during early stages of the production flow.
The devices also contain on-board logic test circuitry to allow
verification of function and AC specification once encapsu-
lated in non-windowed packages.
Timing Considerations
Unless otherwise stated, propagation delays do not include
expanders. When using expanders, add the maximum
expander delay t
EXP
to the overall delay. Similarly, there is an
additional t
PIA
delay for an input from an I/O pin when
compared to a signal from straight input pin.
When calculating synchronous frequencies, use t
SU
if all
inputs are on dedicated input pins. When expander logic is
used in the data path, add the appropriate maximum expander
delay, t
EXP
to t
S1
. Determine which of 1/(t
WH
+ t
WL
), 1/t
CO1
,
or 1/(t
EXP
+ t
S1
) is the lowest frequency. The lowest of these
frequencies is the maximum data path frequency for the
synchronous configuration.
When calculating external asynchronous frequencies, use
t
AS1
if all inputs are on the dedicated input pins.
When expander logic is used in the data path, add the appro-
priate maximum expander delay, t
EXP
to t
AS1
. Determine
which of 1/(t
AWH
+ t
AWL
), 1/t
ACO1
, or 1/(t
EXP
+ t
AS1
) is the
lowest frequency. The lowest of these frequencies is the
maximum data path frequency for the asynchronous config-
uration.
The parameter t
OH
indicates the system compatibility of this
device when driving other synchronous logic with positive
input hold times, which is controlled by the same
synchronous clock. If t
OH
is greater than the minimum
required input hold time of the subsequent synchronous
logic, then the devices are guaranteed to function properly
with a common synchronous clock under worst-case
environmental and supply voltage conditions.
Typical I
CC
vs. f
MAX
400
300
200
100
1 kHz
10 kHz
100 kHz
1 MHz
I
CC
MAXIMUM FREQUENCY
10 MHz
0
50 MHz
100 Hz
AC
T
I
VE
(m
A)
T
y
p.
V
CC
= 5.0V
Room Temp.
Output Drive Current
0
1
2
3
4
I
OUTP
UT
CURRE
NT (m
A
)
TY
P
I
CA
L
V
O
OUTPUT VOLTAGE (V)
250
200
150
100
50
5
O
I
OH
I
OL
V
CC
= 5.0V
Room Temp.
CY7C342B
Document #: 38-03014 Rev. *A
Page 5 of 14
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................ 65
C to +135
C
Ambient Temperature with
Power Applied............................................ 65
C to +135
C
Maximum Junction Temperature
(under bias).................................................................. 150
C
Supply Voltage to Ground Potential ............2.0V to +7.0V
[1]
DC Output Current per Pin
[1]
................... 25 mA to +25 mA
DC Input Voltage
[1]
.........................................2.0V to +7.0V
Operating Range
Range
Ambient Temperature
V
CC
Commercial
0
C to +70
C
5V
5%
Industrial
40
C to +85
C
5V
10%
Electrical Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
V
CC
Supply Voltage
Maximum V
CC
rise time is 10 ms
4.75(4.5)
5.25(5.5)
V
V
OH
Output HIGH Voltage
I
OH
= 4 mA DC
[2]
2.4
V
V
OL
Output LOW Voltage
I
OL
= 8 mA DC
[2]
0.45
V
V
IH
Input HIGH Voltage
2.0
V
CC
+ 0.3
V
V
IL
Input LOW Voltage
0.3
0.8
V
I
IX
Input Current
V
I
= V
CC
or ground
10
+10
A
I
OZ
Output Leakage Current
V
O
= V
CC
or ground
40
+40
A
t
R
Recommended Input Rise Time
100
ns
t
F
Recommended Input Fall Time
100
ns
Capacitance
Parameter
Description
Test Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V, f = 1.0 MHz
10
pF
C
OUT
Output Capacitance
V
OUT
= 0V, f = 1.0 MHz
20
pF
AC Test Loads and Waveforms
Notes:
1.
Minimum DC input is 0.3V. During transactions, input may undershoot to 2.0V or overshoot to 7.0V for input currents less then 100 mA and periods shorter
than 20 ns.
2.
The I
OH
parameter refers to high-level TTL output current; the I
OL
parameter refers to low-level TTL output current.
3.0V
5V
OUTPUT
R1 464
R2
250
50 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
6 ns
6 ns
5V
OUTPUT
R1 464
R2
250
5 pF
INCLUDING
JIG AND
SCOPE
(a)
(b)
OUTPUT
1.75V
Equivalent to:
TH
VENIN EQUIVALENT (commercial/military)
ALL INPUT PULSES
163
CY7C342B
Document #: 38-03014 Rev. *A
Page 6 of 14
Commercial and Industrial External Synchronous Switching Characteristics
Over Operating Range
Parameter
Description
7C342B-15
7C342B-20
Unit
Min.
Max.
Min.
Max.
t
PD1
Dedicated Input to Combinatorial Output Delay
[3]
15
20
ns
t
PD2
I/O Input to Combinatorial Output Delay
[3]
25
33
ns
t
SU
Global Clock Set-Up time
10
13
ns
t
CO1
Synchronous Clock Input to Output Delay
[3]
8
9
ns
t
H
Input Hold Time from Synchronous Clock Input
0
0
ns
t
WH
Synchronous Clock Input HIGH Time
5
7
ns
t
WL
Synchronous Clock Input LOW Time
5
7
ns
f
MAX
Maximum Register Toggle Frequency
[4]
100
71.4
MHz
t
CNT
Minimum Global Clock Period
12
15
ns
f
CNT
Maximum Internal Global Clock Frequency
[5]
83.3
66.7
MHZ
Commercial and Industrial External Synchronous Switching Characteristics
Over Operating Range
Parameter
Description
7C342B-25
7C342B-30
7C342B-35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
t
PD1
Dedicated Input to Combinatorial Output Delay
[3]
25
30
35
ns
t
PD2
I/O Input to Combinatorial Output Delay
[3]
40
45
55
ns
t
SU
Global Clock Set-Up time
15
20
25
ns
t
CO1
Synchronous Clock Input to Output Delay
[3]
14
16
20
ns
t
H
Input Hold Time from Synchronous Clock Input
0
0
0
ns
t
WH
Synchronous Clock Input HIGH Time
8
10
12.5
ns
t
WL
Synchronous Clock Input LOW Time
8
10
12.5
ns
f
MAX
Maximum Register Toggle Frequency
[4]
62.5
50
40
MHz
t
CNT
Minimum Global Clock Period
20
25
30
ns
t
ODH
Output Data Hold Time After clock
2
2
2
ns
f
CNT
Maximum Internal Global Clock Frequency
[5]
50
40
33.3
MHz
Commercial and Industrial External Asynchronous Switching Characteristics
Over Operating Range
Parameter
Description
7C342B-15
7C342B20
Unit
Min.
Max.
Min.
Max.
t
ACO1
Asynchronous Clock Input to Output Delay
[3]
15
20
ns
t
AS1
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input
[6]
5
6
ns
t
AH
Input Hold Time from Asynchronous Clock Input
5
6
ns
t
AWH
Asynchronous Clock Input HIGH Time
[6]
5
7
ns
t
AWL
Asynchronous Clock Input LOW Time
[6]
5
7
ns
t
ACNT
Minimum Internal Array Clock Frequency
12
15
ns
f
ACNT
Maximum Internal Array Clock Frequency
[5]
83.3
66.7
MHz
t
ACO1
Asynchronous Clock Input to Output Delay
[3]
25
30
t
AS1
Dedicated Input or Feedback Set-Up Time to Asynchronous Clock Input
[5]
5
6
10
t
AH
Input Hold Time from Asynchronous Clock Input
6
8
10
Notes:
3.
C1 = 35 pF.
4.
The f
MAX
values represent the highest frequency for pipeline data.
5.
This parameter is measured with a 16-bit counter programmed into each LAB
6.
This parameter is measured with a positive-edge triggered clock at the register. For negative edge triggering, the t
AWH
and t
AWL
parameters must be swapped.
CY7C342B
Document #: 38-03014 Rev. *A
Page 7 of 14
t
AWH
Asynchronous Clock Input HIGH Time
[5]
11
14
16
t
AWL
Asynchronous Clock Input LOW Time
[5]
9
11
14
t
ACNT
Minimum Internal Array Clock Frequency
20
25
f
ACNT
Maximum Internal Array Clock Frequency
[5]
50
40
33.3
Commercial and Industrial External Asynchronous Switching Characteristics
Over Operating Range (continued)
Parameter
Description
7C342B-15
7C342B20
Unit
Min.
Max.
Min.
Max.
Commercial and Industrial Typical Internal Switching Characteristics
Over Operating Range
Parameter
Description
7C342B-15
7C342B-20
Unit
Min.
Max.
Min.
Max.
t
IN
Dedicated Input Pad and Buffer Delay
3
4
ns
t
IO
I/O Input Pad and Buffer Delay
3
4
ns
t
EXP
Expander Array Delay
8
10
ns
t
LAD
Logic Array Data Delay
8
12
ns
t
LAC
Logic Array Control Delay
5
5
ns
t
OD
Output Buffer and Pad Delay
[3]
3
3
ns
t
ZX
[8]
Output Buffer Enable Delay
[3]
5
5
ns
t
XZ
Output Buffer Disable Delay
[7]
5
5
ns
t
RSU
Register Set-Up Time Relative to Clock Signal at Register
2
1
ns
t
RH
Register Hold Time Relative to Clock Signal at Register
7
10
ns
t
LATCH
Flow Through Latch Delay
1
1
ns
t
RD
Register Delay
1
1
ns
t
COMB
[9]
Transparent Mode Delay
1
1
ns
t
IC
Asynchronous Clock Logic Delay
6
8
ns
t
ICS
Synchronous Clock Delay
0
0
ns
t
FD
Feedback Delay
1
1
ns
t
PRE
Asynchronous Register Preset Time
3
3
ns
t
CLR
Asynchronous Register Clear Time
3
3
ns
t
PIA
Programmable Interconnect Array Delay Time
10
13
ns
t
IN
Dedicated Input Pad and Buffer Delay
5
7
t
IO
I/O Input Pad and Buffer Delay
6
6
t
EXP
Expander Array Delay
12
14
t
LAD
Logic Array Data Delay
12
14
t
LAC
Logic Array Control Delay
10
12
t
OD
Output Buffer and Pad Delay
[3]
5
5
t
ZX
[8]
Output Buffer Enable Delay
[3]
10
11
t
XZ
Output Buffer Disable Delay
[7]
10
11
t
RSU
Register Set-Up Time Relative to Clock Signal at Register
6
8
10
t
RH
Register Hold Time Relative to Clock Signal at Register
4
6
8
t
LATCH
Flow Through Latch Delay
3
4
t
RD
Register Delay
1
2
Notes:
7.
C1 = 5 pF.
8.
Sample tested only for an output change of 500 mV.
CY7C342B
Document #: 38-03014 Rev. *A
Page 8 of 14
Commercial and Industrial Typical Internal Switching Characteristics
Over Operating Range (continued)
Parameter
Description
7C342B-25
7C342B-30
7C342B-35
Unit
Min.
Max.
Min.
Max.
Min.
Max.
t
COMB
[9]
Transparent Mode Delay
3
4
4
ns
t
IC
Asynchronous Clock Logic Delay
14
16
16
ns
t
ICS
Synchronous Clock Delay
3
2
1
ns
t
FD
Feedback Delay
1
1
2
ns
t
PRE
Asynchronous Register Preset Time
5
6
7
ns
t
CLR
Asynchronous Register Clear Time
5
6
7
ns
t
PIA
Programmable Interconnect Array Delay Time
14
16
20
ns
Switching Waveforms
External Combinatorial
DEDICATED INPUT/
I/O INPUT
COMBINATORIAL
OUTPUT
t
PD1
/t
PD2
t
WL
t
SU
t
H
LOGIC ARRAY
t
WH
External Synchronous
CLOCK AT REGISTER
SYNCHRONOUS
SYNCHRONOUS
LOGIC ARRAY
DATA FROM
REGISTERED
CLOCK PIN
OUTPUTS
t
CO1
External Asynchronous
t
AH
t
AS1
t
AWH
t
AWL
DEDICATED INPUTS OR
REGISTERED FEEDBACK
ASYNCHRONOUS
CLOCK INPUT
Note:
9.
This specification guarantees the maximum combinatorial delay associated with the macrocell register bypass when the macrocell is configured for combina-
torial operation.
CY7C342B
Document #: 38-03014 Rev. *A
Page 9 of 14
Switching Waveforms
(continued)
t
IN
IO
t
EXP
t
LAC
, t
LAD
t
COMB
t
OD
INPUT PIN
I/O PIN
LOGIC ARRAY
LOGIC ARRAY
OUTPUT
INPUT
ARRAY DELAY
EXPANDER
OUTPUT
PIN
t
Internal Combinatorial
Internal Synchronous
t
XZ
t
ZX
t
OD
HIGH IMPEDANCE
CLOCK FROM
LOGIC ARRAY
LOGIC ARRAY
DATA FROM
OUTPUT PIN
t
RD
STATE
Internal Asynchronous
t
IO
t
AWH
t
AWL
t
F
t
IN
t
IC
t
RSU
t
RH
t
RD
,t
LATCH
t
FD
t
CLR
,t
PRE
t
FD
CLOCK PIN
LOGIC ARRAY
LOGIC ARRAY
CLOCK FROM
DATA FROM
CLOCK INTO
LOGIC ARRAY
REGISTER OUTPUT
TO ANOTHER LAB
t
PIA
TO LOCAL LAB
REGISTER OUTPUT
LOGIC ARRAY
t
R
CY7C342B
Document #: 38-03014 Rev. *A
Page 10 of 14
Switching Waveforms
(continued)
t
IN
t
ICS
t
RSU
t
RH
SYSTEM CLOCK
AT REGISTER
DATA FROM
LOGIC ARRAY
Internal Synchronous
SYSTEM CLOCK PIN
Ordering Information
Speed (ns)
Ordering Code
Package Name
Package Type
Operating Range
15
CY7C342B-15JC/JI
J81
68-lead Plastic Leaded Chip Carrier
Commercial/
Industrial
20
CY7C342B-20JC/JI
J81
68-lead Plastic Leaded Chip Carrier
Commercial/
Industrial
25
CY7C342B-25HC/HI
H81
68-pin Windowed Leaded Chip Carrier
Commercial/
Industrial
CY7C342B-25JC/JI
J81
68-lead Plastic Leaded Chip Carrier
CY7C342B-25RC/RI
R68
68-pin Windowed Ceramic Pin Grid Array
30
CY7C342B-30JC/JI
J81
68-lead Plastic Leaded Chip Carrier
Commercial/
Industrial
35
CY7C342B-35JC/JI
J81
68-lead Plastic Leaded Chip Carrier
Commercial/
Industrial
CY7C342B-35RJ/RI
R68
68-pin Windowed Ceramic Pin Grid Array
CY7C342B
Document #: 38-03014 Rev. *A
Page 11 of 14
Package Diagrams
68-pin Windowed Leaded Chip Carrier H81
51-80080
CY7C342B
Document #: 38-03014 Rev. *A
Page 12 of 14
Package Diagrams
(continued)
68-lead Plastic Leaded Chip Carrier J81
51-85005-A
CY7C342B
Document #: 38-03014 Rev. *A
Page 13 of 14
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
MAX and Warp are registered trademarks and Warp Professional and Warp Enterprise are trademarks of Cypress Semiconductor
Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.
Package Diagrams
(continued)
68-Pin Windowed PGA Ceramic R68
51-80099-*A
CY7C342B
Document #: 38-03014 Rev. *A
Page 14 of 14
Document Title: CY7C342B 128-Macrocell MAX
EPLD
Document Number: 38-03014
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
106314
04/25/01
SZV
Change from Spec number: 38-00119 to 38-03014
*A
113612
04/11/02
OOR
PGA package diagram dimensions were updated
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