Flash-erasable Reprogrammable
CMOS PAL
Device
PALCE22V10
PALCE22V10 is a replacement device for
PALC22V10, PALC22V10B, and PALC22V10D.
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-03027 Rev. *B
Revised April 9, 2004
Features
Low power
-- 90 mA max. commercial (10 ns)
-- 130 mA max. commercial (5 ns)
CMOS Flash EPROM technology for electrical erasabil-
ity and reprogrammability
Variable product terms
-- 2 (8 through 16) product terms
User-programmable macrocell
-- Output polarity control
-- Individually selectable for registered or combina-
torial operation
Up to 22 input terms and 10 outputs
DIP, LCC, and PLCC available
-- 5 ns commercial version
4 ns t
CO
3 ns t
S
5 ns t
PD
181-MHz state machine
-- 10 ns military and industrial versions
7 ns t
CO
6 ns t
S
10 ns t
PD
110-MHz state machine
-- 15-ns commercial, industrial, and military versions
-- 25-ns commercial, industrial, and military versions
High reliability
-- Proven Flash EPROM technology
-- 100% programming and functional testing
Logic Block Diagram (PDIP/CDIP)
Pin Configuration
PLCC
Top View
Macrocell
8
10
12
14
16
16
14
12
10
8
11
10
9
8
7
6
5
4
3
2
1
12
13
14
15
16
17
18
19
20
21
22
23
24
Preset
PROGRAMMABLE
AND ARRAY
(132 X 44)
I
I
I
I
I
I
I
I
I
I
CP/I
VSS
I
I/O9
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
VCC
Reset
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
Macrocell
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
2
3
4
5
6
7
I
9
I
CP/I
V
I/
O
I/
O
8
I/
O
I/
O
I
V
I
I
SS
0
1
CC
N/C
LCC
Top View
5
6
7
8
9
10
11
4 3 2
282726
12131415161718
25
24
23
22
21
20
19
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
2
3
4
5
6
7
I
9
I
CP
/I
V
I/O
I/O
8
I/O
I/O
I
V
I
I
SS
0
1
CC
1
N/C
NC
NC
NC
NC
NC
NC
25
24
23
22
21
20
19
5
6
7
8
9
10
11
121314 1516 1718
4 3 2
2827 26
1
PALCE22V10
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03027 Rev. *B
Page 2 of 13
Functional Description
The Cypress PALCE22V10 is a CMOS Flash-erasable
second-generation programmable array logic device. It is
implemented with the familiar sum-of-products (AND-OR)
logic structure and the programmable macrocell.
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP,
a 300-mil cerDIP, a 28-lead square ceramic leadless chip
carrier, a 28-lead square plastic leaded chip carrier, and
provides up to 22 inputs and 10 outputs. The PALCE22V10
can be electrically erased and reprogrammed. The program-
mable macrocell provides the capability of defining the archi-
tecture of each output individually. Each of the ten potential
outputs may be specified as "registered" or "combinatorial."
Polarity of each output may also be individually selected,
allowing complete flexibility of output configuration. Further
configurability is provided through "array" configurable "output
enable" for each potential output. This feature allows the 10
outputs to be reconfigured as inputs on an individual basis, or
alternately used as a combination I/O controlled by the
programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product
terms per output and incrementing by 2 to 16 product terms
per output. By providing this variable structure, the
PALCE22V10 is optimized to the configurations found in a
majority of applications without creating devices that burden
the product term structures with unusable product terms and
lower performance.
Additional features of the Cypress PALCE22V10 include a
synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, elimi-
nating the need to dedicate standard product terms for initial-
ization functions. The device automatically resets upon
power-up.
The PALCE22V10, featuring programmable macrocells and
variable product terms, provides a device with the flexibility to
implement logic functions in the 500- to 800-gate-array
complexity. Since each of the ten output pins may be individ-
ually configured as inputs on a temporary or permanent basis,
functions requiring up to 21 inputs and only a single output and
down to twelve inputs and ten outputs are possible. The ten
potential outputs are enabled using product terms. Any output
pin may be permanently selected as an output or arbitrarily
enabled as an output and an input through the selective use
of individual product terms associated with each output. Each
of these outputs is achieved through an individual program-
mable macrocell. These macrocells are programmable to
provide a combinatorial or registered inverting or non-inverting
output. In a registered mode of operation, the output of the
register is fed back into the array, providing current status
information to the array. This information is available for estab-
lishing the next result in applications such as control state
machines. In a combinatorial configuration, the combinatorial
output or, if the output is disabled, the signal present on the I/O
pin is made available to the array. The flexibility provided by
both programmable product term control of the outputs and
variable product terms allows a significant gain in functional
density through the use of programmable logic.
Along with this increase in functional density, the Cypress
PALCE22V10 provides lower-power operation through the use
of CMOS technology, and increased testability with Flash
reprogrammability.
Selection Guide
Generic Part Number
t
PD
ns
t
S
ns
t
CO
ns
I
CC
mA
Com'l
Mil/Ind
Com'l
Mil/Ind
Com'l
Mil/Ind
Com'l
Mil/Ind
PALCE22V10-5
5
3
4
130
PALCE22V10-7
7.5
5
5
130
PALCE22V10-10
10
10
6
6
7
7
90
150
PALCE22V10-15
15
15
10
10
8
8
90
120
PALCE22V10-25
25
25
15
15
15
15
90
120
Configuration Table
Registered/Combinatorial
C
1
C
0
Configuration
0
0
Registered/Active LOW
0
1
Registered/Active HIGH
1
0
Combinatorial/Active LOW
1
1
Combinatorial/Active HIGH
PALCE22V10
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03027 Rev. *B
Page 4 of 13
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................65
C to +150
C
Ambient Temperature with
Power Applied.............................................55
C to +125
C
Supply Voltage to Ground Potential
(Pin 24 to Pin 12) ........................................... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State ............................................... 0.5V to +7.0V
DC Input Voltage............................................ 0.5V to +7.0V
Output Current into Outputs (LOW)............................. 16 mA
DC Programming Voltage............................................. 12.5V
Latch-up Current..................................................... > 200 mA
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ............................ > 2001V
Operating Range
Range
Ambient
Temperature
V
CC
Commercial
0
C to +75
C 5V
5%
Industrial
40
C to +85
C
5V
10%
Military
[1]
55
C to +125
C 5V
10%
Electrical Characteristics
Over the Operating Range
[2]
Parameter
Description
Test Conditions
Min.
Max. Unit
V
OH
Output HIGH Voltage
V
CC
= Min.,
V
IN
= V
IH
or V
IL
I
OH
= 3.2 mA
Com'l
2.4
V
I
OH
= 2 mA
Mil/Ind
V
OL
Output LOW Voltage
V
CC
= Min.,
V
IN
= V
IH
or V
IL
I
OL
= 16 mA
Com'l
0.5
V
I
OL
= 12 mA
Mil/Ind
V
IH
Input HIGH Level
Guaranteed Input Logical HIGH Voltage for All Inputs
[3]
2.0
V
V
IL
[4]
Input LOW Level
Guaranteed Input Logical LOW Voltage for All Inputs
[3]
0.5
0.8
V
I
IX
Input Leakage Current
V
SS
< V
IN
< V
CC
, V
CC
= Max.
10
10
A
I
OZ
Output Leakage Current
V
CC
= Max., V
SS
< V
OUT
< V
CC
40
40
A
I
SC
Output Short Circuit Current V
CC
= Max., V
OUT
= 0.5V
[5,6]
30
130 mA
I
CC1
Standby Power Supply
Current
V
CC
= Max.,
V
IN
= GND,
Outputs Open in Unprogrammed
Device
10, 15, 25 ns
Com'l
90
mA
5, 7.5 ns
130
mA
15, 25 ns
Mil/Ind
120
mA
10 ns
120
mA
I
CC2
[6]
Operating Power Supply
Current
V
CC
= Max., V
IL
= 0V, V
IH
= 3V,
Output Open, Device Programmed
as a 10-bit Counter,
f = 25 MHz
10, 15, 25 ns
Com'l
110
mA
5, 7.5 ns
Com'l
140
mA
15, 25 ns
Mil/Ind
130
mA
10 ns
Mil/Ind
130
mA
Capacitance
[6]
Parameter
Description
Test Conditions
Min.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 2.0V @ f = 1 MHz
10
pF
C
OUT
Output Capacitance
V
OUT
= 2.0V @ f = 1 MHz
10
pF
Endurance Characteristics
[6]
Parameter
Description
Test Conditions
Min.
Max.
Unit
N
Minimum Reprogramming Cycles
Normal Programming Conditions
100
Cycles
Notes:
1. T
A
is the "instant on" case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.
4. V
IL
(Min.) is equal to 3.0V for pulse durations less than 20 ns.
5. Not more than one output should be tested at a time. Duration of the short circuit should not be more than one second. V
OUT
= 0.5V has been chosen to avoid test problems
caused by tester ground degradation.
6. Tested initially and after any design or process changes that may affect these parameters.
PALCE22V10
USE ULTRA37000
TM
FOR
ALL NEW DESIGNS
Document #: 38-03027 Rev. *B
Page 5 of 13
AC Test Loads and Waveforms
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
CL
(a)
(b)
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
5 pF
(c)
OUTPUT
CL
R1238
(319
MIL)
R1238
(319
MIL)
R2170
(236
MIL)
R2170
(236
MIL)
750
(1.2K
MIL)
OUTPUT
2.08V = V
THC
OUTPUT
2.13V = V
THM
90%
10%
3.0V
GND
90%
10%
ALL INPUT PULSES
< 2 ns
< 2 ns
(d)
99
136
Equivalent to:TH VENIN Equivalent (Commercial)
Equivalent to: TH VENIN Equivalent (Military)
Load Speed
C
L
Package
5, 7.5, 10, 15, 25 ns
50 pF
PDIP, CDIP,
PLCC, LCC
Commercial Switching Characteristics PALCE22V10
[2, 7]
Parameter
Description
22V10-5
22V10-7
22V10-10
22V10-15
22V10-25
Unit
Min. Max. Min. Max. Min.
Max. Min.
Max. Min.
Max.
t
PD
Input to Output
Propagation Delay
[8]
3
5
3
7.5
3
10
3
15
3
25
ns
t
EA
Input to Output Enable Delay
[9]
6
8
10
15
25
ns
t
ER
Input to Output Disable Delay
[10]
6
8
10
15
25
ns
t
CO
Clock to Output Delay
[8]
2
4
2
5
2
7
2
8
2
15
ns
Notes:
7. Part (a) of AC Test Loads and Waveforms is used for all parameters except t
ER
and t
EA(+)
. Part (b) of AC Test Loads and Waveforms is used for t
ER
. Part (c) of AC Test
Loads and Waveforms is used for t
EA(+)
.
8. Min. times are tested initially and after any design or process changes that may affect these parameters.
9. The test load of (a) of AC Test Loads and Waveforms is used for measuring t
EA(-)
. The test load of (c) of AC Test Loads and Waveforms is used for measuring t
EA(+)
only.
Please see (e) of AC Test Loads and Waveforms for enable and disable test waveforms and measurement reference levels.
10. This parameter is measured as the time after output disable input that the previous output data state remains stable on the output. This delay is measured to
the point at which a previous HIGH level has fallen to 0.5V below V
OH
min. or a previous LOW level has risen to 0.5V above V
OL
max. Please see (e) of AC Test Loads
and Waveforms for enable and disable test waveforms and measurement reference levels.
Parameter
V
X
Output Waveform Measurement Level
t
ER (- )
1.5V
V
OH
0.5V
V
X
0.5V
t
ER (+)
2.6V
V
OL
V
X
t
EA (+)
0V
0.5V
t
EA (- )
V
thc
V
X
V
OL
1.5V
V
X
V
OH
(e) Test Waveforms
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