PCIX I/O System Clock Generator with EMI Control Features
C9531
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Document #: 38-07034 Rev. *D
Revised May 12, 2003
Features
Dedicated clock buffer power pins for reduced noise,
crosstalk and jitter
Input clock frequency of 25 MHz to 33 MHz
Output frequencies of XINx1, XINx2, XINx3 and XINx4
One output bank of 5 clocks.
One REF XIN clock output.
SMBus clock control interface for individual clock
disabling and SSCG control
Output clock duty cycle is 50% ( 5%)
< 250 ps skew between output clocks within a bank
Output jitter <175 ps
Spread Spectrum feature for reduced electromagnetic
interference (EMI)
OE pin for entire output bank enable control and
testability
28-pin SSOP and TSSOP packages
Note:
1.
XIN is the frequency of the clock on the device's XIN pin.
Table 1. Test Mode Logic Table
[1]
Input Pins
Output Pins
OE
S1
S0
CLK
REF
HIGH
LOW
LOW
XIN
XIN
HIGH
LOW
HIGH
2 * XIN
XIN
HIGH
HIGH
LOW
3 * XIN
XIN
HIGH
HIGH
HIGH
4 * XIN
XIN
LOW
X
X
Three-state Three-state
Block Diagram
Pin Configuration
XIN
CLK3
CLK2
CLK1
CLK0
/N
SSCG#
CLK4
SSCG
Logic
1
0
XOUT
I
2
C
Control
Logic
SCLK
OE
IA(0:2)
SDATA
GOOD#
REF
S(0,1)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD
XOUT
VSS
S1
GOOD#
VSS
IA1
IA2
VDDA
OE
IA0
SSCG#
VSS
CLK4
CLK3
VSS
CLK2
VDDA
VDDP
CLK1
CLK0
VDDP
VSS
SCLK
SDATA
C9531
REF
S0
XIN
C9531
Document #: 38-07034 Rev. *D
Page 2 of 10
Notes:
2.
Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is
connected to them.
3.
A bypass capacitor (0.1
F) should be placed as close as possible to each V
DD
pin. If these bypass capacitors are not close to the pins their high frequency
filtering characteristic will be cancelled by the lead inductance of the trace.
4.
PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required.
Data Protocol
The clock driver serial protocol accepts block write a opera-
tions from the controller. The bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. The C9531 does not support the Block Read
function.
The block write protocol is outlined in Table 2. The addresses
are listed in Table 3.
Pin Description
[3]
Pin
[2]
Name
PWR
[4]
I/O
Description
3
XIN
VDDA
I
Crystal Buffer Input Pin. Connects to a crystal, or an external clock
source. Serves as input clock TCLK, in Test mode.
4
XOUT
VDDA
O
Crystal Buffer Output Pin. Connects to a crystal only. When a Can
Oscillator is used or in test mode, this pin is kept unconnected.
1
REF
VDD
O
Buffered inverted outputs of the signal applied at Xin, typically
33.33 or 25.0 MHz.
14*
OE
VDD
I
Output Enable for Clock Bank. Causes the CLK (0:4) output clocks
to be in a three-state condition when driven to a logic low level.
24, 23, 22, 19, 18
CLK(0:4)
VDDP
O
A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
8
GOOD#
VDD
O
When his output signal is a logic low level, it indicates that the output
clocks of the bank are locked to the input reference clock. This
output is latched.
6*, 7*
S(0,1)
VDD
I
Clock Bank Selection Bits. These control the clock frequency that will
be present on the outputs of the bank of buffers. See table on page
one for frequency codes and selection values.
20, 25
VDDP
PWR
3.3V common power supply pin for all PCI clocks CLK (0:4).
10*, 11*, 12*
IA(0:2)
VDD
I
SMBus Address Selection Input Pins. See Table 3 on page 3.
15*
SSCG#
VDD
I
Spread Spectrum Clock Generator. Enables Spread Spectrum clock
modulation when at a logic low level, see Spread Spectrum Clocking
on page 6.
28
SDATA
VDD
I/O
Data for the Internal SMBus Circuitry. See Table 3 on page 3.
27
SCLK
VDD
I
Clock for the Internal SMBus Circuitry. See Table 3 on page 3.
13, 17
VDDA
I
Power for Internal Analog Circuitry. This supply should have a
separately decoupled current source from VDD.
2
VDD
PWR
Power supply for internal core logic.
5, 9, 16, 21, 26
VSS
PWR
Ground pins for the device.
C9531
Document #: 38-07034 Rev. *D
Page 3 of 10
Serial Control Registers
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Bit
Description
1
Start
2:8
Slave address 7 bits
9
Write = 0
10
Acknowledge from slave
11:18
Command Code 8 bits
'00000000' stands for block operation
19
Acknowledge from slave
20:27
Byte Count 8 bits
28
Acknowledge from slave
29:36
Data byte 1 8 bits
37
Acknowledge from slave
38:45
Data byte 2 8 bits
46
Acknowledge from slave
....
......................
....
Data Byte (N1) 8 bits
....
Acknowledge from slave
....
Data Byte N 8 bits
....
Acknowledge from slave
....
Stop
Table 3. SMBus Address Selection Table
SMBus Address of the Device
IA0 Bit (Pin 10)
IA1 Bit (Pin 11)
IA2 Bit (Pin 12)
DE
0
0
0
DC
1
0
0
DA
0
1
0
D8
1
1
0
D6
0
0
1
D4
1
0
1
D0
0
1
1
D2
1
1
1
Byte 0: Output Register
Bit
@Pup
Name
Description
7
1
TESTEN
Test Mode Enable.
1 = Normal operation, 0 = Test mode
6
0
SSEN
Spread Spectrum modulation control bit (effective only when Bit 0 of this register is
set to a 0) 0 = OFF, 1= ON
5
1
SSSEL
SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table 4 below for clarification
4
0
S1
S1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
3
0
S0
S0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set
to a 0)
C9531
Document #: 38-07034 Rev. *D
Page 4 of 10
2
0
Not used
1
0
Not used
0
1
HWSEL
Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, and 15), 0 = SMBus
Byte 0 bits 3, 4, & 6
Table 4. Clarification Table for Byte0, bit 5
Byte0, bit6
Byte0, bit5
Description
0
0
Frequency generated from second PLL
0
1
Frequency generated from XIN
1
0
Spread @ 1.0%
1
1
Spread @ 0.5%
Table 5. Test Table
Test Function Clock
Outputs
Note
CLK
REF
Frequency
XIN/4
XIN
XIN is the frequency of the clock that is present on the
XIN input during test mode.
Byte 1: CPU Register
Bit
@Pup
Name
Description
7
1
Reserved
6
1
Reserved
5
1
REFEN
REF Output Enable
0 = Disable, 1= Enable
4
1
Reserved
3
1
Reserved
2
1
Reserved
1
1
Reserved
0
1
Reserved
Byte 2: PCI Register
Bit
@Pup
Name
Description
7
1
Reserved
6
1
Reserved
5
1
Reserved
4
1
18
CLK4 Output Enable
0 = Disable, 1= Enable
3
1
19
CLK3 Output Enable
0 = Disable, 1= Enable
2
1
22
CLK2Output Enable
0 = Disable, 1= Enable
1
1
23
CLK1 Output Enable
0 = Disable, 1= Enable
0
1
24
CLK0 Output Enable
0 = Disable, 1= Enable
Byte 0: Output Register (continued)
C9531
Document #: 38-07034 Rev. *D
Page 5 of 10
Output Clock Three-state Control
All of the clocks in the Bank may be placed in a three-state
condition by bringing their relevant OE pins to a logic low state.
This transition to and from a three-state and active condition
is a totally asynchronous event and clock glitching may occur
during the transitioning states. This function is intended as a
board level testing feature. When output clocks are being
enabled and disabled in active environments the SMBus
control register bits are the preferred mechanism to control
these signals in an orderly and predictable manner.
The output enable pin contains an internal pull-up resistor that
will insure that a logic 1 is maintained and sensed by the
device if no external circuitry is connected to this pin.
Output Clock Frequency Control
All of the output clocks have their frequency selected by the
logic state of the S0 and S1 control bits. The source of these
control signals is determined by the SMBus register Byte 0 bit
0. At initial power up this bit is set of a logic 1 state and thus
the frequency selections are controlled by the logic levels
present on the device's S(0,1) pins. If the application does not
use an SMBus interface then hardware frequency selection
S(0,1) must be used. If it is desired to control the output clocks
using an SMBus interface, then this bit (B0b0) must first be set
to a low state. After this is done the device will use the contents
of the internal SMBus register Bytes 0 bits 3 and 4 to control
the output clock's frequency.
The following formula and schematic may be used to under-
stand and calculate either the loading specification of a crystal
for a design or the additional discrete load capacitance that
must be used to provide the correct load to a known load rated
crystal.
where:
C
XTAL
= The load rating of the crystal.
C
XINFTG
= The clock generators XIN pin effective device internal capacitance to ground.
C
XOUTFTG
= The clock generators XOUT pin effective device internal capacitance to ground.
C
XINPCB
= The effective capacitance to ground of the crystal to device PCB trace.
C
XOUTPCB
= The effective capacitance to ground of the crystal to device PCB trace.
C
XINDISC
= Any discrete capacitance that is placed between the XIn pin and ground.
C
XOUTDISC
= Any discrete capacitance that is placed between the XIn pin and ground.
As an example and using this formula for this data sheet's
device, a design that has no discrete loading capacitors
(C
DISC
) and each of the crystal device PCB traces has a
capacitance (C
PCB
) to ground of 4 pF (typical value) would
calculate as:
Therefore, to obtain output frequencies that are as close to this
data sheets specified values as possible, in this design
example, you should specify a parallel cut crystal that is
designed to work into a load of 20 pF.
(C
XINPCB
+ C
XINFTG
+ C
XINDISC
) x (C
XOUTPCB
) + C
XOUTFTG
) + C
XOUTDISC
)
(C
XINPCB
+ C
XINFTG
+ C
XINDISC
) + (C
XOUTPCB
) + C
XOUTFTG
) + C
XOUTDISC
)
C
L
=
C
XINPCB
C
XOUTPCB
C
XOUTDISC
C
XINDISC
C
XINFTG
C
XOUTFTG
XIN
XOUT
Clock Generator
(4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF)
(4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF)
C
L
=
40 x 40
40 x 40
=
=
1600
80
= 20 pF.
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