C9827H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 1 of 25
Approved Product
Product Features
Supports
Pentium
4 Type CPUs
3.3 Volt Power Supply
10 Copies of PCI Clocks
3 Differential CPU Clocks
SMBus Support with Read-back Capabilities
Spread Spectrum EMI Reduction
Dial-a-FrequencyTM
Features
Dial-a-dBTM
Features
56 Pin SSOP and TSSOP Package
Frequency Table
S2
S1
S0
CPU
(0:2)
3V66
66BUFF(0:2)/
3V66(0:4)
66IN/
3V66-5
PCI_F
PCI
REF
USB/
DOT
1
0
0
66M
66M
66IN
66MHz clock input
66IN/2
14.318M
48M
1
0
1
100M
66M
66IN
66MHz clock input
66IN/2
14.318M
48M
1
1
0
200M
66M
66IN
66MHz clock input
66IN/2
14.318M
48M
1
1
1
133M
66M
66IN
66MHZ clock input
66IN/2
14.318M
48M
0
0
0
66M
66M
66M
66M
33 M
14.318M
48M
0
0
1
100M
66M
66M
66M
33 M
14.318M
48M
0
1
0
200M
66M
66M
66M
33 M
14.318M
48M
0
1
1
133M
66M
66M
66M
33 M
14.318M
48M
M
0
0
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
M
0
1
TCLK/2
TCLK/4
TCLK/4
TCLK/4
TCLK/8
TCLK
TCLK/2
M
1
0
150M
50M
50M
50M
25M
14.318M
48M
M
1
1
166.6M
55.5M
55.5M
55.5M
27.7M
14.318M
48M
Note: TCLK is a test clock over driven on the XTAL_IN input during test mode. M= driven to a level between 1.0 and 1.8 Volts
If the S2 pin is at a M level during power up, a 0 state will be latched into the devices internal state register.
Block Diagram
Pin Configuration
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VDDA
VSSA
VTT_PG#
REF
S1
S0
CPU_STP#
CPU0
CPU/0
VDD
CPU1
CPU/1
VSS
VDD
CPU2
CPU/2
MULT0
IREF
VSSIREF
S2
48MUSB
48MDOT
VDD
VSS
3V66_1/VCH
PCI_STP#
3V66_0
VDD
VSS
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
C9827
PLL1
PLL2
/2
WD
Logic
Power
Up Logic
XIN
XOUT
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PG#
PCI_STP#
PD#
SDATA
SCLK
VDDA
66B[0:2]/3V66[2:4]
48M DOT
48M USB
PCI_F(0:2)
PCI(0:6)
3V66_1/VCH
3V66_0
CPU/(0:2)
CPU(0:2)
REF
66IN/3V66-5
I2C
Logic
C9827H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 2 of 25
Approved Product
Pin Description
PIN
NAME
PWR
I/O
Description
2
XIN
I
Oscillator Buffer Input. Connect to a crystal or to an external clock.
3
XOUT
VDD
O
Oscillator Buffer Output. Connect to a crystal. Do not connect when an
external clock is applied at XIN.
52, 51, 49,
48, 45, 44
CPU, CPU/
(0:2)
VDD
O
Differential host output clock pairs. See the frequency table on page
one of this data sheet for frequencies and functionality.
10, 11, 12,
13, 16, 17, 18
PCI(0:6)
VDDP
O
PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See
Frequency Table on page one of this data sheet.
5, 6, 7
PCIF (0:2)
VDD
O
33Mhz PCI clocks, which are
2 copies of 66IN or 3V66 clocks, may be
free running (not stopped when PCI_STP# is asserted low) or may be
stoppable depending on the programming of SMBus register Byte3,
Bits (3:5).
56
REF
VDD
O
Buffered Output copy of the device's XIN clock.
42
IREF
VDD
I
Current reference programming input for CPU buffers. A resistor is
connected between this pin and VSSIREF. See CPU Clock current
Select Table in page 18 of this data sheet.
28
VTT_PG#
VDD
I
Qualifying input that latches S (0:2) and MULT0. When this input is at a
logic low, the S (0:2) and MULT0 are latched
39
48MUSB
VDD48
O
Fixed 48MHz USB Clock Outputs.
38
48MDOT
VDD48
O
Fixed 48MHZ DOT Clock Outputs.
33
3V66_0
VDD
O
3.3 Volt 66 MHz fixed frequency clock.
35
3V66_1/VCH
VDD
O
3.3 volt clock selectable with SMBus byte0, Bit5, when Byte5, Bit5.
When Byte 0 Bit 5 is at a logic 1, then this pin is a 48M output clock.
When byte0, Bit5 is a logic 0, then this is a 66M output clock (default).
25
PD#
VDD
I
PU
This pin is a power down mode pin. A logic low level causes the device
to enter a power down state. All internal logic is turned off except for the
SMBus logic. All output buffers are stopped. See the Power Down
section of this data sheet.
43
MULT0
I
PU
Programming input selection for CPU clock current multiplier. See CPU
Clock Current Select Function Table.
55, 54
S(0,1)
I
I
Frequency Select Inputs. See Frequency Table on page 1.
29
SDATA
I
I
Serial Data Input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an
open drain output when acknowledging or transmitting data. See
application note AN-0022
30
SCLK
I
I
Serial Clock Input. Conforms to the SMBus specification. See
application note AN-0022.
40
S2
VDD
I
T
Frequency Select input. See Frequency Table on page 1. This is a Tri
level input that is driven high, low or driven to a intermediate level.
34
PCI_STP#
VDD
I
PU
PCI Clock Disable Input. When asserted low, PCI (0:6) clocks are
synchronously disabled in a low state. This pin does not effect PCIF
(0:2) clocks' outputs if they are programmed to be PCIF clocks via the
device's SMBus interface.
C9827H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 3 of 25
Approved Product
Pin Description (Cont.)
PIN
NAME
PWR
I/O
Description
53
CPU_STP#
VDD
I
PU
CPU Clock Disable Input. When asserted low, CPU (0:2) clocks are
synchronously disabled in a high state and CPU/(0:2) clocks are
synchronously disabled in a low state.
24
66IN/3V66_5
VDD
I/O
Input connection for 66CLK(0:2) output clock buffers if S2 = 1, or
output clock for fixed 66 MHz clock if S2=0. See table on page 1
21, 22, 23
66B(0:2)/
3V66(2:4)
VDD
O
3.3 volt clock outputs. These clocks are buffered copies of the 66IN
clock or fixed at 66 MHz. See table on page 1
1, 8, 14, 19,
32, 37, 46, 50
VDD
PWR
3.3V Power Supply
4, 9, 15, 20,
27, 31, 36, 47
VSS
PWR
Common Ground
41
VSSIREF
PWR
Current reference programming input for CPU buffers. A resistor is
connected between this pin and IREF. See CPU Clock current Select
Table in page 18 of this data sheet. This pin should also be returned to
device VSS.
26
VDDA
-
PWR
Analog power input. Used for PLL and internal analog circuits. Is also
specifically used to detect and determine when power is at an
acceptable level to enable the device to operate.
PU = Internal Pull-Up. PD = Internal Pull-Down. T = Tri level logic input with valid logic voltages of LOW=<0.8V, T=1.0-1.8V and
HIGH=>2.0V
2-Wire SMBus Control Interface
The 2-wire control interface implements a read/write slave only interface according to SMBus specification. (See
Application Note AN-0022).
The device will accept data written to the D2 address and data may read back from address D3. It will not respond to
any other addresses, and previously set control registers are retained as long as power in maintained on the device.
Serial Control Registers
Following the acknowledge of the Address Byte, two additional bytes must be sent:
1) "Command Code " byte, and
2) "Byte Count" byte.
Although the data (bits) in the command is considered "don't care"; it must be sent and will be acknowledged.
After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2)
described below will be valid and acknowledged.
Note: The Pin# column lists the relevant pin number where applicable. The @Pup column gives the default state at
power up.
C9827H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 4 of 25
Approved Product
Serial Control Registers (Cont.)
Byte 0: CPU Clock Register
Bit
@Pup
Pin#
Description
7
0
-
Spread Spectrum Enable
0 = Spread Off, 1 = Spread On
This is a Read and Write control bit.
6
0
-
Reserved
5
0
35
3V66_1/VCH frequency Select
0 = 66M selected, 1 = 48M selected
This is a Read and Write control bit.
4
Pin 53
44,45,48,49,
51,52
CPU_STP#. Reflects the current value of the external CPU_STP# (pin 53) This bit is Read Only.
3
Pin 34
10,11,12,13,
16,17,18
Reflects the current value of the internal PCI_STP# function when read. Internally PCI_STP# is a
logical AND function of the internal SMBus register bit and the external PCI_STP# pin.
2
Pin 40
-
Frequency Select Bit 2. Reflects the value of SEL2 (pin 40). This bit is Read Only.
1
Pin 55
-
Frequency Select Bit 1. Reflects the value of SEL1 (pin 55). This bit is Read Only.
0
Pin 54
-
Frequency Select Bit 0. Reflects the value of SEL0 (pin 54). This bit is Read Only.
Byte 1: CPU Clock Register
Bit
@Pup
Pin#
Description
7
Pin 43
-
MULT0 (Pin 43) Value. This bit is Read Only.
6
0
-
Reserved
5
0
44,45
Controls CPU2 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
4
0
48,49
Controls CPU1 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
3
0
51,52
Controls CPU0 functionality when CPU_STP# is asserted LOW
1 = Free Running, 0 = Stopped LOW with CPU_STP# asserted LOW
This is a Read and Write control bit.
2
1
44,45
CPU2 Output Control, 1 = enabled, 0 = disable HIGH and CPU/2 disables LOW
This is a Read and Write control bit.
1
1
48,49
CPU1 Output Control, 1 = enabled, 0 = disable HIGH and CPU/1 disables LOW
This is a Read and Write control bit.
0
1
51,52
CPU0 Output Control, 1 = enabled, 0 = disable HIGH and CPU/0 disables LOW
This is a Read and Write control bit.
Byte 2: PCI Clock Control Register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
0
-
Reserved
6
1
18
PCI6 Output Control
1 = enabled, 0 = forced LOW
5
1
17
PCI5 Output Control
1 = enabled, 0 = forced LOW
4
1
16
PCI4 Output Control
1 = enabled, 0 = forced LOW
3
1
13
PCI3 Output Control
1 = enabled, 0 = forced LOW
2
1
12
PCI2 Output Control
1 = enabled, 0 = forced LOW
1
1
11
PCI1 Output Control
1 = enabled, 0 = forced LOW
0
1
10
PCI0 Output Control
1 = enabled, 0 = forced LOW
Byte 3: PCI_F Clock and 48M Control Register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
1
38
48MDOT Output Control
1 = enabled, 0 = forced LOW
6
1
39
48MUSB Output Control
1 = enabled, 0 = forced LOW
5
0
7
PCI_STP#, control of PCI_F2.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
4
0
6
PCI_STP#, control of PCI_F1.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
3
0
5
PCI_STP#, control of PCI_F0.
0 = Free Running, 1 = Stopped when
PCI_STP# is LOW
2
1
7
PCI_F2 Output Control
1=running, 0=forced LOW
1
1
6
PCI_F1 Output Control
1= running, 0=forced LOW
0
1
5
PCI_F0 Output Control
1= running, 0=forced LOW
C9827H
High Performance Pentium 4 Clock Synthesizer
Cypress Semiconductor Corporation
http://www.cypress.com
Document#: 38-07106 Rev. *A
12/26/2002
Page 5 of 25
Approved Product
Byte 4: DRCG Control Register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
0
-
SS2 Spread Spectrum control bit
(0=down spread, 1=Center spread)
6
0
-
Reserved
5
1
33
3V66_0 Output Enabled
1 = enabled, 0 = disabled
4
1
35
3V66_1/VCH Output Enable
1 = enabled, 0 = disabled
3
1
24
3V66_5 Output Enable
1 = enabled, 0 = disabled
2
1
23
66B2/3V66_4 Output Enabled
1 = enabled, 0 = disabled
1
1
22
66B1/3V66_3 Output Enabled
1 = enabled, 0 = disabled
0
1
21
66B0/3V66_2 Output Enabled
1 = enabled, 0 = disabled
Byte 6: Silicon Signature Register
(all bits are read only)
Bit
@Pup
Pin#
Description
7
0
-
6
0
-
5
0
-
4
0
-
3
0
-
2
0
-
1
1
-
0
1
-
Vendor Code
011 = IMI
Note: When writing to this register the device will acknowledge the
write operation, but the data itself will be ignored.
Byte 8: Dial-a-FrequencyTM Control Register N
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
0
0
N7, MSB
6
0
0
N6
5
0
0
N5
4
0
0
N4
3
0
0
N3
2
0
0
N2
1
0
0
N3
0
0
0
N0, LSB
66IN to 66M Delay Control Table
Byte5
Bit5
Bit4
Delay (ns)
0
0
4.29
0
1
4.43
1
0
3.95 (default)
1
1
3.95
Byte 5: Clock control register
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
0
-
SS1 Spread Spectrum control bit
6
1
-
SS0 Spread Spectrum control bit
5
0
-
66IN to 66M delay Control MSB, See table
4
0
-
66IN to 66M delay Control LSB, See table
3
0
-
Reserved
2
0
-
48MDOT edge rate control. When set to 1,
the edge is slowed by 15%.
1
0
-
Reserved
0
0
-
USB edge rate control. When set to 1, the
edge is slowed by 15%
Byte 7: Watch Dog Time Stamp Register
Bit
@Pup
Pin#
Description
7
0
-
Reserved
6
0
-
Reserved
5
0
-
Reserved
4
0
-
Reserved
3
0
-
Reserved
2
0
-
Reserved
1
0
-
Reserved
0
0
-
Reserved
Byte 9: Dial-a-FrequencyTM Control Register R
(all bits are read and write functional)
Bit
@Pup
Pin#
Description
7
0
-
R6 MSB
6
0
-
R5
5
0
-
R4
4
0
-
R3
3
0
-
R2
2
0
-
R1
1
0
-
R0, LSB
0
0
-
R and N register load gate 0=gate closed
(data is latched), 1=gate open (data is
loading from SMBus registers into R and
N)
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