CS5954AM
ADVANCE
INFORMATION
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-08025 Rev. **
Revised May 28, 2002
CS5954AM
USB Controller for NAND Flash
CS5954AM
ADVANCE
INFORMATION
Document #: 38-08025 Rev. **
Page 2 of 44
Table of Contents
1.0 DEFINITIONS ................................................................................................................................... 5
2.0 REFERENCES ................................................................................................................................. 5
3.0 INTRODUCTION .............................................................................................................................. 5
3.1 Overview .......................................................................................................................................... 5
3.2 Features ........................................................................................................................................... 5
3.3 CS5954AM 16-bit RISC Processor ................................................................................................ 6
3.4 3K16 Mask ROM and BIOS ........................................................................................................... 6
3.5 Internal RAM .................................................................................................................................... 7
3.6 Clock Generator .............................................................................................................................. 7
3.7 USB Interface .................................................................................................................................. 7
3.8 Processor Control Registers ......................................................................................................... 7
3.9 Interrupts ......................................................................................................................................... 7
3.10 2-Wire Serial EEPROM Interface ................................................................................................. 7
3.11 External SRAM Interface .............................................................................................................. 7
3.12 General Timers and Watchdog Timer ......................................................................................... 7
3.13 Special GPIO Functionality for Suspend, Resume, and Low-power Modes ........................... 7
3.14 CS5954AM Interface Modes ......................................................................................................... 7
3.14.1 General-purpose I/O Mode (GPIO) ..................................................................................................... 7
4.0 INTERFACE ..................................................................................................................................... 8
4.1 Internal Masked ROM: 0xE8000xFFFF ........................................................................................ 8
4.2 External ROM: 0xC1000xE800 ..................................................................................................... 8
4.3 Internal RAM: 0x00000x0BFF ...................................................................................................... 8
4.4 Clock Generator .............................................................................................................................. 9
4.5 USB Interface ................................................................................................................................ 10
4.5.1 USB Global Control and Status Register (0xC080: R/W) ................................................................. 10
4.5.2 USB Frame Number Register (0xC082: Read-only) .......................................................................... 11
4.5.3 USB Address Register (0xC084: R/W) ............................................................................................... 11
4.5.4 USB Command Done Register (0xC086: Write-only) ....................................................................... 11
4.6 USB Endpoint 0 Control and Status Register (0xC090: R/W) ................................................... 11
4.7 USB Endpoint 1 Control and Status Register (0xC092: R/W) ................................................... 11
4.8 USB Endpoint 2 Control and Status Register (0xC094: R/W) ................................................... 11
4.9 USB Endpoint 3 Control and Status Register (0xC096: R/W) ................................................... 11
4.9.1 General Description for All Endpoints from Endpoint 0 to Endpoint 3 .......................................... 11
4.9.2 USB Endpoint Control (for Writing) ................................................................................................... 11
4.9.3 USB Endpoints Status (for Reading) ................................................................................................. 12
4.9.4 USB Endpoint 0 Address Register (0x0120: R/W) ............................................................................ 12
4.9.5 USB Endpoint 1 Address Register (0x0124: R/W) ............................................................................ 12
4.9.6 USB Endpoint 2 Address Register (0x0128: R/W) ............................................................................ 12
4.9.7 USB Endpoint 3 Address Register (0x012C: R/W) ........................................................................... 12
4.9.8 USB Endpoint 0 Count Register (0x0122: R/W) ................................................................................ 12
4.9.9 USB Endpoint 1 Count Register (0x0126: R/W) ................................................................................ 12
4.9.10 USB Endpoint 2 Count Register (0x012A: R/W) ............................................................................. 12
4.9.11 USB Endpoint 3 Count Register (0x012E: R/W) .............................................................................. 12
4.10 Processor Control Registers ..................................................................................................... 13
4.10.1 Configuration Register (0xC006: R/W) ............................................................................................ 13
4.10.2 Speed Control Register (0xC008: R/W) ........................................................................................... 14
4.10.3 Power-down Control Register (0xC00A: R/W) ................................................................................ 14
4.10.4 Breakpoint Register (0xC014: R/W) ................................................................................................. 15
CS5954AM
ADVANCE
INFORMATION
Document #: 38-08025 Rev. **
Page 3 of 44
4.11 Interrupts ..................................................................................................................................... 15
4.11.1 Hardware Interrupts .......................................................................................................................... 15
4.11.2 Interrupt Enable Register (0xC00E: R/W) ........................................................................................ 15
4.11.3 GPIO Interrupt Control Register (0xC01C: R/W) ............................................................................. 16
4.11.4 Software Interrupts ............................................................................................................................ 16
4.12 Serial EEPROM Interface (2-wire serial interface) ................................................................... 17
4.13 External SRAM ............................................................................................................................ 18
4.13.1 Memory Control Register (0xC03E: R/W) ........................................................................................ 18
4.13.2 Extended Memory Control Register (0xC03A: R/W) ....................................................................... 18
4.13.3 Extended Page 1 Map Register (0xC018: R/W) ............................................................................... 19
4.13.4 Extended Page 2 Map Register (0xC01A: R/W) .............................................................................. 19
4.13.5 Memory Map ....................................................................................................................................... 19
4.14 General Timers and Watchdog Timer ....................................................................................... 20
4.14.1 Timer 0 Count Register (0xC010: R/W) ............................................................................................ 20
4.14.2 Timer 1 Count Register (0xC012: R/W) ............................................................................................ 20
4.14.3 Watchdog Timer Count and Control Register (0xC00C: R/W) ....................................................... 21
4.15 Special GPIO Function for Suspend, Resume and Low-power Modes ................................. 21
5.0 CS5954AM INTERFACE MODES ................................................................................................. 21
5.1 General-purpose I/O Mode (GPIO) .............................................................................................. 21
5.1.1 I/O Control Register 0 (0xC022: R/W) ................................................................................................ 22
5.1.2 I/O Control Register 1 (0xC028: R/W) ................................................................................................ 22
5.1.3 Output Data Register 0 (0xC01E: R/W) .............................................................................................. 22
5.1.4 Output Data Register 1 (0xC024: R/W) .............................................................................................. 22
5.1.5 Input Data Register 0 (0xC020: Read only) ....................................................................................... 22
5.1.6 Input Data Register 1 (0xC026: Read-only) ....................................................................................... 22
5.1.7 I/O Address Map .................................................................................................................................. 23
6.0 PIN ASSIGNMENTS ...................................................................................................................... 25
6.1 Pin Diagram ................................................................................................................................... 25
7.0 PHYSICAL CONNECTION ............................................................................................................ 26
7.1 Package Type ................................................................................................................................ 26
7.2 Pin Assignment and Description ............................................................................................... 26
8.0 CS5954AM CPU PROGRAMMING GUIDE ................................................................................... 28
8.1 Instruction Set Overview .............................................................................................................. 28
8.2 Reset Vector .................................................................................................................................. 28
8.3 Register Set ................................................................................................................................... 28
8.4 General-purpose Registers .......................................................................................................... 29
8.5 General-purpose/Address Registers .......................................................................................... 29
8.6 REGBANK Register (0xC002: R/W) ............................................................................................. 29
8.7 Flags Register (0xC000: Read-only) ........................................................................................... 29
8.8 Instruction Format ........................................................................................................................ 29
8.9 Addressing Modes ........................................................................................................................ 30
8.10 Register Addressing ................................................................................................................... 30
8.11 Immediate Addressing ............................................................................................................... 30
8.12 Direct Addressing ....................................................................................................................... 30
8.13 Indirect Addressing .................................................................................................................... 30
8.14 Indirect Addressing with Auto Increment ................................................................................ 31
8.15 Indirect Addressing with Offset ................................................................................................ 31
8.16 Stack Pointer (R15) Special Handling ....................................................................................... 31
8.17 Dual Operand Instructions ......................................................................................................... 31
CS5954AM
ADVANCE
INFORMATION
Document #: 38-08025 Rev. **
Page 4 of 44
8.18 Program Control Instructions .................................................................................................... 32
8.19 Single Operand Operation Instructions .................................................................................... 33
8.20 Miscellaneous Instructions ........................................................................................................ 35
8.21 Built-in Macros ............................................................................................................................ 35
8.22 CS5954AM Processor Instruction Set Summary .................................................................... 36
9.0 CS5954AMELECTRICAL SPECIFICATIONS ............................................................................. 37
9.1 Absolute Maximum Ratings ......................................................................................................... 37
9.2 Recommended Operating Conditions ........................................................................................ 37
9.3 Crystal Requirements (XIN, XOUT) ............................................................................................. 37
9.4 External Clock Input Characteristics (XIN) ................................................................................. 37
9.5 CS5954AM DC Characteristics ................................................................................................... 37
9.6 CS5954AM USB Transceiver Characteristics ............................................................................ 38
9.7 CS5954AM Reset Timing ............................................................................................................. 38
9.8 CS5954AM Clock Timing Specifications .................................................................................... 38
9.9 CS5954AM SRAM Read Cycle .................................................................................................... 39
9.10 CS5954AM SRAM Write Cycle .................................................................................................. 40
9.11 Thermal Specifications .............................................................................................................. 40
9.12 2-wire Serial Interface EEPROM Timing .................................................................................. 41
10.0 PACKAGE AND ORDERING INFORMATION ............................................................................ 41
10.1 Ordering Information .................................................................................................................. 41
10.2 Package Drawings and Dimensions ......................................................................................... 42
10.3 Package Markings ...................................................................................................................... 43
11.0 WARRANTY DISCLAIMER AND LIMITED LIABILITY ............................................................... 43
12.0 REVISION HISTORY .................................................................................................................... 44
List of Figures
Figure 3-1. CS5954AM Block Diagram ................................................................................................. 6
Figure 4-1. 48-MHz Crystal Circuit ....................................................................................................... 9
Figure 4-2. 12-MHz Crystal Circuit ..................................................................................................... 10
Figure 4-3. 2-Wire Serial Interface 2K-byte Connection ................................................................... 17
Figure 4-4. 2-Wire Serial Interface 16K Connection ......................................................................... 17
Figure 4-5. Special GPIO Pull-up Connection Example ................................................................... 21
Figure 5-1. GPIO Mode Block Diagram .............................................................................................. 23
Figure 6-1. 100-pin PQFP .................................................................................................................... 25
List of Tables
Table 4-1. Internal Masked ROM (CS5954AM BIOS) .......................................................................... 8
Table 4-2. Internal RAM Memory Usage ............................................................................................. 8
Table 4-3. Hardware Interrupt Table .................................................................................................. 15
Table 4-4. Software Interrupt Table ................................................................................................... 16
Table 4-5. Memory Map ...................................................................................................................... 19
Table 5-1. I/O Address Map ................................................................................................................ 23
Table 7-1. Pin Assignment and Description ..................................................................................... 26
Table 10-1. Ordering Information ...................................................................................................... 41
CS5954AM
ADVANCE
INFORMATION
Document #: 38-08025 Rev. **
Page 5 of 44
1.0
Definitions
USB
Universal Serial Bus
CS5954
The CS5954AM is a Cypress USB Controller, which provides multiple functions on a single chip.
QT
Quick stream data Transfer engine, which contains a small set of RISC instructions designed for the
CS5954AM USB controller.
QTU
"QT" is a naming convention that represents QT Engine utility tools. For example: "QTU" indicates all
tools that interface with the USB port.
R/W
Read/Write
PLL
Phase Lock Loop
WDT
Watchdog Timer
RAM
Random Access Memory
2-wire serial interface 2-wire serial EEPROM interface
R0-R15
CS5954AM Registers
R0-R7 data registers or general-purpose registers
R8-R14 address/data registers, or general-purpose registers
R15 stack pointer register
CS5954AM BIOS
A simulation model similar to 8086 BIOS
2.0
References
[Ref. 1] SL11R_BIOS
[Ref. 2] SL11R Family Tools
[Ref. 3] Universal Serial Bus Specification 2.0
3.0
Introduction
3.1
Overview
The CS5954AM is a low-cost, full-speed Universal Serial Bus (USB) RISC-based controller specifically designed for mass storage
applications using NAND Flash technology. It contains a 16-bit RISC processor with built-in BIOS ROM to greatly reduce firmware
development work. Its 2-wire serial EEPROM interface offers low cost storage for USB device configuration and customer's
product-specific functions. New functions can be programmed into the 2-wire serial interface by downloading them from a USB
Host PC. This unique architecture provides the ability to upgrade products in the field without changing the peripheral hardware.
The CS5954AM Processor can execute code from either internal ROM/RAM or external ROM and SRAM. The CS5954AM
Programmable bidirectional data port supports I/O mode. A built-in USB port supports data transfers up to 12 MBits/sec which is
the maximum full speed USB transfer rate. All USB protocol modes are supported: Isochronous (up to 1024 bytes/packet), Bulk,
Interrupt, and Control. The CS5954AM requires a 3.3V power supply, which can be powered via a USB host PC or a Hub.
Suspend/Resume, and Low power modes are available.
The CS5954AM offers a cost effective solution for NAND Flash products.
3.2
Features
Cypress offers a development kit for each of its product lines. These development kits include multiple peripheral
mini-port class drivers for Microsoft
Windows
98/ME/2000, firmware source code and demo USB source code for
a variety of applications. Also available is a debugger and assembler with a reference demo board.
48-MHz 16-bit RISC processor.
Up to 16 bits of programmable bidirectional data I/O.
Up to 32 bits of general-purpose I/O (GPIO).
6K 8 internal mask ROM with built-in BIOS supporting a comprehensive list of interrupt calls (see [Ref. 1] SL11R_BIOS
for detailed information). These include USB functions, 2-wire serial interface boot-up option (boot-up from 2-wire
serial interface or external ROM). Executable code can also run from 8-bit or 16-bit external memory.
3K 8 internal RAM that can be configured as the USB Ping-Pong buffer for USB DATA0 and DATA1 packets. It can
also be used for data and/or code.
Two-wire serial EEPROM interface port with CS5954AM BIOS support to allow on-board EEPROM programming.
Flexible programmable external memory wait-states and a 8/16 data path.
Up to 16-bit address for extended memory interface port for external SRAM and ROM.
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