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High - Accuracy EPROM Programmable

PLL Die for Crystal Oscillators

CY2037

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07354 Rev. *A

Revised December 7, 2002

Features

Benefits

· EPROM-programmable die for in-package program-

ming of crystal oscillators

Enables quick turnaround of custom oscillators
Lowers inventory costs through stocking of blank parts

· High resolution PLL with 12 bit multiplier and 10 bit di-

vider

Enables synthesis of highly accurate and stable output clock
frequencies with zero or low PPM

· EPROM-programmable capacitor tuning array with

Shadow register

Enables fine-tuning of output clock frequency by adjusting
C

Load

of the crystal

· Twice programmable die (CY2037A and CY2037-2).

Enables reprogramming of programmed part, to correct errors,
and control excess inventory

· Simple 4-wire programming interface

Enables programming of output frequency after packaging

· On-chip oscillator runs from 1030 MHz fundamental

tuned crystal

Lowers cost of oscillator as PLL can be programmed to a high
frequency using a low-frequency, low-cost crystal

· EPROM-selectable TTL or CMOS duty cycle levels

Duty cycle centered at 1.4V or V

Provides flexibility to service most TTL or CMOS applications

· Operating frequency

-- 1133 MHz at 5V
-- 1100 MHz at 3.3V
-- 166.6 MHz at 2.7V

Services most PC, networking, and consumer applications

· Sixteen selectable post-divide options, using either

PLL or reference oscillator output

Provides flexibility in output configurations and testing

· Programmable PWR_DWN or OE pin (CY2037A and

CY2037-2)

· Frequency Select (CY2037-3)

Enables low-power operation or output enable function

Enables two frequency options for meeting different industry
standards, i.e., PAL/NTSC.

· Programmable asynchronous or synchronous OE and

PWR_DWN modes (CY2037 and CY2037-2)

Provides flexibility for system applications, through selectable
instantaneous or synchronous change in outputs

· Low Jitter outputs typically

-- < ± 100 ps (pk-pk) at 5V and f>33 MHz
-- < ± 125 ps (pk-pk) at 3.3V and f>33 MHz

Suitable for most PC, consumer, and networking applications

· 3.3V or 5V operation

Lowers inventory cost as same die services both applications

· Small Die

Enables encapsulation in small-size, surface mount packages

· Controlled rise and fall times and output slew rate

Has lower EMI than oscillators

CY2037

Document #: 38-07354 Rev. *A

Page 2 of 9

Functional Description

The CY2037 is an EPROM programmable, high accuracy,
PLL-based die designed for the crystal oscillator market. The
die attaches directly to a low-cost 1030 MHz crystal and can
be packaged into 4-pin through-hole or surface mount pack-
ages. The oscillator devices can be stocked as blank parts and
custom frequencies programmed in-package at the last stage
before shipping. This enables fast-turn manufacture of custom
and standard crystal oscillators without the need for dedicated,
expensive crystals.

The CY2037 contains an on-chip oscillator and an unique os-
cillator tuning circuit for fine-tuning of the output frequency.
The crystal C

load

can be selectively adjusted by programming

a set of seven EPROM bits. This feature can be used to com-
pensate for crystal variations or to obtain a more accurate syn-
thesized frequency.

The CY2037 uses EPROM programming with a simple 2-wire,
4-pin interface that includes V

and V

. Clock outputs can

be generated up to 133 MHz at 5V or up to 100 MHz at 3.3V.
The entire configuration can be reprogrammed one time, al-
lowing programmed inventory to be altered or reused.

The CY2037 PLL die has been designed for very high resolu-
tion. It has a 12 bit feedback counter multiplier and a 10 bit
reference counter divider. This enables the synthesis of highly
accurate and stable output clock frequencies with zero or low
PPM error. The clock can be further modified by eight output
divider options of 1, 2, 4, 8, 16, 32, 64, and 128. The divider

input can be selected as either the PLL or crystal oscillator
output providing a total of sixteen separate output options. For
further flexibility, the ouput is selectable between TTL and
CMOS duty cycle levels.

The CY2037A and CY2037-2 also contain flexible power man-
agement controls. These parts include both PWR_DWN and
OE features with integrated pull-up resistors. The PWR_DWN
and OE modes have an additional setting to determine timing
(asynchronous or synchronous) with respect to the output sig-
nal. When PWR_DWN or OE modes are enables, CLKOUT is
pulled low by a weak pull down. The weak pull down is easily
overdriven by another active CLKOUT for applications that re-
quire multiple CLKOUTs on a single signal path.

Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enable the CY2037 to
have low jitter and accurate outputs making it suitable for most
PC, networking and consumer applications.

On the other hand, the CY2037-3 contains a frequency select
function in place of the power down and output enable modes.
For example, consumer products often require frequency
compatibility with different electrical standards around the
world. With this frequency select feature a product that incor-
porates the CY2037-3 could be compatible with both NTSC for
North American and PAL for Europe simply by changing the
FS line. The twice programmable feature is also lost in the
CY2037-3, because the second EPROM row is now being
used for the alternate frequency.

Die Configuration

CY2037 Logic Block Diagram

Top View

PD/OE

CLKOUT

PD/OE

CONFIGURATION

CRYSTAL

CLKOUT

/ 1, 2, 4, 8, 16, 32, 64, 128

N/C / Xx

[1]

N/C

OSCILLATOR

or FS

MUX

HIGH

ACCURACY

PLL

EPROM

N/C

7C803xx

Note:

For Customers not bonding X

or X

pad to external pins, an alternative bonding option would be shorting the Xx pad to the X

pad.

CY2037

Document #: 38-07354 Rev. *A

Page 3 of 9

EPROM Configuration Block

Table 1 summarizes the features which are configurable by
EPROM. Please refer to the "7C8038x/7C8034X
Programming Specification" for further details. The specifica-
tion can be obtained from your Cypress factory representative.

PLL Output Frequency

The CY2037 contains a high resolution PLL with 12 bit multi-
plier and 10 bit divider.The output frequency of the PLL is de-
termined by the following formula:

where P is the feedback counter value and Q is the reference
counter value. P and Q are EPROM programmable values.

Power Management features (except CY2037-3)

The CY2037 contains EPROM programmable PWR_DWN
and OE functions. If Powerdown is selected, all active circuitry
on the chip is shut down when the control pin goes low. The
oscillator and PLL circuits must re-lock when the part leaves
Powerdown Mode. If Output Enable mode is selected, the out-
put is tri-stated and weakly pulled low when the Control pin
goes low. In this mode the oscillator and PLL circuits continue
to operate, allowing a rapid return to normal operation when
the Control input is deasserted.

In addition, the PWR_DWN and OE modes can be pro-
grammed to occur synchronously or asynchronously with re-
spect to the output signal. When the asynchronous setting is
used, the powerdown or output disable occurs immediately

(allowing for logic delays) irrespective of position in the clock
cycle. However, when the synchronous setting is used, the
part waits for a falling edge at the output before powerdown or
output enable signal is initiated, thus preventing output glitch-
es. In either asynchronous or synchronous setting, the output
is always enabled synchronously by waiting for the next falling
edge of the output.

Crystal Oscillator Tuning Circuit

The CY2037 contains a unique tuning circuit to fine-tune the
output frequency of the device. The tuning circuit consists of
an array of eleven load capacitors on both sides of the oscilla-
tor drive inverter. The capacitor load values are EPROM pro-
grammable and can be increased in small increments. As the
capacitor load is increased the circuit is fine-tuned to a lower
frequency. The capacitor load values vary from 0.17 pF to 8 pF
for a 100:1 total control ratio. The tuning increments are shown
in the table below. Please refer to the "7C8038x/7C8034x Pro-
gramming Specification" for further details.

Difference Between CY2037A and CY2037-2

The CY2037A contains a shadow register in addition to the
EPROM register. The shadow register is an exact copy of the
EPROM register and is the default register when the Valid bit
is not set. It is useful when the prototype or production envi-
ronment calls for measuring and adjusting the CLKOUT fre-
quency numerous times. Multiple adjustments can be per-
formed with the shadow register. Once the desired frequency
is achieved the EPROM register is permanently programmed.

Some production flows do not require the use of the shadow
register. If this is the case, then the CY2037-2 is the device of
choice. The CY2037-2 has a disabled shadow register.

The CY2037-3 contains the shadow register.

Frequency Select Feature of CY2037-3

The CY2037-3 contains a frequency select function in place of
the powerdown and the output enable functions. With the
frequency select feature, customers can switch two different
frequencies that are configured in the two EPROM rows The
definition of the Frequency select pin (FS) is shown in the fol-
lowing table.

Table 1. EPROM Adjustable Features

Adjust

Frequency

Feedback counter value (P)

Reference counter value (Q)

Output divider selection

Oscillator Tuning (load capacitance values)

Duty cycle levels (TTL or CMOS)

Power management mode (OE or PWR_DWN)

Power management timing

(synchronous or asynchronous)

PLL

(

)

(

)

---------------------------

REF

Die Pad Summary

Name

Die Pad

Description

1,2

Voltage supply

8,9

Ground

Crystal connection.

No Connect. (For customers not bonding X

or X

pad to external pins, an alternative bonding option

would be shorting this pad to XD pad.)

Crystal connection.

PD/OE or FS

CY2037A and CY2037-2--EPROM programmable power down or output enable pad.
CY2037-3--Frequency Select.
Serves as V

in programming mode for all devices

CLKOUT

Clock output. Also serves as three-state input during programming.

N/C

5,10

No Connect. (Do not bond to these pads)

CY2037

Document #: 38-07354 Rev. *A

Page 4 of 9

Crystal Oscillator Tuning Circuit

Device Functionality: Output Frequencies

Parameter

Description

Condition

Min.

Max.

Unit

Output frequency

= 4.5V5.5V

133

MHz

= 3.0V3.6V

100

MHz

= 2.7V3.0V

MHz

Symbol

Description

Min.

Typ.

Max.

Unit

Feedback resistor, V

= 4.55.5V

Feedback resistor, V

= 2.73.6V

0.5
1.0

2
4

3.5
9.0

Capacitors have ± 20% Tolerance

Gate capacitor

Drain Capacitor

Series Cap

0.27

Series Cap

0.52

Series Cap

1.00

Series Cap

0.7

Series Cap

1.4

Series Cap

2.6

Series Cap

5.0

Series Cap

0.45

Series Cap

0.85

Series Cap

1.7

Series Cap

3.3

Table 2. Frequency Select Pin Decoding for CY2037-3

FS Pin

Output Frequency

From EPROM Row 0 Configuration

From EPROM Row 1 Configuration

CD = EPROM BIT
T = TRANSISTOR
C = LOAD CAPACITOR

CD6

CD5

CD4

CD3

CD2

CD1

CD0

CD3

CD4

CD5

CD6

C10

External Crystal

Cgo Cdo

CY2037

Document #: 38-07354 Rev. *A

Page 5 of 9

Absolute Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Supply Voltage ..................................................0.5 to +7.0V

Input Voltage ..............................................0.5V to V

+0.5

Storage Temperature (Non-Condensing) ... 55

C to +150

Junction Temperature ................................. 40

C to +100

Static Discharge Voltage............................................ >2000V
(per MIL-STD-883, Method 3015)

Operating Conditions

Parameter

Description

Min.

Max.

Unit

Supply Voltage (3.3V)
Supply Voltage (5.0V)

2.7
4.5

3.6
5.5

V
V

[2]

Operating Temperature, Junction

+100

TTL

Max. Capacitive Load on outputs for TTL levels

= 4.55.5V, Output frequency = 140 MHz

= 4.55.5V, Output frequency = 40133 MHz

50
25

pF
pF

CMOS

Max. Capacitive Load on outputs for CMOS levels

= 4.55.5V, Output frequency = 166.6MHz

= 4.55.5V, Output frequency = 66.6133MHz

= 3.03.6V, Output frequency = 140 MHz

= 3.03.6V, Output frequency = 40100 MHz

= 2.73.0V, Output frequency = 166 MHz

50
25
30
15
15

pF
pF
pF
pF
pF

REF

Reference Frequency, input crystal. Fundamental tuned crystals only.

MHz

Power-up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)

0.05

Electrical Characteristics

Over the Operating Range (Part was characterized in a 20 pin SOIC package with external

crystal, Electrical Characteristics may change with other package types.)

Parameter Description

Test Conditions

Min.

Typ.

Max.

Unit

Low-level Input Voltage

= 4.5V5.5V

= 2.7V3.6V

0.8
0.2V

V
V

High-level Input Voltage

= 4.5V5.5V

= 2.7V3.6V

2.0
0.7V

V
V

Low-level Output Voltage

= 4.5V5.5V, I

= 16 mA

= 2.7V3.6V, I

= 8 mA

0.4
0.4

V
V

OHCMOS

High-level Output Voltage,
CMOS levels

= 4.5V5.5V, I

= 16 mA

= 2.7V3.6V, I

= 8 mA

0.4

V
V

OHTTL

High-level Output Voltage,
TTL levels

= 4.5V5.5V, I

= 8 mA

2.4

Input Low Current

= 0V

Input High Current

= V

Power Supply Current,
Unloaded

= 4.5V5.5V, Output frequency <= 133MHz

= 2.7V3.6V, Output frequency <= 100 MHz

45
25

mA
mA

DDS

[3]

Stand-by current

= 2.7V3.6V

Input Pull-Up Resistor

= 4.5V5.5V, V

= 0V

= 4.5V5.5V, V

= 0.7V

1.1
50

3.0
100

8.0
200

OE_CLKOUT

CLKOUT Pulldown current

= 5.0

Notes:

This product is sold in die form so operating conditions are specified for the die, or junction temperature

If external reference is used, it is required to stop the reference (set reference to LOW) during power down.

CY2037

Document #: 38-07354 Rev. *A

Page 6 of 9

Output Clock Switching Characteristics

Over the Operating Range

[5]

Symbol

Description

Test Conditions

Min

Typ

Max

Unit

Output Duty Cycle at
1.4V, V

= 4.55.5V

= t

140 MHz, C

<= 50 pF

4066 MHz, C

<= 15 pF

66125 MHz, C

<= 25 pF

125133 MHz, C

<= 15 pF

45
45
40
40

55
55
60
60

%
%
%
%

Output Duty Cycle at
V

/2, V

= 4.55.5V

= t

166.6 MHz, C

<= 25 pF

66.6125 MHz, C

<= 25 pF

125133 MHz, C

<= 15 pF

45
40
40

55
60
60

%
%
%

Output Duty Cycle at
V

/2, V

= 3.03.6

= t

140 MHz, C

<= 30 pF

40100 MHz, C

<= 15 pF

45
40

55
60

%
%

Output Duty Cycle at
V

/2, V

= 2.73.0

= t

140 MHz, C

<= 15 pF

4066.6 MHz, C

<= 10 pF

40
40

60
60

%
%

Output Clock Rise time

Between 0.8V2.0V, V

= 4.5V5.5V, C

= 50 pF

Between 0.8V2.0V, V

= 4.5V5.5V, C

= 25 pF

Between 0.8V2.0V, V

= 4.5V5.5V, C

= 15 pF

Between 0.2V

0.8V

, V

= 4.5V5.5V, C

= 50 pF

Between 0.2V

0.8V

, V

= 3.0V3.6V, C

= 30 pF

Between 0.2V

0.8V

, V

= 2.7V3.6V, C

= 15 pF

1.8
1.2
0.9
3.4
4.0
2.4

ns
ns
ns
ns
ns
ns

Output Clock Fall time

Between 0.8V2.0V, V

= 4.5V5.5V, C

= 50 pF

Between 0.8V2.0V, V

= 4.5V5.5V, C

= 25 pF

Between 0.8V2.0V, V

= 4.5V5.5V, C

= 15 pF

Between 0.2V

0.8V

, V

= 4.5V-5.5V, C

= 50 pF

Between 0.2V

0.8V

, V

= 3.0V3.6V, C

= 30 pF

Between 0.2V

0.8V

, V

= 2.7V3.6V, C

= 15 pF

1.8
1.2
0.9
3.4
4.0
2.4

ns
ns
ns
ns
ns
ns

Start-up time out of
power-down

PWR_DWN pin LOW to HIGH

[4]

Power Down delay time
(synchronous setting)

PWR_DWN pin LOW to output LOW
(T = period of Output clk)

T/2

T+10

Power Down delay time
(asynchronous setting)

PWR_DWN pin LOW to output LOW

Power Up time

From power on

[4]

Output disable time
(synchronous setting)

OE pin LOW to output Hi-Z
(T = period of output clk)

T/2

T+10

Output disable time
(asynchronous setting)

OE pin LOW to output Hi-Z

Output enable time
(always synchronous
enable)

OE pin LOW to HIGH
(T = period of output clk)

1.5T+25

Peak-to-Peak Period
Jitter

= 4.5V5.5V, Fo > 33 MHz, VCO > 100 MHz

= 2.7V3.6V, Fo > 33 MHz, VCO > 100 MHz

= 2.7V5.5V, Fo < 33 MHz

±100
±125
±250

±125
±200

1% of F

ps
ps
ps

Notes:

Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.

Not all parameters measured in production testing.

CY2037

Document #: 38-07354 Rev. *A

Page 8 of 9

© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Ordering Information

[8]

Note:

The only difference between the CY2037A and the CY2037-2 is: The CY2037-2 has the shadow register disabled. The CY2037-3 replaces the power-down
options with a Frequency Select, and contains the shadow register.

Switching Waveforms

(continued)

CLKOUT

OUTPUT
ENABLE

Output Enable Timing (synchronous and asynchronous modes)

High Impedance

CLKOUT

High Impedance

(synchronous

]

)

(asynchronous

]

)

Ordering Code

Type

Operating Range

CY2037AWAF

Wafer

Industrial

CY2037-2WAF

Wafer

Industrial

CY2037-3WAF

Wafer

Industrial

Die Information

Wafer Thickness

14 ±0.5 mils

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