High Accuracy EPROM Programmable
Die for Crystal Oscillators
CY2039
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07355 Rev. **
Revised February 4, 2002
Features
Benefits
EPROM-programmable capacitor tuning array with
Shadow register
Enables fine-tuning of crystal clock frequency by adjusting
C
Load
of the crystal
Twice programmable die
EPROM redundancy allows 2 programming opportunities to
correct errors, and control excess inventory
Simple 4-pin programming interface
Enables programming of output frequency after packaging
On-chip oscillator runs from 1030 MHz crystal
Lowers cost of oscillator as PPM manufacturing error can be
tweaked in package
EPROM-selectable TTL or CMOS duty cycle levels
Duty cycle centered at 1.4V or V
DD
/2
Provides flexibility to service most TTL or CMOS applications
Four selectable post-divide options, using reference os-
cillator output
Provides flexibility in output configurations and testing
Programmable PWR_DWN or OE pin
Enables low-power operation or output enable function
Programmable asynchronous or synchronous OE and
PWR_DWN modes
Provides flexibility for system applications, through selectable
instantaneous or synchronous change in outputs
3.3V or 5V operation
Lowers inventory cost as same die services both applications
Small Die
Enables encapsulation in small-size, surface mount packages
Controlled rise and fall times and output slew rate
Has lower EMI than oscillators
Die Configuration
CY2039 Logic Block Diagram
V
DD
Top View
V
SS
V
DD
X
G
PWR_DWN
CLKOUT
V
SS
X
G
PWR_DWN
X
D
CRYSTAL
CLKOUT
/ 1, 2, 4, 8
N/C
X
D
N/C
OSCILLATOR
1
2
3
4
5
6
7
8
9
11
or OE
or OE
N/C
10
CONFIGURATION
EPROM
CY2039
Document #: 38-07355 Rev. **
Page 2 of 8
Functional Description
The CY2039 is a high-accuracy IC designed for the crystal
oscillator market. The die attaches directly to a low-cost 1030
MHz crystal and can be packaged into 4-pin through-hole or
surface mount packages. The oscillator devices can be
stocked as blank parts and PPM error programmed in-pack-
age at the last stage before shipping. This enables fast-turn
manufacture of custom and standard crystal oscillators without
the need for dedicated, expensive crystals.
The CY2039 contains an on-chip oscillator and a unique oscil-
lator tuning circuit for fine-tuning of the output frequency. The
crystal C
load
can be selectively adjusted by programming a set
of seven EPROM bits. This feature can be used to compensate
for crystal variations or to obtain a more accurate frequency.
The CY2039 uses EPROM programming with a simple 2-wire,
4-pin interface that includes V
SS
and V
DD
. The entire configu-
ration can be reprogrammed one time allowing programmed
inventory to be altered or reused.
The CY2039 also contains flexible power management con-
trol. The part includes both PWR_DWN and OE features with
integrated pull-up resistors. The PWR_DWN and OE modes
have an additional setting to determine timing (asynchronous
or synchronous) with respect to the output signal. When
PWR_DWN or OE modes are enables, CLKOUT is pulled low
by a weak pull down. The weak pull down is easily overdriven
by another active CLKOUT for applications that require multi-
ple CLKOUTs on a single signal path.
Controlled rise and fall times, unique output driver circuits, and
innovative circuit layout techniques enable the CY2039 to have
low jitter and accurate outputs making it suitable for most PC,
networking and consumer applications
EPROM Configuration Block
The following table summarizes the features which are config-
urable by EPROM. Please refer to the "7C80320 Programming
Specification" for further details. The specification can be ob-
tained from your local Cypress representative
Power Management Features
The CY2039 contains EPROM programmable PWR_DWN
and OE functions. If Powerdown is selected, all active circuitry
on the chip is shut down when the control pin goes LOW. The
oscillator must re-lock when the part leaves Powerdown Mode.
If Output Enable mode is selected, the output is three-stated
and weakly pulled low when the Control pin goes low. In this
mode the oscillator circuit continues to operate, allowing a rap-
id return to normal operation when the Control input is
deasserted.
In addition, the PWR_DWN and OE modes can be pro-
grammed to occur synchronously or asynchronously with re-
spect to the output signal. When the asynchronous setting is
used, the powerdown or output three-state occurs immediately
(allowing for logic delays) irrespective of position in the clock
cycle. However, when the synchronous setting is used, the
part waits for a falling edge at the output before powerdown or
output enable is initiated, thus preventing output glitches.
Crystal Oscillator Tuning Circuit
The CY2039 contains a unique tuning circuit to fine-tune the
output frequency of the device. The tuning circuit consists of
an array of eleven load capacitors on both sides of the oscilla-
tor drive inverter. The capacitor load values are EPROM pro-
grammable and can be increased in small increments. As the
capacitor load is increased the circuit is fine-tuned to a lower
frequency. The capacitor load values vary from 0.17 pF to 8 pF
for a 100:1 total control ratio. The tuning increments are shown
in the table on page 3. Please refer to the "7C80320 Program-
ming Specification" for further details.
EPROM Adjustable Features
Output divider selection
Oscillator Tuning (load capacitance values)
Duty cycle levels (TTL or CMOS)
Power management mode (OE or PWR_DWN)
Power management timing
(synchronous or asynchronous)
Die Pad Summary
Name
Die
Pad
Description
V
DD
1,2
Voltage supply
V
SS
8,9
Ground
X
D
4
Crystal connection
X
G
6
Crystal connection
PWR_DWN / OE 7
EPROM programmable power down or output enable pad. Weak pull up.
CLKOUT
11
Clock output. Weak pull down.
N/C
3, 5,10
No Connect. (Do not bond to these pads)
CY2039
Document #: 38-07355 Rev. **
Page 3 of 8
Device Functionality: Output Frequencies
Crystal Oscillator Tuning Circuit
Symbol
Description
Condition
Min.
Max.
Unit
Fo
Output frequency
V
DD
= 4.5V5.5V
1.25
30
MHz
V
DD
= 3.0V3.6V
1.25
30
MHz
Symbol
Description
Min
Typ
Max
Unit
R
f
Feedback resistor, V
DD
= 4.5V5.5V
Feedback resistor, V
DD
= 3.0V3.6V
0.5
1.0
2
4
3.5
9.0
M
M
Capacitors have 20% Tolerance
C
g
Gate capacitor
13
pF
C
d
Drain Capacitor
9
pF
C
0
Series Cap
0.27
pF
C
1
Series Cap
0.52
pF
C
2
Series Cap
1.00
pF
C
3
Series Cap
0.7
pF
C
4
Series Cap
1.4
pF
C
5
Series Cap
2.6
pF
C
6
Series Cap
5.0
pF
C
7
Series Cap
0.45
pF
C
8
Series Cap
0.85
pF
C
9
Series Cap
1.7
pF
C
10
Series Cap
3.3
pF
C = LOAD CAPACITOR
C6
C5
C4
C3
C2
C1
C0
C7
C8
C9
C10
External Crystal
Cg Cd
Rf
CY2039
Document #: 38-07355 Rev. **
Page 4 of 8
Absolute Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Supply Voltage ..................................................0.5 to +7.0V
Input Voltage ............................................0.5V to V
DD
+0.5V
Storage Temperature (Non-Condensing) ... 55C to +150C
Junction Temperature ................................ 40
C to +100
C
Static Discharge Voltage ......................................... >=2000V
(per MIL-STD-883, Method 3015)
Operating Conditions
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage (3.3V)
Supply Voltage (5.0V)
3.0
4.5
3.6
5.5
V
V
T
AJ
[1]
Operating Temperature, Junction
40
+100
C
C
TTL
Max. Capacitive Load on outputs for TTL levels
25
pF
C
CMOS
Max. Capacitive Load on outputs for CMOS levels
25
pF
X
REF
Reference Frequency, input crystal
10
30
MHz
Electrical Characteristics
Over the Operating Range
[2]
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
V
IL
Low-level Input Voltage
V
DD
= 4.5V5.5V
V
DD
= 3.0V3.6V
0.8
0.2V
DD
V
V
V
IH
High-level Input Voltage
V
DD
= 4.5V5.5V
V
DD
= 3.0V3.6V
2.0
0.7V
DD
V
V
V
OL
Low-level Output Voltage
V
DD
= 4.5V5.5V, I
OL
= 16 mA
V
DD
= 3.0V3.6V, I
OL
= 8 mA
0.4
0.4
V
V
V
OHCMOS
High-level Output Voltage,
CMOS levels
V
DD
= 4.5V5.5V, I
OH
= 16 mA
V
DD
= 3.0V3.6V, I
OH
= 8 mA
V
DD
0.4
V
DD
0.4
V
V
V
OHTTL
High-level Output Voltage,
TTL levels
V
DD
= 4.5V5.5V, I
OH
= 8 mA
2.4
V
I
IL
Input Low Current
V
IN
= 0V
10
A
I
IH
Input High Current
V
IN
= V
DD
5
A
I
DD
Power Supply Current,
Unloaded
V
DD
= 4.5V5.5V
V
DD
= 3.0V3.6V
45
25
mA
mA
I
DDS
Stand-by current
V
DD
= 3.0V3.6V
10
50
A
R
UP
Input Pull-Up Resistor
V
DD
= 4.5V5.5V, V
IN
= 0V
V
DD
= 4.5V5.5V, V
IN
= 0.7V
DD
1.1
50
3.0
100
8.0
200
M
k
I
OE_CLKOUT
CLKOUT Pulldown current
V
DD
= 5.0
20
A
Note:
1.
This product is sold in die form so operating conditions are specified for the die, or junction temperature.
2.
The part was characterized in a 20-pin SOIC package with external crystal; Electrical Characteristics may change with other package types.
CY2039
Document #: 38-07355 Rev. **
Page 5 of 8
Output Clock Switching Characteristics
Over the Operating Range
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Unit
t
1w
Output Duty Cycle at
1.4V, V
DD
= 4.55.5V
t
1w
= t
1A
t
1B
130 MHz, C
L
<= 25 pF (TTL output)
45
55
%
t
1x
Output Duty Cycle at
V
DD
/2, V
DD
= 4.55.5V
t
1x
= t
1A
t
1B
130 MHz, C
L
<= 25 pF (CMOS output)
45
55
%
t
1y
Output Duty Cycle at
V
DD
/2, V
DD
= 3.03.6V
t
1y
= t
1A
t
1B
130 MHz, C
L
<= 25 pF (CMOS output)
45
55
%
t
2t
Output Clock Rise time
Between 0.8V2.0V, V
DD
= 4.5V5.5V
2.0
ns
t
2c
Output Clock Rise time
Between 0.2V
DD
0.8V
DD
, V
DD
= 4.5V5.5V
Between 0.2V
DD
0.8V
DD
, V
DD
= 3.0V3.6V
4.0
4.0
ns
ns
t
3t
Output Clock Fall time
Between 2.0V0.8V, V
DD
= 4.5V5.5V
2.0
ns
t
3c
Output Clock Fall time
Between 0.8V
DD
0.2V
DD
, V
DD
= 4.5V5.5V
Between 0.8V
DD
0.2V
DD
, V
DD
= 3.0V3.6V
4.0
4.0
ns
ns
t
4
Start-Up Time Out of
Power-Down
PWR_DWN pin transition LOW to HIGH until output
stable
5
10
ms
t
5a
Power Down Delay Time
(synchronous setting)
From PWR_DWN pin at or below V
IL
to output LOW
(T = period of output clk)
T/2
T+10
ns
t
5b
Power Down Delay Time
(asynchronous setting)
From PWR_DWN pin at or below V
IL
to output LOW
10
15
ns
t
6
Power Up Time
From power on at or above VDD-10% to within fre-
quency specification.
[3]
5
10
ms
t
7a
Output Disable Time
(synchronous setting)
From OE pin at or below V
IL
to output Hi-Z
(T = period of output clk)
T/2
T+10
ns
t
7b
Output Disable Time
(asynchronous setting)
From OE pin at or below V
IL
to output Hi-Z
10
15
ns
t
8
Output Enable Time
OE pin LOW to HIGH
(T = period of output clk)
1.5T+25
ns
t
9
RMS Period Jitter
Over 6000 cycles
25
ps
t
10
Cycle to Cycle Jitter
Over 6000 cycles
100
ps
Note:
3.
Oscillator start time cannot be guaranteed for all crystal types. This specification is for operation with AT cut crystals with ESR < 70 ohms.
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