One-PLL General-Purpose Flash-Programmable
and 2-Wire Serially Programmable Clock Generator
CY22150
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07104 Rev. *D
Revised May 17, 2003
Features
Benefits
Integrated phase-locked loop (PLL)
Internal PLL to generate six outputs up to 200 MHz. Able to generate custom
frequencies from an external crystal or a driven source.
Commercial and industrial operation
Performance guaranteed for applications that require an extended temper-
ature range.
Flash-programmable
Nonvolatile reprogrammable technology allows easy customization, quick
turnaround on design changes and product performance enhancements,
and better inventory control. Parts can be reprogrammed up to 100 times,
reducing inventory of custom parts and providing an easy method for
upgrading existing designs.
Field-programmable
The CY22150 can be programmed at the package level. In-house
programming of samples and prototype quantities is available using the
CY3672 FTG Development Kit. Production quantities are available through
Cypress's value-added distribution partners or by using third party
programmers from BP Microsystems
, HiLo Systems
, and others.
2-wire serial programming interface
The CY22150 provides an industry-standard interface for volatile,
system-level customization of unique frequencies and options. Serial
programming and reprogramming allows quick design changes and product
enhancements, eliminates inventory of old design parts, and simplifies
manufacturing.
Low-skew, low-jitter, high-accuracy outputs High performance suited for commercial, industrial, networking, telecomm
and other general-purpose applications.
3.3V operation with 2.5V output option
Application compatibility in standard and low-power systems.
16-lead TSSOP
Industry-standard packaging saves on board space.
Logic Block Diagram
SPI
Control
VDDL
AVDD
VSS
AVSS
SDAT
SCLK
Serial
VSSL
VDD
XIN
XOUT
LCLK1
Divider
PLL
OSC.
LCLK3
Q
P
VCO
LCLK2
LCKL4
CLK5
CLK6
Bank 1
Divider
Bank 2
Crosspoint
Switch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
SCLK
LCLK1
XIN
XOUT
VDD
SDAT
AVSS
LCLK3
LCLK2
CLK6
CLK5
AVDD
VDDL
LCLK4
Pin Configuration
Programming
Interface
Matrix
CY22150
Document #: 38-07104 Rev. *D
Page 2 of 13
Frequency Calculation and Register Definitions
The CY22150 is an extremely flexible clock generator with four
basic variables that can be used to determine the final output
frequency. They are the input reference frequency (REF), the
internally calculated P and Q dividers, and the post divider,
which can be a fixed or calculated value. There are three basic
formulas for determining the final output frequency of a
CY22150-based design:
CLK = ((REF * P)/Q)/Post Divider
CLK = REF/Post Divider
CLK = REF.
The basic PLL block diagram is shown in Figure 1. Each of the
six clock outputs on the CY22150 has a total of seven output
options available to it. There are six post divider options
available: /2 (two of these), /3, /4, /DIV1N and /DIV2N. DIV1N
and DIV2N are independently calculated and are applied to
individual output groups. The post divider options can be
applied to the calculated VCO frequency ((REF*P)/Q) or to the
REF directly.
In addition to the six post divider output options, the seventh
option bypasses the PLL and passes the REF directly to the
crosspoint switch matrix.
Note:
1.
Float XOUT if XIN is driven by an external clock source.
Part Number
Outputs
Input Frequency Range
Output Frequency Range
Specifications
CY22150FC
6
8 MHz30 MHz (external crystal)
1 MHz133 MHz (driven clock)
80 kHz200 MHz (3.3V)
80 KHz166.6 MHz (2.5V)
Field programmable
Serially programmable
Commercial temperature
CY22150FI
6
8 MHz30 MHz (external crystal)
1 MHz133 MHz (driven clock)
80 kHz 166.6 MHz (3.3V)
80 KHz 150 MHz (2.5V)
Field programmable
Serially programmable
Industrial temperature
Pin Summary
Pin Name
Pin Number
Pin Description
XIN
1
Reference Input. Driven by a crystal (8 MHz 30 MHz) or external clock (1 MHz 133 MHz).
Programmable input load capacitors allow for maximum flexibility in selecting a crystal,
regardless of manufacturer, process, performance, or quality.
VDD
2
3.3V voltage supply
AVDD
3
3.3V analog voltage supply
SDAT
4
Serial data input
AVSS
5
Analog ground
VSSL
6
LCLK ground
LCLK1
7
Configurable clock output 1 at V
DDL
level (3.3V or 2.5V)
LCLK2
8
Configurable clock output 2 at V
DDL
level (3.3V or 2.5V)
LCLK3
9
Configurable clock output 3 at V
DDL
level (3.3V or 2.5V)
SCLK
10
Serial clock input
VDDL
11
LCLK voltage supply (2.5V or 3.3V)
LCLK4
12
Configurable clock output 4 at V
DDL
level (3.3V or 2.5V)
VSS
13
Ground
CLK5
14
Configurable clock output 5 (3.3V)
CLK6
15
Configurable clock output 6 (3.3V)
XOUT
[1]
16
Reference output
CY22150
Document #: 38-07104 Rev. *D
Page 3 of 13
Default Start-up Condition for the CY22150
The default (programmed) condition of the device is generally
set by the distributor who programs the device using a
customer-specific JEDEC file produced by CyClocksRT
.
Parts shipped from the factory are blank and unprogrammed.
In this condition, all bits are set to 0, all outputs are
three-stated, and the crystal oscillator circuit is active.
While you can develop your own subroutine to program any or
all of the individual registers described in the following pages,
it may be easier to use CyClocksRT to produce the required
register setting file.
The serial interface address of the CY22150 is 69H. Should
there be a conflict with any other devices in your system, this
can also be changed using CyClocksRT.
Frequency Calculations and Register Defini-
tions Using the Serial Programming Interface
The CY22150 provides an industry standard serial interface
for volatile, in-system programming of unique frequencies and
options. Serial programming and reprogramming allows for
quick design changes and product enhancements, eliminates
inventory of old design parts, and simplifies manufacturing.
The Serial Programming Interface (SPI) provides volatile
programming, i.e., when the target system is powered down,
the CY22150 reverts to its pre-SPI state, as defined above
(programmed or unprogrammed). When the system is
powered back up again, the SPI registers will need to be
reconfigured again.
All programmable registers in the CY22150 are addressed
with eight bits and contain eight bits of data. The CY22150 is
a slave device with an address of 1101001 (69H).
Table 1 lists the SPI registers and their definitions. Specific
register definitions and their allowable values are listed below.
Reference Frequency
The REF can be a crystal or a driven frequency. For crystals,
the frequency range must be between 8 MHz and 30 MHz. For
a driven frequency, the frequency range must be between
1 MHz and 133 MHz.
Using a Crystal as the Reference Input
The input crystal oscillator of the CY22150 is an important
feature because of the flexibility it allows the user in selecting
a crystal as a REF source. The input oscillator has program-
mable gain, allowing for maximum compatibility with a
reference crystal, regardless of manufacturer, process, perfor-
mance and quality.
Programmable Crystal Input Oscillator Gain Settings
The Input crystal oscillator gain (XDRV) is controlled by two
bits in register 12H, and are set according to Table 2. The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
manufacturer), and the CapLoad setting during crystal
start-up.
(Q+2)
VCO
(2(PB+4)+PO)
/2
/3
/2
LCLK1
LCLK2
LCLK3
LCLK4
CLK5
CLK6
CLKSRC
Crosspoint
Switch Matrix
[44H]
[44H]
[44H,45H]
[45H]
[45H,46H]
DIV2
CL
K
REF
PFD
Divider Bank 1
[45H]
DIV1SRC [OCH]
/4
DIV2SRC [47H]
Divider Bank 2
DIV1N [OCH]
DIV2N [47H]
DIV1
CL
K
/DIV1N
1
0
1
0
[42H]
[40H], [41H], [42H]
/DIV2N
Qtotal
Ptotal
CLKOE [09H]
Figure 1. Basic Block Diagram of CY22150 PLL
CY22150
Document #: 38-07104 Rev. *D
Page 4 of 13
Bits 3 and 4 of register 12H control the input crystal oscillator
gain setting. Bit 4 is the MSB of the setting, and bit 3 is the
LSB. The setting is programmed according to Table 2. All other
bits in the register are reserved and should be programmed as
shown in Table 3.
Using an External Clock as the Reference Input
The CY22150 can also accept an external clock as reference,
with speeds up to 133 MHz. With an external clock, the XDRV
(register 12H) bits must be set according to Table 4.
Table 1. Summary Table CY22150 Programmable Registers
Register
Description
D7
D6
D5
D4
D3
D2
D1
D0
09H
CLKOE control
0
0
CLK6
CLK5
LCLK4
LCLK3
LCLK2
LCLK1
OCH
DIV1SRC mux and
DIV1N divider
DIV1SRC DIV1N(6)
DIV1N(5)
DIV1N(4)
DIV1N(3)
DIV1N(2)
DIV1N(1)
DIV1N(0)
12H
Input crystal oscillator
drive control
0
0
1
XDRV(1)
XDRV(0)
0
0
0
13H
Input load capacitor
control
CapLoad
(7)
CapLoad
(6)
CapLoad
(5)
CapLoad
(4)
CapLoad
(3)
CapLoad
(2)
CapLoad
(1)
CapLoad
(0)
40H
Charge Pump and PB
counter
1
1
0
Pump(2)
Pump(1)
Pump(0)
PB(9)
PB(8)
41H
PB(7)
PB(6)
PB(5)
PB(4)
PB(3)
PB(2)
PB(1)
PB(0)
42H
PO counter, Q
counter
PO
Q(6)
Q(5)
Q(4)
Q(3)
Q(2)
Q(1)
Q(0)
44H
Crosspoint switch
matrix control
CLKSRC2
for LCLK1
CLKSRC1
for LCLK1
CLKSRC0
for LCLK1
CLKSRC2
for LCLK2
CLKSRC1
for LCLK2
CLKSRC0
for LCLK2
CLKSRC2
for LCLK3
CLKSRC1
for LCLK3
45H
CLKSRC0
for LCLK3
CLKSRC2
for LCLK4
CLKSRC1
for LCLK4
CLKSRC0
for LCLK4
CLKSRC2
for CLK5
CLKSRC1
for CLK5
CLKSRC0
for CLK5
CLKSRC2
for CLK6
46H
CLKSRC1
for CLK6
CLKSRC0
for CLK6
1
1
1
1
1
1
47H
DIV2SRC mux and
DIV2N divider
DIV2SRC DIV2N(6)
DIV2N(5)
DIV2N(4)
DIV2N(3)
DIV2N(2)
DIV2N(1)
DIV2N(0)
Table 2. Programmable Crystal Input Oscillator Gain Settings
Calculated CapLoad Value
00H 20H
20H 30H
30H 40H
Crystal ESR
30
60
30
60
30
60
Crystal Input
Frequency
8 15 MHz
00
01
01
10
01
10
15 20 MHz
01
10
01
10
10
10
20 25 MHz
01
10
10
10
10
11
25 30 MHz
10
10
10
11
11
N/A
Table 3. Bit Locations and Values
Address
D7
D6
D5
D4
D3
D2
D1
D0
12H
0
0
1
XDRV(1)
XDRV(0)
0
0
0
Table 4. Programmable External Reference Input Oscillator Drive Settings
Reference Frequency
1 25 MHz
25 50 MHz
50 90 MHz
90 133 MHz
Drive Setting
00
01
10
11
CY22150
Document #: 38-07104 Rev. *D
Page 5 of 13
Input Load Capacitors
Input load capacitors allow the user to set the load capacitance
of the CY22150 to match the input load capacitance from a
crystal. The value of the input load capacitors is determined by
8 bits in a programmable register [13H]. Total load capacitance
is determined by the formula:
CapLoad = (CL CBRD CCHIP)/0.09375 pF
where:
C
L
= specified load capacitance of your crystal.
C
BRD
= the total board capacitance, due to external capac-
itors and board trace capacitance. In CyClocksRT, this value
defaults to 2 pF.
C
CHIP
= 6 pF.
0.09375 pF = the step resolution available due to the 8-bit
register.
In CyclocksRT, only the crystal capacitance (C
L
) is specified.
C
CHIP
is set to 6 pF, and C
BRD
defaults to 2 pF. If your board
capacitance is higher or lower than 2 pF, the formula above
can be used to calculate a new CapLoad value and
programmed into register 13H.
In CyClocksRT, enter the crystal capacitance (C
L
). The value
of CapLoad will be determined automatically and programmed
into the CY22150. Through the SDAT and SCLK pins, the
value can be adjusted up or down if your board capacitance is
greater or less than 2 pF. For an external clock source,
CapLoad defaults to 0. See Table 5 for CapLoad bit locations
and values.
The input load capacitors are placed on the CY22150 die to
reduce external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency
shift that occurs when non-linear load capacitance is affected
by load, bias, supply and temperature changes.
PLL Frequency, Q Counter [42H(6..0)]
The first counter is known as the Q counter. The Q counter
divides REF by its calculated value. Q is a 7 bit divider with a
maximum value of 127 and minimum value of 0. The primary
value of Q is determined by 7 bits in register 42H (6..0), but 2
is added to this register value to achieve the total Q, or Q
total
.
Q
total
is defined by the formula:
Q
total
= Q + 2
The minimum value of Q
total
is 2. The maximum value of Q
total
is 129. Register 42H is defined in the table.
Stable operation of the CY22150 cannot be guaranteed if
REF/Q
total
falls below 250 kHz. Q
total
bit locations and values
are defined in Table 6.
PLL Frequency, P Counter [40H(1..0)], [41H(7..0)],
[42H(7)
The next counter definition is the P (product) counter. The P
counter is multiplied with the (REF/Q
total
) value to achieve the
VCO frequency. The product counter, defined as P
total
, is
made up of two internal variables, PB and PO. The formula for
calculating P
total
is:
P
total
= (2(PB + 4) + PO).
PB is a 10-bit variable, defined by registers 40H(1:0) and
41H(7:0). The 2 LSBs of register 40H are the two MSBs of
variable PB. Bits 4..2 of register 40H are used to determine the
charge pump settings (see Section 5). The 3 MSBs of register
40H are preset and reserved and cannot be changed. PO is a
single bit variable, defined in register 42H(7). This allows for
odd numbers in P
total
.
The remaining seven bits of 42H are used to define the Q
counter, as shown in Table 6.
The minimum value of P
total
is 8. The maximum value of P
total
is 2055. To achieve the minimum value of P
total
, PB and PO
should both be programmed to 0. To achieve the maximum
value of P
total
, PB should be programmed to 1023, and PO
should be programmed to 1.
Stable operation of the CY22150 cannot be guaranteed if the
value of (P
total
*(REF/Q
total
)) is above 400 MHz or below
100 MHz. Registers 40H, 41H and 42H are defined in Table 7.
PLL Post Divider Options [OCH(7..0)], [47H(7..0)]
The output of the VCO is routed through two independent
muxes, then to two divider banks to determine the final clock
output frequency. The mux determines if the clock signal
feeding into the divider banks is the calculated VCO frequency
or REF. There are two select muxes (DIV1SRC and DIV2SRC)
and two divider banks (Divider Bank 1 and Divider Bank 2)
used to determine this clock signal. The clock signal passing
through DIV1SRC and DIV2SRC is referred to as DIV1CLK
and DIV2CLK, respectively.
The divider banks have 4 unique divider options available: /2,
/3, /4, and /DIVxN. DIVxN is a variable that can be indepen-
dently programmed (DIV1N and DIV2N) for each of the two
divider banks. The minimum value of DIVxN is 4. The
maximum value of DIVxN is 127. A value of DIVxN below 4 is
not guaranteed to work properly.
DIV1SRC is a single bit variable, controlled by register OCH.
The remaining seven bits of register OCH determine the value
of post divider DIV1N.
DIV2SRC is a single bit variable, controlled by register 47H.
The remaining seven bits of register 47H determine the value
of post divider DIV2N.
Register OCH and 47H are defined in Table 8.
Charge Pump Settings [40H(2..0)]
The correct pump setting is important for PLL stability. Charge
pump settings are controlled by bits (4..2) of register 40H, and
are dependent on internal variable PB (see "PLL Frequency,
P Counter[40H(1..0)], [41H(7..0)], [42H(7)]"). Table 9 summa-
rizes the proper charge pump settings, based on Ptotal.
See Table 10 for register 40H bit locations and values.
Table 5. Input Load Capacitor Register Bit Settings
Address
D7
D6
D5
D4
D3
D2
D1
D0
13H
CapLoad(7)
CapLoad(6)
CapLoad(5)
CapLoad(4)
CapLoad(3)
CapLoad(2)
CapLoad(1)
CapLoad(0)
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