Pentium

/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/

Mobile PCs with Intel

82430TX and 2 DIMMs or 3 SO-DIMMs

CY2277A

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07332 Rev. *A

Revised December 7, 2002

Features

· Mixed 2.5V and 3.3V operation
· Complete clock solution to meet requirements of Pen-

tium

, Pentium

II, 6x86, or K6 motherboards

-- Four CPU clocks at 2.5V or 3.3V
-- Up to eight 3.3V SDRAM clocks
-- Seven 3.3V synchronous PCI clocks, one free

running

-- Two 3.3V USB/IO clocks at 48 or 24 MHz, selectable

by serial interface

-- One 2.5V IOAPIC clock at 14.318 MHz
-- Two 3.3V Ref. clocks at 14.318 MHz

· Factory-EPROM programmable CPU, PCI, and USB/IO

clock frequencies for custom configuration

· Factory-EPROM programmable output drive and slew

rate for EMI customization

· MODE Enable pin for CPU_STOP and PCI_STOP
· SMBus serial configuration interface
· Available in space-saving 48-pin SSOP and TSSOP

packages.

Functional Description

The CY2277A is a Clock Synthesizer/Driver for Pentium, Pen-
tium II, 6X86, and K6 portable PCs designed with the Intel

82430TX or similar chipsets. There are three available options
as shown in the selector guide

The CY2277A outputs four CPU clocks at 2.5V or 3.3V with up
to nine selectable frequencies. There are up to eight 3.3V
SDRAM clocks and seven PCI clocks, running at one half the
CPU clock frequency. One of the PCI clocks is free-running.
Additionally, the part outputs two 3.3V USB/IO clocks at 48
MHz or 24 MHz, one 2.5V IOAPIC clock at 14.318 MHz, and
two 3.3V reference clocks at 14.318 MHz. The CPU, PCI,
USB, and IO clock frequencies are factory-EPROM program-
mable for easy customization with fast turnaround times.

The CY2277A has power-down, CPU stop and PCI stop pins
for power management control. The CPU stop and PCI stop
are controlled by the MODE pin. They are multiplexed with
SDRAM clock outputs, and are selected when the MODE pin
is driven LOW. Additionally, these inputs are synchronized
on-chip, enabling glitch-free transitions. When the
CPU_STOP input is asserted, the CPU outputs are driven
LOW. When the PCI_STOP input is asserted, the PCI outputs
(except the free-running PCI clock) are driven LOW. Finally,
when the PWR_DWN pin is asserted, the reference oscillator
and PLLs are shut down, and all outputs are driven LOW.

The CY2277A outputs are designed for low EMI emission.
Controlled rise and fall times, unique output driver circuits and
factory-EPROM programmable output drive and slew-rate en-
able optimal configurations for EMI control.

CY2277A Selector Guide

Note:

One free-running PCI clock.

Clock Outputs

-1/-1M

-3

-7M

-12/

-12M/

-12I

CPU (60, 66.6 MHz)

CPU (33.3, 66.6 MHz)

CPU (SMBus select-
able)

PCI (CPU/2)

[1]

SDRAM

6/8

USB/IO (48 or 24 MHz)

IOAPIC (14.318 MHz)

Ref (14.318 MHz)

CPU-PCI delay

16 ns

<1 ns

14 ns

EPROM

Pin Configuration

Logic Block Diagram

XTALOUT

XTALIN

IOAPIC (14.318 MHz)

14.318

MHz

OSC.

SDRAM[05]

SEL

SDRAM7/PCI_STOP

DDQ2

CPU

PLL

MODE

SYS

PLL

Delay

1
2
3
4

5
6

7
8
9
10
11
12

33
32
31

30
29

36
35

REF1

SSOP

Top View

14
15
16
17
18

19
20
21
22
23
24

45
44
43
42
41

48
47
46

2277

-
1,-1M

,
-3,

-
7M

,-12,

-12M

,-12

REF0

XTALIN

XTALOUT

MODE

DDQ3

PCICLK_F

PCICLK0

PCICLK1
PCICLK2

PCICLK3
PCICLK4

DDQ3

PCICLK5

SEL

SDATA

SCLK

DDQ3

USBCLK/IOCLK
USBCLK/IOCLK

PWR_SEL
V

DDQ2

IOAPIC
PWR_DWN
V

CPUCLK0
CPUCLK1
V

DDCPU

CPUCLK2
CPUCLK3
V

SDRAM0
SDRAM1
V

DDQ3

SDRAM2

SDRAM3
V

SDRAM4
SDRAM5
V

DDQ3

SDRAM6/CPU_STOP
SDRAM7/PCI_STOP
AV

SCLK

SDATA

REF [01]
(14.318)

CPUCLK[03]

DDCPU

SDRAM6/CPU_STOP

PCI[05]

PCICLK_F

USBCLK/IOCLK[0:1]

STOP

INTERFACE

CONTROL

LOGIC

SERIAL

LOGIC

Divide and
Mux Logic

PWR_DWN

CY2277A

Document #: 38-07332 Rev. *A

Page 2 of 19

Pin Summary

Name

Pins

Description

DDQ3

7, 15, 21, 28, 34

3.3V Digital voltage supply

DDQ2

IOAPIC Digital voltage supply, 2.5V

DDCPU

CPU Digital voltage supply, 2.5V or 3.3V

25, 48

3.3V Analog voltage supply

3, 10, 17, 24, 31, 37, 43

Ground

XTALIN

[2]

Reference crystal input

XTALOUT

[2]

Reference crystal feedback

MODE

Mode select input, enables power management features

SEL

Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function
tables.)

SDATA

SMBus serial data input for serial configuration port

SCLK

SMBus serial clock input for serial configuration port

PWR_DWN

Active low control input to put osc., PLLs, and outputs in power down state

PWR_SEL

Power select input, indicates whether V

DDCPU

is at 2.5V or 3.3V

HIGH = 3.3V, LOW=2.5V (internal pull-up to V

)

SDRAM7/PCI_STOP

SDRAM clock output. Also, active LOW control input to stop PCI clocks,
enabled when MODE is LOW

SDRAM6/CPU_STOP

SDRAM clock output. Also, active LOW control input to stop CPU clocks,
enabled when MODE is LOW

SDRAM[0:5]

36, 35, 33, 32, 30, 29

SDRAM clock outputs, have same frequency as CPU clocks

CPUCLK[0:3]

42, 41, 39, 38

CPU clock outputs

PCICLK[0:5]

9, 11, 12, 13, 14, 16

PCI clock outputs

PCICLK_F

PCI clock output, free-running

IOAPIC

IOAPIC clock output

REF[0:1]

1, 2

Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load

USBCLK/IOCLK

22, 23

USB or IO clock outputs, frequency selected by serial word

Note:

For best accuracy, use a parallel-resonant crystal, C

LOAD

= 18 pF.

CY2277A

Document #: 38-07332 Rev. *A

Page 3 of 19

CPU and PCI Clock Driver Strengths

· Matched impedances on both rising and falling edges on

the output drivers

· Output impedance: 25

(typical) measured at 1.5V

Notes:

On power-up, the default frequency on these outputs is 48 MHz.

Meets Intel USB clock requirements.

Function Table (-1, -1M, -7M, -12, -12M, -12I)

SEL

XTALIN

CPUCLK[0:3]

SDRAM[0:7]

PCICLK[0:5]

PCICLK_F

REF[0:1]

IOAPIC

USBCLK / IOCLK

[3]

14.318 MHz

60.0 MHz

30.0 MHz

14.318 MHz

48.0 MHz / 24.0 MHz

14.318 MHz

66.67 MHz

33.33 MHz

14.318 MHz

48.0 MHz / 24.0 MHz

Function Table (-3)

SEL

XTALIN

CPUCLK[0:3]

SDRAM[0:7]

PCICLK[0:5]

PCICLK_F

REF[0:1]

IOAPIC

USBCLK / IOCLK

[3]

14.318 MHz

33.33 MHz

16.67 MHz

14.318 MHz

48.0 MHz / 24.0 MHz

14.318 MHz

66.67 MHz

33.33 MHz

14.318 MHz

48.0 MHz / 24.0 MHz

Actual Clock Frequency Values (-1, -1M, -3, -7M,
-12, -12M, -12I)

Clock Output

Target

Frequency

(MHz)

Actual

Frequency

(MHz)

PPM

CPUCLK,
SDRAM

66.67

66.654

195

CPUCLK,
SDRAM

60.0

USBCLK

[4]

48.0

48.008

167

IOCLK

24.0

24.004

167

CY2277A

Document #: 38-07332 Rev. *A

Page 4 of 19

Serial Configuration Map

· The Serial bits will be read by the clock driver in the following

order:

Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0

Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0

· Reserved and unused bits should be programmed to "0".
· SMBus Address for the CY2277A is:

Power Management Logic

CPU_STOP

PCI_STOP

PWR_DWN

CPUCLK

PCICLK

PCICLK_F

Other Clocks

Osc.

PLLs

LOW

Stopped

Off

LOW

Running

LOW

33/30 MHz

Running

66/60 MHz

LOW

Running

66/60 MHz

33/30 MHz

Running

R/W

----

Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)

Bit

Pin #

Description

Bit 7 --

(Reserved) drive to `0'

Bit 6 --

(Reserved) drive to `0' on -1, -1M, -3, -7M, -12,
-12M, -12I

Bit 5 --

(Reserved) drive to `0' on -1, -1M, -3, -7M, -12,
-12M, -12I

Bit 4 --

(Reserved) drive to `0' on -1, -1M, -3, -7M, -12,
-12M, -12I

Bit 3 23

48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz

Bit 2 22

48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz

Bit 1
Bit 0

Bit 1
1
1
0
0

Bit 0
1 - Three-State (see table below)
0 - N/A
1 - Test Mode (see table below)
0 - Normal Operation

Select Functions

Functional Description

Outputs

CPU

PCI, PCI_F

SDRAM

Ref

IOAPIC

IOCLK

USBCLK

Three-State

Hi-Z

Test Mode

TCLK/2

[5]

TCLK/4

TCLK/2

TCLK

TCLK/4

TCLK/2

Note:

TCLK supplied on the XTALIN, PIN 4.

CY2277A

Document #: 38-07332 Rev. *A

Page 5 of 19

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Supply Voltage ..................................................0.5 to +7.0V

Input Voltage ............................................ 0.5V to V

+ 0.5

Storage Temperature (Non-Condensing) .... 65

C to +150

Junction Temperature ............................................... +150

Package Power Dissipation.............................................. 1W

Static Discharge Voltage............................................ >2000V
(per MIL-STD-883, Method 3015, like V

pins tied together)

Byte 1: CPU, 24/48 MHz Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

48/24 MHz (Active/Inactive)

Bit 6

48/24 MHz (Active/Inactive)

Bit 5

(Reserved) drive to `0'

Bit 4

N/A

Not Used, drive 0

Bit 3

CPUCLK3 (Active/Inactive)

Bit 2

CPUCLK2 (Active/Inactive)

Bit 1

CPUCLK1 (Active/Inactive)

Bit 0

CPUCLK0 (Active/Inactive)

Byte 3: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

SDRAM7 (Active/Inactive)

Bit 6

SDRAM6 (Active/Inactive)

Bit 5

SDRAM5 (Active/Inactive)

Bit 4

SDRAM4 (Active/Inactive)

Bit 3

SDRAM3 (Active/Inactive)

Bit 2

SDRAM2 (Active/Inactive)

Bit 1

SDRAM1 (Active/Inactive)

Bit 0

SDRAM0 (Active/Inactive)

Byte 5: Peripheral Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

(Reserved) drive to `0'

Bit 6

(Reserved) drive to `0'

Bit 5

(Reserved) drive to `0'

Bit 4

IOAPIC (Active/Inactive)

Bit 3

(Reserved) drive to `0'

Bit 2

(Reserved) drive to `0'

Bit 1

REF1 (Active/Inactive)

Bit 0

REF0 (Active/Inactive)

Byte 2: PCI Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

(Reserved) drive to `0'

Bit 6

PCICLK_F (Active/Inactive)

Bit 5

PCICLK5 (Active/Inactive)

Bit 4

PCICLK4 (Active/Inactive)

Bit 3

PCICLK3 (Active/Inactive)

Bit 2

PCICLK2 (Active/Inactive)

Bit 1

PCICLK1 (Active/Inactive)

Bit 0

PCICLK0 (Active/Inactive)

Byte 4: SDRAM Active/Inactive
Register (1 = Active, 0 = Inactive), Default = Active

Bit

Pin #

Description

Bit 7

N/A

Not used, drive to `0'

Bit 6

N/A

Not used, drive to `0'

Bit 5

N/A

Not used, drive to `0'

Bit 4

N/A

Not used, drive to `0'

Bit 3

N/A

Not used, drive to `0'

Bit 2

N/A

Not used, drive to `0'

Bit 1

N/A

Not used, drive to `0'

Bit 0

N/A

Not used, drive to `0'

Byte 6: Reserved, for future use

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