100-MHz Pentium

II Clock Synthesizer/Driver with

Spread Spectrum for Mobile or Desktop PCs

CY2280

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07207 Rev. *A

Revised December 08, 2002

Features

· Mixed 2.5V and 3.3V operation
· Clock solution for Pentium® II, and other similar pro-

cessor-based motherboards

-- Four 2.5V CPU clocks up to 100 MHz
-- Eight 3.3V sync. PCI clocks, one free-running
-- Two 3.3V 48-MHz USB clocks
-- Three 3.3V Ref. clocks at 14.318 MHz
-- Two 2.5V APIC clocks at 14.318 MHz or PCI/2

· EMI control

-- Spread spectrum clocking

-- Factory-EPROM programmable spread spectrum

margin

-- Factory-EPROM programmable output drive and

slew rate

· Factory-EPROM programmable CPU clock frequencies

for custom configurations

· Available in space-saving 48-pin SSOP package

Functional Description

The CY2280 is a Spread Spectrum clock synthesizer/driver for
a Pentium II, or other similar processor-based PC requiring
100-MHz support. All of the required system clocks are provid-
ed in a space-saving 48-pin SSOP package. The CY2280 can
be used with the CY231x for a total solution for systems with
SDRAM.
The CY2280 provides the option of spread spectrum clocking
on the CPU and PCI clocks for reduced EMI. A downspread
percentage is introduced when the SEL_SS input is asserted.
The device can be run without spread spectrum when the
SEL_SS input is deasserted. The percentage of spreading is
EPROM-programmable to optimize EMI-reduction.

The CY2280 has power-down, CPU stop, and PCI stop pins
for power management control. The signals are synchronized
on-chip, and ensure glitch-free transitions on the outputs.
When the CPU_STOP input is asserted, the CPU clock out-
puts are driven LOW. When the PCI_STOP input is asserted,
the PCI clock outputs (except the free-running PCI clock) are
driven LOW. When the PWR_DWN pin is asserted, the refer-
ence oscillator and PLLs are shut down, and all outputs are
driven LOW.

CY2280 Selector Guide

CY2280 Configuration Options

Clock Outputs

11S

21S

CPU (66.6, 100 MHz)

PCI (CPU/2, CPU/3)

USB (48 MHz)

APIC (14.318 MHz)

APIC (PCI/2)

Reference (14.318 MHz)

CPU-PCI delay

1.5

4.0 ns

1.5

4.0 ns

1.5

4.0 ns

CPU-APIC delay

2.04.5 ns

Spread Spectrum (Downspread)

N/A

0.6%

Pentium is a registered trademark of Intel Corporation.

Logic Block Diagram

EPROM

XTALOUT

XTALIN

APIC [0:1]

14.318

MHz

OSC.

SEL0

DDAPIC

CPU

PLL

SEL100

Delay

REF [0-2]

CPUCLK [0-3]

DDCPU

PCI [1-7]

PCICLK_F

STOP

LOGIC

SEL1

USBCLK [0:1]

SYS PLL

CPU_STOP

PWR_DWN

Divider

PCI_STOP

DDPCI

DDREF

DDUSB

-1
-2

SEL_SS

CY2280

Document #: 38-07207 Rev. *A

Page 2 of 12

Pin Summary

Name

Pins

Description

DDPCI

15, 9

3.3V Digital voltage supply for PCI clocks

DDUSB

3.3V Digital voltage supply for USB clocks

DDREF

3.3V Digital voltage supply for REF clocks

DDAPIC

2.5V Digital voltage supply for APIC clocks

DDCPU

41, 37

2.5V Digital voltage supply for CPU clocks

33, 19

Analog voltage supply, 3.3V

3, 6, 12, 18, 20, 24, 32, 34, 38, 43 Ground

XTALIN

[1]

Reference crystal input

XTALOUT

[1]

Reference crystal feedback

PCI_STOP

Active LOW control input to stop PCI clocks

CPU_STOP

Active LOW control input to stop CPU clocks

PWR_DWN

Active LOW control input to power down device

SEL_SS

Spread spectrum select input (-11S and -21S options)

N/C

Spread spectrum select input (-1 option)

SEL0

CPU frequency select input, bit 0 (see Function Table)

SEL1

CPU frequency select input, bit 1 (see Function Table)

SEL100

CPU frequency select input, selects between 100 MHz and 66.6 MHz
(see Function Table)

CPUCLK[0:3]

40, 39, 36, 35

CPU clock outputs

PCICLK[1:7]

8, 10, 11, 13, 14, 16, 17

PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz
or 100 MHz respectively

PCICLK_F

Free-running PCI clock output

APIC[0:1]

45, 44

APIC clock outputs

REF[0:2]

1, 2, 47

3.3V Reference clock outputs

USBCLK[0:1]

22, 23

USB clock outputs

RESERVED

Reserved

Note:

For best accuracy, use a parallel-resonant crystal, C

LOAD

= 18 pF.

Pin Configurations

10
11

REF0

REF1

XTALIN

XTALOUT

PCICLK_F

PCICLK1

PCICLK2

DDPCI

PCICLK3

PCICLK4

DDPCI

PCICLK5

PCICLK7

DDUSB

USBCLK0
USBCLK1

DDREF

REF2

DDAPIC

APIC0

APIC1

RESERVED

DDCPU

CPUCLK0

CPUCLK1

DDCPU

CPUCLK2

CPUCLK3

PCI_STOP

PWR_DWN

N/C

SEL0
SEL1

SEL100

CPU_STOP

PCICLK6

10
11

REF0

REF1

XTALIN

XTALOUT

PCICLK_F

PCICLK1

PCICLK2

DDPCI

PCICLK3

PCICLK4

DDPCI

PCICLK5

PCICLK7

DDUSB

USBCLK0
USBCLK1

DDREF

REF2

DDAPIC

APIC0

APIC1

RESERVED

DDCPU

CPUCLK0

CPUCLK1

DDCPU

CPUCLK2

CPUCLK3

PCI_STOP

PWR_DWN

SEL_SS

SEL0
SEL1

SEL100

CPU_STOP

PCICLK6

CY2280-1

CY2280-11S
CY2280-21S

48-

n S

(

i
e

)

-pi

op V

i
ew

)

CY2280

Document #: 38-07207 Rev. *A

Page 3 of 12

Function Table (-11S Option)

SEL100

SEL1

SEL0

SEL_SS

[2]

CPU/PCI

Ratio

CPUCLK

PCICLK_F

PCICLK

REF

APIC USBCLK

N/A

Hi-Z

N/A

Reserved

14.318 MHz

48 MHz

N/A

Reserved

14.318 MHz

48 MHz

0 (downspread)

66.66 MHz 33.33 MHz

14.318 MHz

48 MHz

1 (no spread)

66.66 MHz 33.33 MHz

14.318 MHz

48 MHz

N/A

TCLK/2

TCLK/6

TCLK

[3]

TCLK

[3]

TCLK/2

N/A

Reserved

14.318 MHz

48 MHz

N/A

Reserved

14.318 MHz

48 MHz

0 (downspread)

100 MHz

33.33 MHz

14.318 MHz

48 MHz

1 (no spread)

100 MHz

33.33 MHz

14.318 MHz

48 MHz

Function Table (-21S Option)

SEL100

SEL1

SEL0

SEL_SS

[2]

CPU/PCI

Ratio

CPUCLK

PCICLK_F

PCICLK

REF

APIC USBCLK

N/A

Hi-Z

N/A

Reserved

14.318 MHz

Reserved

48 MHz

N/A

Reserved

14.318 MHz

Reserved

48 MHz

0 (downspread)

66.66 MHz 33.33 MHz

14.318 MHz

16.67 MHz

48 MHz

1 (no spread)

66.66 MHz 33.33 MHz

14.318 MHz

16.67 MHz

48 MHz

N/A

TCLK/2

TCLK/6

TCLK

[3]

TCLK/12

[3]

TCLK/2

N/A

Reserved

14.318 MHz

Reserved

48 MHz

N/A

Reserved

14.318 MHz

Reserved

48 MHz

0 (downspread)

100 MHz

33.33 MHz

14.318 MHz

16.67 MHz

48 MHz

1 (no spread)

100 MHz

33.33 MHz

14.318 MHz

16.67 MHz

48 MHz

Actual Clock Frequency Values

Clock Output

Target Frequency

(MHz)

Actual Frequency

(MHz)

PPM

CPUCLK

66.67

66.654

195

CPUCLK

100

99.77

2346

USBCLK

48.0

48.008

167

Power Management Logic

CPU_STOP

PCI_STOP

PWR_DWN

CPUCLK

PCICLK

PCICLK_F

Other

Clocks

Osc.

PLLs

Low

Off

Low

Running

Running Running

Low

Running

Running Running

Running

Low

Running

Running Running

Running

Running Running

Notes:

Target frequency is modulated by percentage shown (max.) when SEL_SS = 0.

TCLK supplied on the XTALIN pin in Test Mode.

CY2280

Document #: 38-07207 Rev. *A

Page 4 of 12

Maximum Ratings

(Above which the useful life may be impaired. For user guide-
lines, not tested.)

Supply Voltage .................................................0.5 to + 7.0V

Input Voltage ............................................ 0.5V to V

+ 0.5

Storage Temperature (Non-Condensing) ... 65

C to +150

Junction Temperature ............................................... +150

Package Power Dissipation.............................................. 1W

Static Discharge Voltage........................................... > 2000V
(per MIL-STD-883, Method 3015, like V

pins tied together)

Operating Conditions

[4]

Parameter

Description

Min.

Max.

Unit

, V

DDPCI

DDUSB

, V

DDREF

Analog and Digital Supply Voltage

3.135

3.465

DDCPU

CPU Supply Voltage

2.375

2.625

DDAPIC

APIC Supply Voltage

2.375

2.625

Operating Temperature, Ambient

Max. Capacitive Load on

CPUCLK
PCICLK
APIC, REF
USB

20
30
20
20

(REF)

Reference Frequency, Oscillator Nominal Value

14.318

MHz

Power-up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)

0.05

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

Min. Max. Unit

High-level Input Voltage

Except Crystal Inputs

[5]

2.0

Low-level Input Voltage

Except Crystal Inputs

[5]

0.8

High-level Output Voltage

[6]

DDCPU

= V

DDAPIC

= 2.375V

= 12 mA CPUCLK

2.0

= 18 mA APIC

Low-level Output Voltage

[6]

DDCPU

= V

DDAPIC

= 2.375V

= 12 mA

CPUCLK

0.4

= 18 mA

APIC

High-level Output Voltage

[6]

DDPCI

, AV

, V

DDREF

, V

DDUSB

= 3.135V I

= 14.5 mA PCICLK

2.4

= 16 mA USBCLK

= 16 mA REF

Low-level Output Voltage

[6]

DDPCI

, AV

, V

DDREF

DDUSB

= 3.135V I

= 9.4 mA PCICLK

0.4V

= 9 mA

USBCLK

= 9 mA

REF

Input High Current

= V

+10

Input Low Current

= 0V

Output Leakage Current

Three-state

+10

DD25

Power Supply Current for
2.5V Clocks

[6]

DDCPU

= 2.625V, V

= 0 or V

, Loaded Outputs, CPU = 66.6 MHz

DD25

Power Supply Current for
2.5V Clocks

[6]

DDCPU

= 2.625V, V

= 0 or V

, Loaded Outputs, CPU = 100 MHz

100

DD33

Power Supply Current for
3.3V Clocks

[6]

= 3.465V, V

= 0 or V

, Loaded Outputs

170

DDS

Power-down Current

[6]

Current draw in power-down state

500

CY2280

Document #: 38-07207 Rev. *A

Page 5 of 12

Notes:

Electrical parameters are guaranteed with these operating conditions.

Crystal Inputs have CMOS thresholds.

Parameter is guaranteed by design and characterization. Not 100% tested in production.

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

Min. Max. Unit

Switching Characteristics

[6, 7]

Parameter

Output

Description

Test Conditions

Min.

Typ.

Max.

Unit

All

Output Duty Cycle

[8]

= t

CPUCLK,
APIC

CPU and APIC Clock
Rising and Falling Edge
Rate

Between 0.4V and 2.0V

-1,-11S,
-21S

1.0

4.0

V/ns

PCICLK

PCI Clock Rising and
Falling Edge Rate

Between 0.4V and 2.4V

-1,-11S,
-21S

1.0

4.0

V/ns

USBCLK,
REF

USB, REF Rising and
Falling Edge Rate

Between 0.4V and 2.4V

0.5

2.0

V/ns

CPUCLK

CPU Clock Rise Time

Between 0.4V and 2.0V

-1,-11S,
-21S

0.4

1.6

CPUCLK

CPU Clock Fall Time

Between 2.0V and 0.4V

-1,-11S,
-21S

0.4

1.6

CPUCLK

CPU-CPU Clock Skew

Measured at 1.25V

100

175

CPUCLK,
PCICLK

CPU-PCI Clock Skew

[9]

Measured at 1.25V for 2.5V
clocks, and at 1.5V for 3.3V
clocks

-1,-11S,
-21S

1.5

4.0

PCICLK,
PCICLK

PCI-PCI Clock Skew

Measured at 1.5V

250

CPUCLK,
APIC

CPU-APIC Clock
Skew

[10]

Measured at 1.25V for 2.5V
clocks

-21S

2.0

4.5

APIC

APIC-APIC Clock Skew

Measured at 1.25V

100

175

CPUCLK

Cycle-Cycle Clock Jitter

Measured at 1.25V

-1,-11S,
-21S

200

250

PCICLK

Cycle-Cycle Clock Jitter

Measured at 1.5V

250

500

CPUCLK,
PCICLK

Power-up Time

CPU, PCI clock stabilization from
power-up

Notes:

All parameters specified with loaded outputs.

Duty cycle is measured at 1.5V when V

= 3.3V. When V

= 2.5V, duty cycle is measured at 1.25V.

PCI lags CPU for -11S and -21S options.

10. APIC lags CPU for -21S option.

CY2280

Document #: 38-07207 Rev. *A

Page 7 of 12

Switching Waveforms

(continued)

APIC

APIC-APIC Clock Skew

CPU_STOP

CPUCLK
(Internal)

PCICLK

(Internal)

PCICLK

(Free-Running)

CPU_STOP

CPUCLK

(External)

PCI_STOP

CPUCLK
(Internal)

PCICLK

(Internal)

PCICLK

PCI_STOP

PCICLK

(External)

(Free-Running)

PWR_DOWN

CPUCLK
(Internal)

PCICLK

(Internal)

PWR_DWN

PCICLK

CPUCLK

(External)

VCO

Crystal

Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock.

CY2280

Document #: 38-07207 Rev. *A

Page 9 of 12

Application Information

Clock traces must be terminated with either series or parallel termination, as is normally done.

Application Circuit

Summary

· A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and C

LOAD

this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different
C

LOAD

is used. Footprints must be laid out for flexibility.

· Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1

In some cases, smaller value capacitors may be required.

· The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic imped-

ance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series
terminating resistor.

Rseries > Rtrace Rout

· Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor

as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF.

· A Ferrite Bead may be used to isolate the Board V

from the clock generator V

island. Ensure that the Ferrite Bead offers

greater than 50

impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout

and Termination Techniques for Cypress Clock Generators" for more details.

· If a Ferrite Bead is used, a 10

F22

F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor

prevents power supply droop during current surges.

CY2280

Document #: 38-07207 Rev. *A

Page 10 of 12

Test Circuit

3, 6, 12, 18, 20, 24, 32, 34, 38, 43

9, 15, 19, 21, 33, 48

DDPCI

, V

DDCORE

LOAD

OUTPUTS

0.1

DDCPU

, V

DDAPIC

Notes:

CY2280

37, 41, 46

Each supply pin must have an individual decoupling capacitor.
All capacitors must be placed as close to the pins as is possible.

DDUSB

, V

DDREF

Ordering Information

Ordering Code

Package Name

Package Type

Operating Range

CY2280PVC-1

O48

48-Pin SSOP

Commercial

CY2280PVC-11S

O48

48-Pin SSOP

Commercial

CY2280PVC-21S

O48

48-Pin SSOP

Commercial

CY2280

Document #: 38-07207 Rev. *A

Page 11 of 12

© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Package Diagram

48-Lead Shrunk Small Outline Package O48

51-85061-B

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: CY2280-11S