3.3V Zero Delay Buffer

CY2308

Cypress Semiconductor Corporation

3901 North First Street

San Jose

CA 95134

408-943-2600

Document #: 38-07146 Rev. *C

Revised June 16, 2004

1CY2308

Features

· Zero input-output propagation delay, adjustable by

capacitive load on FBK input

· Multiple configurations, see "Available CY2308

Configurations" table

· Multiple low-skew outputs

-- Output-output skew less than 200 ps
-- Device-device skew less than 700 ps
-- Two banks of four outputs, three-stateable by two

select inputs

· 10-MHz to 133-MHz operating range
· Low jitter, less than 200 ps cycle-cycle (1, 1H, 4, 5H)
· Space-saving 16-pin 150-mil SOIC package or 16-pin

TSSOP

· 3.3V operation
· Industrial Temperature available

Functional Description

The CY2308 is a 3.3V Zero Delay Buffer designed to distribute

high-speed clocks in PC, workstation, datacom, telecom, and

other high-performance applications.
The part has an on-chip PLL which locks to an input clock

presented on the REF pin. The PLL feedback is required to be

driven into the FBK pin, and can be obtained from one of the

outputs. The input-to-output skew is guaranteed to be less

than 350 ps, and output-to-output skew is guaranteed to be

less than 200 ps.

The CY2308 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the table "Select

Input Decoding." If all output clocks are not required, Bank B

can be three-stated. The select inputs also allow the input

clock to be directly applied to the output for chip and system

testing purposes.
The CY2308 PLL enters a power-down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

µA of current draw. The PLL shuts down in two additional

cases as shown in the "Select Input Decoding" table.
Multiple CY2308 devices can accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.
The CY2308 is available in five different configurations, as

shown in the "Available CY2308 Configurations" table on page

2. The CY23081 is the base part, where the output

frequencies equal the reference if there is no counter in the

feedback path. The CY23081H is the high-drive version of

the 1, and rise and fall times on this device are much faster.
The CY23082 allows the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration and

output frequencies depends on which output drives the

feedback pin. The CY23083 allows the user to obtain 4X and

2X frequencies on the outputs.
The CY23084 enables the user to obtain 2X clocks on all

outputs. Thus, the part is extremely versatile, and can be used

in a variety of applications.
The CY23085H is a high-drive version with REF/2 on both

banks.

FBK
CLKA4
CLKA3
V

GND
CLKB4
CLKB3
S1

Block Diagram

REF

CLKA1
CLKA2

GND

CLKB1
CLKB2

SOIC

Top View

Pin Configuration

REF

CLKA1

CLKA2

CLKA3

CLKA4

FBK

PLL

MUX

Select Input

Decoding

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (2, 3)

Extra Divider (3, 4)

Extra Divider (5H)

CY2308

Document #: 38-07146 Rev. *C

Page 2 of 14

Notes:

1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. Outputs inverted on 23082 and 23083 in bypass mode, S2 = 1 and S1 = 0.
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY23082.

Pin Description

Pin

Signal

Description

REF

[1]

Input reference frequency, 5V tolerant input

CLKA1

[2]

Clock output, Bank A

CLKA2

[2]

Clock output, Bank A

3.3V supply

GND

Ground

CLKB1

[2]

Clock output, Bank B

CLKB2

[2]

Clock output, Bank B

[3]

Select input, bit 2

[3]

Select input, bit 1

CLKB3

[2]

Clock output, Bank B

CLKB4

[2]

Clock output, Bank B

GND

Ground

3.3V supply

CLKA3

[2]

Clock output, Bank A

CLKA4

[2]

Clock output, Bank A

FBK

PLL feedback input

Select Input Decoding

CLOCK A1A4

CLOCK B1B4

Output Source

PLL Shutdown

Three-State

PLL

Driven

Three-State

PLL

Driven

[4]

Driven

[4]

Reference

Driven

PLL

Available CY2308 Configurations

Device

Feedback From

Bank A Frequency

Bank B Frequency

CY23081

Bank A or Bank B

Reference

CY23081H

Bank A or Bank B

Reference

CY23082

Bank A

Reference

Reference/2

CY23082

Bank B

2 X Reference

Reference

CY23083

Bank A

2 X Reference

Reference or Reference

[5]

CY23083

Bank B

4 X Reference

2 X Reference

CY23084

Bank A or Bank B

2 X Reference

CY23085H

Bank A or Bank B

Reference /2

CY2308

Document #: 38-07146 Rev. *C

Page 3 of 14

Zero Delay and Skew Control

To close the feedback loop of the CY2308, the FBK pin can be

driven from any of the eight available output pins. The output

driving the FBK pin will be driving a total load of 7 pF plus any

additional load that it drives. The relative loading of this output

(with respect to the remaining outputs) can adjust the input-

output delay. This is shown in the graph above.
For applications requiring zero input-output delay, all outputs

including the one providing feedback should be equally

loaded. If input-output delay adjustments are required, use the

above graph to calculate loading differences between the

feedback output and remaining outputs.
For zero output-output skew, be sure to load outputs equally.

For further information on using CY2308, refer to the appli-

cation note "CY2308: Zero Delay Buffer."

Maximum Ratings

Supply Voltage to Ground Potential ...............0.5V to +7.0V
DC Input Voltage (Except Ref) .............. 0.5V to V

+ 0.5V

DC Input Voltage REF ........................................... 0.5 to 7V
Storage Temperature.................................. 65°C to +150°C
Junction Temperature...................................................150°C
Static Discharge Voltage

(per MIL-STD-883, Method 3015) ............................. >2000V

REF. Input to CLKA/CLKB Delay v/s Difference in Loading between FBK pin and CLKA/CLKB Pins

Operating Conditions for CY2308SC-XX Commercial Temperature Devices

Parameter

Description

Min.

Max.

Unit

Supply Voltage

3.0

3.6

Operating Temperature (Ambient Temperature)

°C

Load Capacitance, below 100 MHz

Load Capacitance, from 100 MHz to 133 MHz

Input Capacitance

[6]

Power-up time for all V

s to reach minimum specified voltage

(power ramps must be monotonic)

0.05

Note:

6. Applies to both Ref Clock and FBK.

CY2308

Document #: 38-07146 Rev. *C

Page 4 of 14

Electrical Characteristics for CY2308SC-XX Commercial Temperature Devices

Parameter

Description

Test Conditions

Min.

Max.

Unit

Input LOW Voltage

0.8

Input HIGH Voltage

2.0

Input LOW Current

= 0V

50.0

µA

Input HIGH Current

= V

100.0

µA

Output LOW Voltage

[7]

= 8 mA (1, 2, 3, 4)

= 12 mA (1H, 5H)

0.4

Output HIGH Voltage

[7]

= 8 mA (1, 2, 3, 4)

= 12 mA (1H, 5H)

2.4

(PD mode)

Power Down Supply Current REF = 0 MHz

12.0

µA

Supply Current

Unloaded outputs, 100-MHz REF,

Select inputs at V

or GND

45.0

70.0

(1H,5H)

Unloaded outputs, 66-MHz REF

(1, 2, 3, 4)

32.0

Unloaded outputs, 33-MHz REF

(1, 2, 3, 4)

18.0

Note:

7. Parameter is guaranteed by design and characterization. Not 100% tested in production.

CY2308

Document #: 38-07146 Rev. *C

Page 5 of 14

Switching Characteristics for CY2308SC-XX Commercial Temperature Devices

[8]

Parameter

Name

Test Conditions

Min.

Typ.

Max.

Unit

Output Frequency

30-pF load, All devices

100

MHz

Output Frequency

20-pF load, 1H, 5H devices

[9]

133.3

MHz

Output Frequency

15-pF load, 1, 2, 3, 4 devices

133.3

MHz

Duty Cycle

[7]

= t

÷ t

(1, 2, 3, 4, 1H, 5H)

Measured at 1.4V, F

OUT

= 66.66 MHz

30-pF load

40.0

50.0

60.0

Duty Cycle

[7]

= t

÷ t

(1, 2, 3, 4, 1H, 5H)

Measured at 1.4V, F

OUT

<50.0 MHz

15-pF load

45.0

50.0

55.0

Rise Time

[7]

(1, 2, 3, 4)