MPEG Clock Generator with VCXO
CY2410
Cypress Semiconductor Corporation
3901 North First Street
San Jose, CA 95134
408-943-2600
Document #: 38-07317 Rev. *B
Revised December 5, 2002
Features
Benefits
Integrated phase-locked loop (PLL)
Highest performance PLL tailored for multimedia applications
Low-jitter, high-accuracy outputs
Meets critical timing requirements in complex system designs
VCXO with analog adjust
Large 150 ppm range, better linearity
3.3V operation
Application compatibility for a wide variety of designs
Pin-for-pin compatible with MK3727 (-1,-4, -5, -6)
Enables design compatibility
Advanced Features
Benefits
Serial programming interface (CY2410-3 only)
Digital VCXO control
Lower drive strength settings (CY2410-4, -6)
Electromagnetic interference (EMI) reduction for standards
compliance
Matches nonlinear MK3727 VCXO control curve
(CY2410-5, -6)
Drop-in replacement for existing designs
Part
Number
Outputs
Input Frequency Range
Output
Frequencies
VCXO Control
Curve
Other Features
CY2410-1
1
13.5-MHz pullable crystal input per
Cypress specification
1 copy of 27 MHz linear
Pin-for-pin compatible with
MK3727
CY2410-3
1
13.5-MHz pullable crystal input per
Cypress specification
1 copy of 27 MHz linear
Serial programming
interface
CY2410-4
1
13.5-MHz pullable crystal input per
Cypress specification
1 copy of 27 MHz linear
Same as CY2410-1 except
lower drive strength settings
CY2410-5
1
13.5-MHz pullable crystal input per
Cypress specification
1 copy of 27 MHz nonlinear
Matches MK3727 nonlinear
VCXO Control Curve
CY2410-6
1
13.5-MHz pullable crystal input per
Cypress specification
1 copy of 27 MHz nonlinear
Same as CY2410-5 except
lower drive strength
CY2410-1,-4,-5,-6 Logic Block Diagram
13.5 XIN
XOUT
OUTPUT
DIVIDERS
PLL
OSC
VCXO
Q
P
VCO
VDD
VSS
27 MHz
13.5 XIN
XOUT
OUTPUT
DIVIDERS
PLL
OSC
Q
P
VCO
VDD
VSS
27 MHz
CY2410-3 Logic Block Diagram
Serial
Programming
Interface
SCLK
SDAT
Digital VCXO
CY2410
Document #: 38-07317 Rev. *B
Page 2 of 7
Pin Descriptions for CY2410-1, -4, -5, -6
Pin Description for CY2410-3
Pullable Crystal Specifications
[2]
8-pin SOIC
CY2410-1,4,5,6
1
2
3
4
XOUT
XIN
VCXO
27 MHz
VSS
NC or VSS
NC or VDD
5
6
7
8
VDD
8-pin SOIC
CY2410-3
1
2
3
4
XOUT
XIN
SDAT
SCLK
VSS
NC or VSS
27 MHz
5
6
7
8
VDD
Pin Configurations
Name
Pin Number
Description
X
IN
1
Reference crystal input
V
DD
2
Voltage supply
V
CXO
3
Input analog control for V
CXO
V
SS
4
Ground
27 MHz
5
27-MHz clock output
NC/V
DD
6
No Connect or voltage supply
NC/V
SS
7
No Connect or ground
X
OUT
[1]
8
Reference crystal output
Name
Pin Number
Description
X
IN
1
Reference crystal input
V
DD
2
Voltage supply
SDAT
3
Serial data input for DCXO control
V
SS
4
Ground
SCLK
5
Serial clock input for DCXO control
27 MHz
6
27-MHz clock output
NC/V
SS
7
No Connect or ground
X
OUT
[1]
8
Reference crystal output
Parameter
Name
Min.
Typ.
Max.
Unit
Crystal Accuracy
Initial Accuracy at 25C
20
ppm
TS
Temperature Stability
30
ppm
Aging
20
ppm
CR
load
Load Capacitance
14
pF
C
o
Shunt Capacitance
7
pF
C0/C1
C0/C1 Ratio
250
ESR
Equivalent Series Resistance
25
35
Notes:
1.
Float X
OUT
if X
IN
is externally driven.
2.
Reference all other crystal parameters per Ecliptek ECX-5432-13.500M specification.
CY2410
Document #: 38-07317 Rev. *B
Page 3 of 7
Se
rial Programmable Interface Protocol
The CY2410-3 utilizes a two-wire-interface SDAT and SCLK
that operates up to 400 kbits/sec in Read or Write mode. The
basic Write serial format is as follows: start bit; 7-bit device
address (DA); R/W bit; slave clock acknowledge (ACK); 8-bit
memory address (MA); ACK; 8-bit data; ACK; 8-bit data in
MA+1 if desired; ACK; 8-bit data in MA+2; ACK; etc. until stop
bit, as illustrated in Figure 1.
Data Valid
Data is valid when the clock is HIGH, and may only be transi-
tioned when the clock is low as illustrated in Figure 2.
Data Frame
Every new data frame is indicated by a start and stop
sequence, as illustrated in Figure 3.
Start Sequence
A start frame is indicated by SDAT going LOW when SCLK is
HIGH. Every time a start signal is given, the next 8-bit data
must be the device address (7 bits) and a R/W bit (0 for Write),
followed by register address (8 bits) and register data (8 bits).
See Figure 3.
Stop Sequence
A stop frame is indicated by SDAT going HIGH when SCLK is
HIGH. A stop frame frees the bus for writing to another part on
the same bus or writing to another random register
address. See Figure 3.
Acknowledge Pulse
During Write mode, the CY2410-3 will respond with an ACK
pulse after every 8 bits. This is accomplished by pulling the
SDAT line LOW during the next clock cycle after the eighth bit
is shifted in.
Device Address
The 7-bit device address is 1101001.
Register Address
The 8-bit address for the VCXO register is 00010011.
Register Data
The register data can be any value between 00HFFH. As you
increase the value, the capacitance on the X
IN
and X
OUT
pins
will increase, thereby decreasing the xtal frequency.
SDA Write
Start Signal
Device
Address
7-bit
R/W = 0
1-bit
8-bit
Register
Address
Slave
1-bit
ACK
Slave
1-bit
ACK
8-bit
Register
Data
Stop Signal
Slave
1-bit
ACK
Figure 1. Data Frame Architecture
SDAT
SCLK
Data Valid
Transition
to next bit
CLK
LOW
CLK
HIGH
V
IH
V
IL
t
SU
t
DH
Figure 2. Data Valid and Data Transition Periods
START
Transition
to next bit
STOP
SDAT
SCLK
Figure 3. Start and Stop Frame
Figure 4. Duty Cycle Definition; DC = t2/t1
t1
t2
50%
50%
CLK
Figure 5. Rise and Fall Time Definitions: ER = 0.6 x
VDD / t3, EF = 0.6 x VDD / t4
CLK
t3
t4
80%
20%
CY2410
Document #: 38-07317 Rev. *B
Page 4 of 7
Absolute Maximum Conditions
Recommended Operating Conditions
DC Electrical Specifications
AC Electrical Specifications (V
DD
= 3.3V)
[4]
Parameter
Description
Min.
Max.
Unit
V
DD
Supply Voltage
0.5
7.0
V
T
S
Storage Temperature
[3]
65
125
C
T
J
Junction Temperature
125
C
Digital Inputs
V
SS
0.3
V
DD
+ 0.3
V
Digital Outputs referred to V
DD
V
SS
0.3
V
DD
+ 0.3
V
Electrostatic Discharge
2000
V
Parameter
Description
Min.
Typ.
Max.
Unit
V
DD
Operating Voltage
3.135
3.3
3.465
V
T
A
Ambient Temperature
0
70
C
C
LOAD
Max. Load Capacitance
15
pF
f
REF
Reference Frequency
13.5
MHz
Parameter
Name
Description
Min.
Typ.
Max.
Unit
I
OH
Output HIGH Current -1,3,5
V
OH
= V
DD
0.5, V
DD
= 3.3V
12
24
mA
I
OL
Output LOW Current -1,3,5
V
OL
= 0.5, V
DD
= 3.3V
12
24
mA
I
OH
Output HIGH Current -4,6
V
OH
= V
DD
0.5, V
DD
= 3.3V
6
18
mA
I
OL
Output LOW Current -4,6
V
OL
= 0.5, V
DD
= 3.3V
6
18
mA
C
IN
Input Capacitance
7
pF
I
IZ
Input Leakage Current
5
A
f
XO
V
CXO
pullability range
+150
ppm
V
VCXO
V
CXO
input range
0
V
DD
V
I
VDD
Supply Current
30
35
mA
Parameter
[4]
Name
Description
Min.
Typ.
Max.
Unit
DC
Output Duty Cycle
Duty Cycle is defined in Figure 4, 50% of V
DD
45
50
55
%
ER
OR
Rising Edge Rate -1, -3, -5
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, CLOAD = 15 pF See Figure 5.
0.8
1.4
V/ns
ER
OF
Falling Edge Rate -1, -3, -5
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF See Figure 5.
0.7
1.4
V/ns
ER
OR
Rising Edge Rate -4, -6
Output Clock Edge Rate, Measured from 20%
to 80% of V
DD
, CLOAD = 15 pF See Figure 5.
0.7
1.1
V/ns
ER
OF
Falling Edge Rate -4, -6
Output Clock Edge Rate, Measured from 80%
to 20% of V
DD
, CLOAD = 15 pF See Figure 5.
0.7
1.1
V/ns
t
9
Clock Jitter -1, -3, -5
Peak-to-peak period jitter
140
ps
t
9
Clock Jitter -4, -6
Peak-to-peak period jitter
150
ps
t
10
PLL Lock Time
3
ms
Notes:
3.
Rated for ten years.
4.
Not 100% tested.
CY2410
Document #: 38-07317 Rev. *B
Page 5 of 7
Serial Programming Interface Timing Specifications
Parameter
Description
Min.
Max.
Unit
f
SCL
Frequency of SCLK
400
kHz
Start mode time from SDAT LOW to SCLK LOW
0.6
S
CLK
LOW
SCLK LOW period
1.3
S
CLK
HIGH
SCLK HIGH period
0.6
S
t
SU
Data transition to SCLK HIGH
100
ns
t
DH
Data hold (SCLK LOW to data transition)
0
ns
Rise time of SCLK and SDAT
300
ns
Fall time of SCLK and SDAT
300
ns
Stop mode time from SCLK HIGH to SDA HIGH
0.6
s
Stop mode to start mode
1.3
s
Test and Measurement Set-up
0.1
F
V
DD
CLK out
C
LOAD
GND
OUTPUTS
Ordering Information
Ordering Code
Package
Name
Package Type
Operating Range
Operating
Voltage
Features
CY2410SC-1
S8
8-pin SOIC
Commercial
3.3V
Linear VCXO control curve
CY2410SC-1T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
Linear VCXO control curve
CY2410SC-3
S8
8-pin SOIC
Commercial
3.3V
Digital VCXO control
CY2410SC-3T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
Digital VCXO control
CY2410SC-4
S8
8-pin SOIC
Commercial
3.3V
Lower drive strength
(reduced EMI)
CY2410SC-4T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
Lower drive strength
(reduced EMI)
CY2410SC-5
S8
8-pin SOIC
Commercial
3.3V
Matches nonlinear MK3727
VCXO control curve
CY2410SC-5T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
Matches nonlinear MK3727
VCXO control curve
CY2410SC-6
S8
8-pin SOIC
Commercial
3.3V
Lower drive strength version
of CY2410-5
CY2410SC-6T
S8
8-pin SOIC - Tape and Reel
Commercial
3.3V
Lower drive strength version
of CY2410-5
CY2410
Document #: 38-07317 Rev. *B
Page 6 of 7
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Drawing and Dimensions
All product or company names mentioned in this document may be the trademarks of their respective holders.
8-lead (150-mil) SOIC S8
51-85066-*A
CY2410
Document #: 38-07317 Rev. *B
Page 7 of 7
Document History Page
Document Title: CY2410 MPEG Clock Generator with VCXO
Document Number: 38-07317
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
111553
02/12/02
CKN
New Data Sheet
*A
114937
09/24/02
CKN
Added -6 to data sheet, Advance Information to Final
*B
121418
12/06/02
CKN
Updated the Pullable Crystal Specifications table on page 2.
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