MediaClockTM Clock Generator for DVD Players
CY24233
Cypress Semiconductor Corporation
3901 North First Street
San Jose
CA 95134
408-943-2600
Document #: 38-07132 Rev. *B
Revised December 14, 2002
Product Features
Two reference outputs (27.00 MHz)
Two 33.8688-MHz outputs
Two 512fs outputs (22.5792 MHz or 24.576 MHz)
27.00-MHz clock or crystal input
3.3V or 3.0V operation (2.5V functional)
High-drive outputs
16-pin TSSOP package
Product Description
The CY24233 is a clock generator solution that supports DVD
digital disk players. It produces a complete set of clocks
needed to support the entire system. All output clocks are
synthesized from a single 27.00-MHz fundamental cut crystal
or input reference clock. The output clocks are precisely
synthesized to meet the systems low PPM error requirements.
Table 1.
Test
FSEL
27-1Out
27-2Out
33-1Out
33-1Out
512-1Out
512-2Out
0
0
27.00 MHz
2.700 MHz
1.800 MHz
0
1
27.00 MHz
2.700 MHz
3.000 MHz
1
0
27.00 MHz
33.8688 MHz
22.5792 MHz
1
1
27.00 MHz
33.8688 MHz
24.576 MHz
Block Diagram
Pin Configuration
XTI
XT0
PLL
1
PLL
2
FSEL
OS
C
2
2
2
512-1Out, 512-2Out
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TEST
FSEL
VDD
VSS
512-1Out
512-2Out
VDD
VSS
VDD
VSS
XT1
XT0
33-1Out or N/C
1
33-2Out or N/C
1
27-2Out or N/C
1
27-1Out or N/C
1
27-1Out, 27-2Out
33-1Out, 33-2Out
OSC
CY24233
Document #: 38-07132 Rev. *B
Page 2 of 5
FSEL Switching Synchronization
The FSEL input is used to select the frequency of the clocks
on the 512-1Out and 512-2Out pins. The device contains
internal clock edge synchronization to insure that when the
state of this pin is changed while the clocks are running no
short (runt) or long (stretched) clocks will occur in the output
streams. This is to say that the transitions will be made at a
naturally occurring clock edge of the former clocks period and
the cycle immediately after the change will be of a full newly
selected clocks period and duty cycle.
Notes:
1.
Part may be operated with Pins 3,4,13,15 soldered to pads on PCB with no PCB trace connected to these pads, i.e., floating.
2.
Table Nomenclature: All pin numbers with an asterisks (*) immediately after them indicates that they have an internal pull-up resistor to ensure that they will
be sensed as a logic HIGH even if no external circuitry is attached to them. I = Input pins, O = Output pins and PWR = Power connection pins.
Pin Description
[1,2]
Pin Number Pin Name
I/O
Pin Description
3,4
27-1Out
27-2Out
O
3.3V fixed-frequency 27.00-MHz clock outputs. See Table 1 on page 1 for frequency
selection for test mode functionality.
9,10
512-1Out
512-2Out
O
3.3V or 3.0V fixed frequency clock outputs. See Table 1 on page 1 for frequency selection.
13,15
33-1Out
33-2Out
O
3.3V fixed frequency 33.8688-MHz clock outputs. See Table 1 on page 1 for frequency
selection for test mode functionality.
14*
FSEL
I
Frequency selection input. This pin controls the frequency that is present on two 512 output
clock pins.
8
XTO
O
On-chip reference oscillator pin. Drives an external crystal. When an externally generated
reference signal is used at XTI, this pin remains unconnected. Bypass with a proper capaci-
tance to ground to match the external crystal's load capacitance.
7
XTI
I
On-chip reference oscillator input pin. Requires either an external crystal (nominally 27
MHz) or externally generated reference signal. Bypass with a proper capacitance to ground to
match the external crystal's load capacitance.
1, 5, 12
VDD
PWR
3.3V or 3.0V power supply.
2,6,11
VSS
PWR
Device ground for all circuitry.
16
TEST
I
Internal pull up. If this input pin is asserted low, it will set this device into a test mode. See
Table 1 on page 1.
Table 2. Maximum Lumped Capacitative Output Loads
Clock
Max Load
Units
27-1Out
40
pF
27-2Out
25
pF
33-1Out,33-2Out, 512-1Out,512-2Out
15
pF
Finish Cycle
Wait
Start at Full Cycle
FSEL Switching Synchronization
CY24233
Document #: 38-07132 Rev. *B
Page 3 of 5
Maximum Ratings
[3]
Maximum Input Voltage Relative to V
SS
: ............. V
SS
0.3V
Maximum Input Voltage Relative to V
DD
: ............. V
DD
+ 0.3V
Storage Temperature: .................................65C to +150C
Operating Temperature: ................................ 20C to +85C
Maximum ESD protection ............................................... 2KV
Maximum Power Supply: ................................................5.5V
Operating Voltage: ...................................................2.53.6V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, V
in
and V
out
should be constrained to the
range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
DC Parameters
(V
DD
= 3.3V 10%, T
A
= 10C to +75C or V
DD
= 3.0V 10%, T
A
= 20C to +85C)
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
V
IL
Input Low Voltage
[3]
0.8
Vdc
V
IH
Input High Voltage
2.0
Vdc
I
IL
Input Low Current
For internal Pull-up resistors
[3,5]
I
IL
measured at V
IN
= GND, I
IH
measured
at V
IN
= V
DD
18
8
3.5
A
I
IH
Input High Current
5
A
V
HYS
Input Hysteriss
[3]
250
410
750
mV
I
dd3.3V
Dynamic Supply Current
Test = 1, FSEL=1
[6]
48
60
mA
I
dd3.0V
Dynamic Supply Current
Test = 1, FSEL=1
[6]
40
50
mA
V
OL
Output Low Voltage
I
OL
= 4.0 mA
0.4
V
V
OH
Output High Voltage
I
OH
= 4.0 mA
2.4
V
C
in
Input Pin Capacitance
5
pF
C
out
Output Pin Capacitance
6
pF
L
pin
Pin Inductance
7
nH
C
xtal
Crystal Pin Capacitance
5
pF
AC Parameters
(V
DD
= 3.3V 10%, T
A
= 10C to +75C)
[7]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
T
R
Rise Time
All clocks at rated load
[8]
2
5
ns
T
F
Fall Time
All clocks at rated load
[8]
2
5
ns
T
PU
Power up to Stable Output
All Output Clocks
s
3
ms
T
DC1
Clock Duty Cycle (all output clocks)
All clocks at rated load
[9]
45
50
55
%
T
j2
Clock Jitter (33-1Out,33-2Out)
Cycle to cycle jitter
(PeakPeak, 10,000 cycles )
All clocks at rated load
[9]
150
200
ps
T
j2
Clock Jitter (512-1Out,512-2Out)
150
200
ps
T
j3
Clock Jitter (27-1Out,27-2Out)
350
ps
T
XS
Crystal Oscillator Start-up Time
40
s
AC Parameters
(V
DD
= 3.0V 10%, T
A
= 20C to +85C, only 512-1Out and 512-2out Loaded)
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
T
R
Rise Time
All clocks at rated load
[8]
2.5
5
ns
T
F
Fall Time
All clocks at rated load
[8]
2.5
5
ns
T
PU
Power-up to Stable Output
All output clocks
3
ms
Notes:
3.
Multiple Supplies:The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4.
Applicable to input signal: FSEL and Test pins.
5.
Although internal pull-up resistors have a typical value of 400K, this value may vary between 200K and 800K.
6.
All outputs loaded as perTable 2 on page 2.
7.
Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs.
8.
Measured between 0.2* V
DD
and 0.8*V
DD
V.
9.
Triggering is done at 1.5V.
CY24233
Document #: 38-07132 Rev. *B
Page 4 of 5
Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Package Diagram
MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the
trademarks of their respective holders.
T
DC1
Clock Duty Cycle (all output
clocks)
All clocks at rated load
9
40
50
60
%
T
j2
Clock Jitter (512-1Out,512-2Out)
Cycle to cycle jitter
(Peak-to-Peak, 10,000 cycles)
All clocks at rated load
9
200
250
ps
T
XS
Crystal Oscillator Start-up Time
40
s
AC Parameters
(V
DD
= 3.0V 10%, T
A
= 20C to +85C, only 512-1Out and 512-2out Loaded) (continued)
Parameter
Description
Conditions
Min.
Typ.
Max.
Units
Ordering Information
Part Number
Package Type
Product Flow
CY24233ZC
16-pin TSSOP
Commercial, 20
to 85
C
CY24233ZCT
16-pin TSSOPTape and Reel
Commercial, 20
to 85
C
16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091
CY24233
Document #: 38-07132 Rev. *B
Page 5 of 5
Document Title: CY24233 MediaClockTM Clock Generator for DVD Players
Document Number: 38-07132
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
110596
11/29/01
DMG
New Data Sheet
*A
116543
08/22/02
CKN
Changed values in DC and AC parameters for operation at 3.0V 10%, and
ambient temp. range from 20
C to 85
C: jitter, rise time, fall time
Explictly allow use with only 512 outputs loaded.
*B
122795
12/14/02
RBI
Power up Requirements to Operating Conditions Information
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