Spread Spectrum Clock Generator
CY25811/12/14
Cypress Semiconductor Corporation
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Document #: 38-07112 Rev. *E
Revised June 03, 2004
Features
4- to 32-MHz input frequency range
4- to 128-MHz output frequency range
Accepts clock, crystal, and resonator inputs
1x, 2x, and 4x frequency multiplication:
-- CY25811: 1x; CY25812: 2x; CY25814: 4x
Center and down spread modulation
Low power dissipation:
-- 3.3V = 52 mW-typ @ 6MHz
-- 3.3V = 60 mW-typ @ 12MHz
-- 3.3V = 72 mW-typ @ 24MHz
Low cycle-to cycle jitter:
-- 8 MHz = 450 ps-max
-- 16 MHz = 225 ps-max
-- 32 MHz = 150 ps-max
Available in 8-pin SOIC and TSSOP packages
Commercial and industrial temperature ranges
Applications
Printers and MFPs
LCD panels
Digital copiers
PDAs
CD-ROM, VCD, and DVD
Networking, LAN/WAN
Scanners
Modems
Embedded digital systems
Benefits
Peak EMI reduction by 8 to 16 dB
Fast time to market
Cost reduction
Block Diagram
Pin Configuration
S1
S0
FRSEL
300K
VDD
VSS
XIN
XOUT
SSCLK
8pF
REFERENCE
DIVIDER
PD and
CP
LF
VCO
VCO
COUNTE
R
COUNTER
and
MUX
INPUT
DECODER
LOGIC
1
7
8
2
5
MODULATION
CONTROL
3
4
6
8pF
1
2
3
4
8
7
6
5
XIN/CLKIN
VSS
S1
S0
XOUT
VDD
FRSEL
SSCLK
CY25811
CY25812
CY25814
8-pin SOIC/TSSOP
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 2 of 11
Functional Description
The CY25811/12/14 products are Spread Spectrum Clock
Generator (SSCG) ICs used for the purpose of reducing
electromagnetic interference (EMI) found in today's
high-speed digital electronic systems.
The devices use a Cypress proprietary phase-locked loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the input clock. By
frequency modulating the clock, the measured EMI at the
fundamental and harmonic frequencies is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory agency requirements and
improve time to market without degrading system perfor-
mance.
The input frequency range is 4 to 32 MHz and accepts clock,
crystal and ceramic resonator inputs. The output clock can be
selected to produce 1x, 2x, or 4x multiplication of the input
frequency with Spread Spectrum Frequency Modulation.
The use of 2x or 4x frequency multiplication eliminates the
need for higher order crystals and enables the user to
generate up to 128-MHz Spread Spectrum Clock (SSC) by
using only first order crystals. This will reduce the cost while
improving the system clock accuracy, performance and
complexity.
Center Spread or Down Spread frequency modulation can be
selected by the user based on four discrete values of
Spread % for each Spread Mode with the option of a
Non-Spread mode for system test and verification purposes.
The CY25811/12/14 products are available in an 8-pin SOIC
(150-mil.) package with a Commercial operating temperature
range of 0 to 70
C and Industrial Temperature range of 40 to
85C. Refer to CY25568 for multiple clock output options such
as modulated and unmodulated clock outputs or Power-down
function. For Automotive applications, refer to
CY25811/12/14SE data sheet.
Input Frequency Range and Selection
The CY25811/12/14 input frequency range is 4 to 32 MHz.
This range is divided into three segments and controlled by
3-Level FRSEL pin as given in Table 1.
Spread% Selection
The CY25811/12/14 SSCG products provide Center-Spread,
Down-Spread and No-Spread functions. The amount of
Spread% is selected by using 3-Level S0 and S1 digital inputs
and Spread% values are given in Table 2.
Pin Definitions
Pin No.
Name
Type
Description
1
Xin/CLK
Crystal, ceramic resonator or clock input pin.
2
VSS
Power supply ground.
3
S1
Digital Spread% control pin. 3-Level input (H-M-L). Default = M.
4
S0
Digital Spread% control pin. 3-Level input (H-M-L). Default = M.
5
SSCLK
Spread Spectrum output clock.
6
FRSEL
Input frequency range selection digital control input. 3-Level input (H-M-L). Default = M.
7
VDD
Positive power supply.
8
XOUT
Crystal or ceramic resonator output pin.
Table 1. Input Frequency Selection
FRSEL
Input Frequency Range
0
4.0 to 8.0 MHz
1
8.0 to 16.0 MHz
M
16.0 to 32.0 MHz
Table 2. Spread% Selection
XIN
(MHz)
FRSEL
S1 = 0
S0 = 0
S1 = 0
S0 = M
S1 = 0
S0 = 1
S1 = M
S0 = 0
S1 = 1
S0 = 1
S1 = 1
S0 = 0
S1 = M
S0 = 1
S1 = 1
S0 = M
S1 = M
S0 = M
Center
(%)
Center
(%)
Center
(%)
Center
(%)
Down
(%)
Down
(%)
Down
(%)
Down
(%)
No Spread
4-5
0
1.4
1.2
0.6
0.5
3.0
2.2
1.9
0.7
0
5-6
0
1.3
1.1
0.5
0.4
2.7
1.9
1.7
0.6
0
6-7
0
1.2
0.9
0.5
0.4
2.5
1.8
1.5
0.6
0
7-8
0
1.1
0.9
0.4
0.3
2.3
1.7
1.4
0.5
0
8-10
1
1.4
1.2
0.6
0.5
3.0
2.2
1.9
0.7
0
10-12
1
1.3
1.1
0.5
0.4
2.7
1.9
1.7
0.6
0
12-14
1
1.2
0.9
0.5
0.4
2.5
1.8
1.5
0.6
0
14-16
1
1.1
0.9
0.4
0.3
2.3
1.7
1.4
0.5
0
16-20
M
1.4
1.2
0.6
0.5
3.0
2.2
1.9
0.7
0
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 3 of 11
3-Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High "1", Low "0" and
Middle "M". With this 3-Level digital input logic, the 3-Level
Logic is able to detect 9 different logic states.
S0, S1 and FRSEL pins include an on chip 20K (10K/10K)
resistor divider. No external application resistors are needed
to implement the 3-Level logic levels as shown below:
Logic Level "0": 3Level logic pin connected to GND.
Logic Level "M": 3Level logic pin left floating (no connection).
Logic Level "1": 3Level logic pin connected to V
DD
.
Figure 1 illustrates how to implement 3Level Logic.
Modulation Rate
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax) and
minimum frequency of the clock (fmin) determine this band of
frequencies. The time required to transition from fmin to fmax
and back to fmin is the period of the Modulation Rate. The
Modulation Rate of SSCG clocks are generally referred to in
terms of frequency, or
fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
In the case of CY25811/2/4 devices, the (Spread Spectrum)
modulation Rate, fmod, is given by the following formula:
fmod = fin/DR
where; fmod is the Modulation Rate, fin is the Input Frequency
and DR is the Divider Ratio as given in Table 3. Notice that
Input Frequency Range is set by FRSEL.
Input and Output Frequency Selection
The relationship between input frequency versus output
frequency in terms of device selection and FRSEL setting is
given in Table 4. As shown, the input frequency range is
selected by FRSEL and is the same for CY25811, CY25812,
and CY25814. The selection of CY25811 (1x), CY25812 (2x)
or CY25814 (4x) determines the frequency multiplication at
the output (SSCLK, Pin 5) with respect to input frequency
(XIN, Pin-1).
20-24
M
1.3
1.1
0.5
0.4
2.7
1.9
1.7
0.6
0
24-28
M
1.2
0.9
0.5
0.4
2.5
1.8
1.5
0.6
0
28-32
M
1.1
0.9
0.4
0.3
2.3
1.7
1.4
0.5
0
Table 2. Spread% Selection (continued)
XIN
(MHz)
FRSEL
S1 = 0
S0 = 0
S1 = 0
S0 = M
S1 = 0
S0 = 1
S1 = M
S0 = 0
S1 = 1
S0 = 1
S1 = 1
S0 = 0
S1 = M
S0 = 1
S1 = 1
S0 = M
S1 = M
S0 = M
LOGIC
MIDDLE (M)
LOGIC
HIGH (H)
S0, S1
and
FRSEL
to VDD
S0, S1
and
FRSEL
UNCONNECTED
S0, S1
and
FRSEL
to VSS
VSS
LOGIC
LOW (0)
Figure 1. 3Level Logic
Table 3. Modulation Rate Divider Ratios
FRSEL
Input Frequency Range
(MHz)
Divider Ratio
(DR)
0
4 to 8
128
1
8 to 16
256
M
16 to 32
512
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 4 of 11
Table 4. Input and Output Frequency Selection
Input Frequency Range
(MHz)
FRSEL
Product
Multiplication
Output Frequency Range
(MHz)
4 to 8
0
CY25811
1x
4 to 8
8 to 16
1
CY25811
1x
8 to 16
16 to 32
M
CY25811
1x
16 to 32
4 to 8
0
CY25812
2x
8 to 16
8 to 16
1
CY25812
2x
16 to 32
16 to 32
M
CY25812
2x
32 to 64
4 to 8
0
CY25814
4x
16 to 32
8 to 16
1
CY25814
4x
32 to 64
16 to 32
M
CY25814
4x
64 to 128
Absolute Maximum Conditions
(both Commercial and Industrial Grades)
[1,2]
Parameter
Description
Condition
Min.
Max.
Unit
V
DD
Supply Voltage
0.5
4.6
V
V
IN
Input Voltage
Relative to V
SS
0.5
V
DD
+ 0.5
VDC
T
S
Temperature, Storage
Non Functional
65
150
C
T
A1
Temperature, Operating Ambient
Functional, C-Grade
0
70
C
T
A2
Temperature, Operating Ambient
Functional, I-Grade
40
85
C
T
J
Temperature, Junction
Functional
150
C
ESD
HBM
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
V
UL-94
Flammability Rating
@1/8 in.
V0
MSL
Moisture Sensitivity Level
1
DC Electrical Specifications
(Commercial Grade)
Parameter
Description
Condition
Min.
Max.
Unit
V
DD
3.3 Operating Voltage
3.3 5%
3.135
3.465
V
V
IL
Input Low Voltage
S0, S1 and FRSEL Inputs
0
0.15V
DD
V
V
IM
Input Middle Voltage
S0, S1 and FRSEL Inputs
0.40V
DD
0.60V
DD
V
V
IH
Input High Voltage
S0, S1 and FRSEL Inputs
0.85V
DD
V
DD
V
V
OL1
Output Low Voltage
I
OL
= 4 ma, SSCLK Output
0.4
V
V
OL2
Output Low Voltage
I
OL
= 10 ma, SSCLK Output
1.2
V
V
OH1
Output High Voltage
I
OH
= 4 ma, SSCLK Output
2.4
V
V
OH2
Output High Voltage
I
OH
= 6 ma, SSCLK Output
2.0
V
C
IN1
Input Pin Capacitance
XIN (Pin 1) and XOUT (Pin 8)
6.0
9.0
pF
C
IN2
Input Pin Capacitance
All Digital Inputs
3.5
6.0
pF
C
L
Output Load Capacitor
SSCLK Output
15
pF
I
DD1
Dynamic Supply Current
Fin = 12 MHz, no load
25
mA
I
DD2
Dynamic Supply Current
Fin = 24 MHz, no load
30
mA
I
DD3
Dynamic Supply Current
Fin = 32 MHz, no load
35
mA
Notes:
1. Operation at any Absolute Maximum Rating is not implied.
2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up.
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 5 of 11
AC Electrical Specifications
(Commercial Grade)
Parameter
Description
Condition
Min.
Max.
Unit
F
IN
Input Frequency Range
Clock, Crystal or Ceramic Resonator Input
4
32
MHz
T
R1
Clock Rise Time
SSCLK, CY25811 and CY25812
2.0
5.0
ns
T
F1
Clock Fall Time
SSCLK, CY25811 and CY25812
2.0
4.4
ns
T
R2
Clock Rise Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
T
F2
Clock Fall Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
T
DCIN
Input Clock Duty Cycle
XIN
40
60
%
T
DCOUT
Output Clock Duty Cycle
SSCLK
40
60
%
T
CCJ1
Cycle-to-Cycle Jitter, Spread on
Fin = 4 MHz, Fout = 4 MHz, CY25811
800
ps
T
CCJ2
Cycle-to-Cycle Jitter, Spread on
Fin = 8 MHZ, Fout = 8 MHz, CY25811
450
ps
T
CCJ3
Cycle-to-Cycle Jitter, Spread on
Fin = 8 MHz, Fout = 16 MHz, CY25812
400
ps
T
CCJ4
Cycle-to-Cycle Jitter, Spread on
Fin = 16 MHz, Fout = 32 MHz, CY25812
380
ps
T
CCJ5
Cycle-to-Cycle Jitter, Spread on
Fin = 16 MHz, Fout = 64 MHz, CY25814
380
ps
T
CCJ6
Cycle-to-Cycle Jitter, Spread on
Fin = 32 MHz, Fout = 128 MHz, CY25814
380
ps
T
SU
PLL Lock Time
Fom V
DD
3.0V to valid SSCLK
3
ms
DC Electrical Specifications
(Industrial Grade)
Parameter
Description
Condition
Min.
Max.
Unit
V
DD
3.3 Operating Voltage
3.3 5%
3.135
3.465
V
V
IL
Input Low Voltage
S0, S1 and FRSEL Inputs
0
0.13V
DD
V
V
IM
Input Middle Voltage
S0, S1 and FRSEL Inputs
0.40V
DD
0.60V
DD
V
V
IH
Input High Voltage
S0, S1 and FRSEL Inputs
0.85V
DD
V
DD
V
V
OL1
Output Low Voltage
I
OL
= 4 ma, SSCLK Output
0.4
V
V
OL2
Output Low Voltage
I
OL
= 10 ma, SSCLK Output
1.2
V
V
OH1
Output High Voltage
I
OH
= 4 ma, SSCLK Output
2.4
V
V
OH2
Output High Voltage
I
OH
= 6 ma, SSCLK Output
2.0
V
C
IN1
Input Pin Capacitance
XIN (Pin 1) and XOUT (Pin 8)
6.0
9.0
pF
C
IN2
Input Pin Capacitance
All Digital Inputs
3.5
6.0
pF
C
L
Output Load Capacitor
SSCLK Output
15
pF
I
DD1
Dynamic Supply Current
Fin = 12 MHz, no load
26
mA
I
DD2
Dynamic Supply Current
Fin = 24 MHz, no load
32
mA
I
DD3
Dynamic Supply Current
Fin = 32 MHz, no load
37
mA
AC Electrical Specifications
(Industrial Grade)
Parameter
Description
Condition
Min.
Max.
Unit
F
IN
Input Frequency Range
Clock, Crystal or Ceramic Resonator Input
4
32
MHz
T
R1
Clock Rise Time
SSCLK, CY25811 and CY25812
2.0
5.0
ns
T
F1
Clock Fall Time
SSCLK, CY25811 and CY25812
2.0
4.4
ns
T
R2
Clock Rise Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
T
F2
Clock Fall Time
SSCLK, only CY25814 when FRSEL = M
1.0
2.2
ns
T
DCIN
Input Clock Duty Cycle
XIN
40
60
%
T
DCOUT
Output Clock Duty Cycle
SSCLK
40
60
%
T
CCJ1
Cycle-to-Cycle Jitter, Spread on
Fin = 6MHz, CY25811/12/14
650
ps
T
CCJ2
Cycle-to-Cycle Jitter, Spread on
Fin = 12MHZ, CY25811/12/14
400
ps
T
CCJ3
Cycle-to-Cycle Jitter, Spread on
Fin = 24MHz, CY25811/12/14
400
ps
T
SU
PLL Lock Time
From V
DD
3.0V to valid SSCLK
4
ms
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 6 of 11
Characteristic Curves
The following curves demonstrate the characteristic behavior
of the CY25811/12/14 when tested over a number of environ-
mental and application-specific parameters. These are typical
performance curves and are not meant to replace any
parameter specified in DC and AC Specification tables.
0
100
200
300
400
500
600
4
8
12
16
20
24
28
32
Input Frequency (MHz)
CCJ (ps)
1.75
2
2.25
2.5
2.75
-40
-25
-10
5
20
35
50
65
80
95
110
125
Temp (C)
BW %
6.0 MHz
32.0 MHz
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
VDD (volts)
BW (%)
4.0 MHz
8.0 MHz
10
12
14
16
18
20
22
24
26
28
30
4
4.5
5
5.5
6
6.5
7
7.5
8
Frequency (MHz), no load, normalized to FRSEL = 0, (4 - 8 MHz).
I
DD (mA)
FRSEL = 0
4 - 8 MHz
FRSEL = 1
8 - 16 MHz
FRSEL = M
16 - 32 MHz
Jitter vs. Input Frequency (No Load)
Bandwidth % vs. Temperature
IDD vs. Frequency (FRSEL = 0, 1, M)
Bandwidth % vs. VDD
Figure 2. Characteristic Curves
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 7 of 11
SSCG Profiles
CY25811/12/14 SSCG products use a non-linear "optimized"
frequency profile as shown In Figure 3. The use of Cypress
proprietary "optimized" frequency profile maintains flat energy
distribution over the fundamental and higher order harmonics.
This results in additional EMI reduction in electronic systems.
Xin = 6.0 MHz
SSCLK1 = 6.0 MHz
S1, S0 = 0
FRSEL = 0
P/N = CY25811
Xin = 24.0 MHz
SSCLK1 = 24.0 MHz
S1, S0 = 0
FRSEL = M
P/N = CY25811
Xin = 12.0 MHz
SSCLK1 = 48.0 MHz
S1, S0 = 0
FRSEL = 1
P/N = CY25814
Xin = 24.0 MHz
SSCLK1 = 96.0 MHz
S1, S0 = 0
FRSEL = M
P/N = CY25814
Figure 3. Spread Spectrum Profiles (Frequency vs. Time)
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 8 of 11
Application Schematic
VDD
C2
C3
27 pF
1
8
Y1
25 MHz
FRSEL
VSS
S1
S0
XIN
XOUT
SSCLK
VDD
CY25811
CY25812
CY25814
6
4
3
5
0.1 uF
C3
27 pF
25 MHz (CY25811)
50 MHz (CY25812)
100 MHz (CY25814)
N/C
7
2
Ordering Information
Part Number
Package Type
Product Flow
CY25811SC
8-pin SOIC
Commercial, 0
to 70C
CY25811SCT
8-pin SOIC Tape and Reel
Commercial, 0
to 70C
CY25811SI
8-pin SOIC
Industrial, 40 to 85C
CY25811SIT
8-pin SOIC Tape and Reel
Industrial, 40 to 85C
CY25811ZC
8-pin TSSOP
Commercial, 0
to 70C
CY25811ZCT
8-pin TSSOP Tape and Reel
Commercial, 0
to 70C
CY25812SC
8-pin SOIC
Commercial, 0
to 70C
CY25812SCT
8-pin SOIC Tape and Reel
Commercial, 0
to 70C
CY25812SI
8-pin SOIC
Industrial, 40 to 85C
CY25812SIT
8-pin SOIC Tape and Reel
Industrial, 40 to 85C
CY25812ZC
8-pin TSSOP
Commercial, 0
to 70C
CY25812ZCT
8-pin TSSOP Tape and Reel
Commercial, 0
to 70C
CY25814SC
8-pin SOIC
Commercial, 0
to 70C
CY25814SCT
8-pin SOIC Tape and Reel
Commercial, 0
to 70C
CY25814SI
8-pin SOIC
Industrial, 40 to 85C
CY25814SIT
8-pin SOIC Tape and Reel
Industrial, 40 to 85C
CY25814ZC
8-pin TSSOP
Commercial, 0
to 70C
CY25814ZCT
8-pin TSSOP Tape and Reel
Commercial, 0
to 70C
Lead Free Devices
CY25811SXC
8-pin SOIC
Commercial, 0
to 70C
CY25811SXCT
8-pin SOIC Tape and Reel
Commercial, 0
to 70C
CY25811SXI
8-pin SOIC
Industrial, 40 to 85C
CY25811SXIT
8-pin SOIC Tape and Reel
Industrial, 40 to 85C
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 9 of 11
Package Drawing and Dimensions
CY25811ZXC
8-pin TSSOP
Commercial, 0
to 70C
CY25811ZXCT
8-pin TSSOP Tape and Reel
Commercial, 0
to 70C
CY25812SXC
8-pin SOIC
Commercial, 0
to 70C
CY25812SXCT
8-pin SOIC Tape and Reel
Commercial, 0
to 70C
CY25812SXI
8-pin SOIC
Industrial, 40 to 85C
CY25812SXIT
8-pin SOIC Tape and Reel
Industrial, 40 to 85C
CY25812ZXC
8-pin TSSOP
Commercial, 0
to 70C
CY25812ZXCT
8-pin TSSOP Tape and Reel
Commercial, 0
to 70C
CY25814SXC
8-pin SOIC
Commercial, 0
to 70C
CY25814SXCT
8-pin SOIC Tape and Reel
Commercial, 0
to 70C
CY25814SXI
8-pin SOIC
Industrial, 40 to 85C
CY25814SXIT
8-pin SOIC Tape and Reel
Industrial, 40 to 85C
CY25814ZXC
8-pin TSSOP
Commercial, 0
to 70C
CY25814ZXCT
8-pin TSSOP Tape and Reel
Commercial, 0
to 70C
Ordering Information
(continued)
SEATING PLANE
PIN 1 ID
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.189[4.800]
0.196[4.978]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
0~8
0.016[0.406]
0.010[0.254]
X 45
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.004[0.102]
1
4
5
8
3. REFERENCE JEDEC MS-012
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
4. PACKAGE WEIGHT 0.07gms
51-85066-*C
8-lead (150-Mil) SOIC S8
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 10 of 11
Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document
are the trademarks of their respective holders.
8
PIN 1 ID
SEATING
PLANE
1
BSC.
BSC
0-8
PLANE
GAUGE
2.90[0.114]
1.10[0.043] MAX.
0.65[0.025]
0.20[0.008]
0.05[0.002]
6.50[0.256]
0.076[0.003]
6.25[0.246]
4.50[0.177]
4.30[0.169]
3.10[0.122]
0.15[0.006]
0.19[0.007]
0.30[0.012]
0.09[[0.003]
0.25[0.010]
0.70[0.027]
0.50[0.020]
0.95[0.037]
0.85[0.033]
DIMENSIONS IN MM[INCHES] MIN.
MAX.
8-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z8
51-85093-*A
CY25811/12/14
Document #: 38-07112 Rev. *E
Page 11 of 11
Document History Page
Document Title: CY25811/12/14 Spread Spectrum Clock Generator
Document Number: 38-07112
REV. ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
107516
06/14/02
NDP
Converted from IMI to Cypress
*A
108002
06/29/02
NDP
Deleted Junction Temp. in Absolute Maximum Ratings
*B
121578
01/29/03
RGL
Converted from Word to FrameMaker
Added 8-pin TSSOP package in Commercial Temp. only
Added an Industrial Temperature Range to all existing 8-pin SOIC packages
*C
125550
05/14/03
RGL
Changed IDD values from 19.6/22/27.2 to 25/30/35 in Commercial Grade DC Specs
table
Changed IDD values from 24/26.5/33 to 26/32/37 in Industrial grade DC Specs table
Changed T
CCJ1/2
values from 675/260 to 800/450 in Commercial grade AC Specs table
Changed T
CCJ1
value from 350 to 650 in Industrial grade AC Specs table
*D
131941
12/24/03
RGL
Removed automotive in the Applications section
Changed the Output Clock Duty Cycle (T
DCOUT
) from min. 45 and max. 55 to 40 and
60% respectively for both industrial and commercial grade
Changed the min. Input Low Voltage (V
IL
) from 0.15V
DD
to 0.13V
DD
Removed preliminary from the industrial AC/DC Electrical Specifications table
*E
231057
See ECN
RGL
Added Lead Free Devices
PDF 
ZIP